CN107688540A - A kind of method that long-range Debug is carried out using BMC - Google Patents

A kind of method that long-range Debug is carried out using BMC Download PDF

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Publication number
CN107688540A
CN107688540A CN201710813190.2A CN201710813190A CN107688540A CN 107688540 A CN107688540 A CN 107688540A CN 201710813190 A CN201710813190 A CN 201710813190A CN 107688540 A CN107688540 A CN 107688540A
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CN
China
Prior art keywords
cpu
bmc
pch
master
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710813190.2A
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Chinese (zh)
Inventor
张国强
赵伟涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhengzhou Yunhai Information Technology Co Ltd
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Zhengzhou Yunhai Information Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Zhengzhou Yunhai Information Technology Co Ltd filed Critical Zhengzhou Yunhai Information Technology Co Ltd
Priority to CN201710813190.2A priority Critical patent/CN107688540A/en
Publication of CN107688540A publication Critical patent/CN107688540A/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3648Software debugging using additional hardware

Abstract

The present invention discloses a kind of method that long-range Debug is carried out using BMC, is related to mainboard circuit design field;Increase corresponding logic between mainboard BMC and CPU/PCH, BMC is connected one to one master signal and CPU/PCH ends by logic circuit, BMC and the master signal transmission direction at CPU/PCH ends are controlled by logic circuit further according to situation, make master signal flow direction correct, realize and long-range debug is carried out to CPU/PCH;Server master board external connector interface quantity can be reduced, reduces design cost, while CPU/PCH remote analysis can be reduced the dependence to special Debug instruments and improve Debug efficiency.

Description

A kind of method that long-range Debug is carried out using BMC
Technical field
The present invention discloses a kind of Debug method, is related to mainboard circuit design field, and specifically one kind utilizes BMC The method for carrying out long-range Debug.
Background technology
To ensure the high reliability of server, it usually needs specific external interface is reserved on mainboard, so that outside is adjusted Trial work tool is connected on CPU/PCH when mainboard breaks down.By accessing CPU/PCH internal resources, register value shape is obtained State, it can greatly provide debug efficiency with abnormal information in Fast Discovery System.
Mainly there is two ways to be used for CPU/PCH in server industries at present to access and system debug:One kind is to utilize ITP instruments are accessed by XDP interfaces, ITP instruments be CPU producers exploitation it is special to CPU/PCH carry out debug instrument, ITP It is that the inter access to CPU/PCH can be achieved by jtag bus when instrument accesses XDP connectors;
It is another then by USB3.0 using DCI interface protocols realize, which is similar with XDP/ITP schemes, simply interface shape State is changed to USB3.0, while is realized using DCI interface protocols, in addition, it is also necessary to which adapter makees Debug instruments.
, the shortcomings that obvious be present in above-mentioned current existing technical scheme:
Two ways is required for special external interface;, it is necessary to special testing tool during Debug;It can not remotely access;
The first scheme:XDP belongs to high-density connector, and cost is higher;Connector is normally at cabinet inside, is not easy conveniently to visit Ask, moreover, it is desirable to special ITP instruments;
Second scheme:Need to take USB3.0 interfaces, on the mainboard of some not reserved USB3.0 interfaces and do not apply to;Sending out During raw catastrophe failure, USB3.0 meeting generating function failures, there is situation about can not access;Need special Debug adapters.
The present invention provides a kind of method that long-range Debug is carried out using BMC, by increasing between mainboard BMC and CPU/PCH Add corresponding hardware circuit, dependence of the server master board to external connector interface and debug instruments can be reduced, reduction is designed to This, while Debug efficiency can be improved to CPU/PCH remote analysis.
DCI, Direct Connect Interface, a kind of interface protocol.
JTAG, Joint Test Action Group, joint test working group, a kind of bus protocol.
BMC(Baseboard Management Controller, baseboard management controller.
PCH, Platform Control Hub, platform courses center.
The content of the invention
Demand and weak point of the present invention for the development of current technology, there is provided a kind of to carry out long-range Debug's using BMC Method.
A kind of method that long-range Debug is carried out using BMC, is set up between BMC the and CPU/PCH ends of server master board and patrolled Circuit is collected, BMC is connected one to one master signal and CPU/PCH ends by logic circuit, passes through logic electricity further according to situation Road controls BMC and the master signal transmission direction at CPU/PCH ends, makes master signal flow direction correct, realizes remote to CPU/PCH progress Journey debug.
Level conversion circuit in described method inside logic circuit utilization according to circumstances controls BMC and CPU/PCH ends Master signal transmission direction, make master signal flow direction correct.
Level conversion circuit signal sent according to master control, control different from master control reception signal flow direction in described method BMC and the master signal transmission direction at CPU/PCH ends.
Include XDP connectors in described method on server master board, be connected with CPU/PCH ends, by logic circuit Gating switch circuit be also connected with BMC.
Gating switch circuit selects to visit CPU/PCH ends according to the master mode for carrying out debug in described method The link asked.
A kind of logic circuit, it is arranged between BMC the and CPU/PCH ends of server master board, BMC will by logic circuit Master signal is connected one to one with CPU/PCH ends, and BMC and the master at CPU/PCH ends are controlled by logic circuit further according to situation Signal transmission direction is controlled, makes master signal flow direction correct, realizes and long-range debug is carried out to CPU/PCH.
Described logic circuit includes level shifting circuit, according to circumstances controls BMC and the master signal at CPU/PCH ends to pass Defeated direction, make master signal flow direction correct.
Level shifting circuit signal sent according to master control, control different from master control reception signal flow direction in described logic circuit BMC processed and the master signal transmission direction at CPU/PCH ends.
Described logic circuit, when including XDP connectors on server master board, it is connected with CPU/PCH ends, then logic circuit Also include gating switch circuit, XDP connectors is also connected with BMC.
Gating switch circuit selects to enter CPU/PCH ends according to the master mode for carrying out debug in described logic circuit The link that row accesses.
The present invention has an advantageous effect in that compared with prior art:
The present invention provides a kind of method that long-range Debug is carried out using BMC, by increasing phase between mainboard BMC and CPU/PCH Master signal and CPU/PCH ends are connected one to one, passed through further according to situation by the logic answered, BMC by logic circuit Logic circuit controls BMC and the master signal transmission direction at CPU/PCH ends, makes master signal flow direction correct, realizes to CPU/PCH Carry out long-range debug;Server master board external connector interface quantity can be reduced, reduces design cost, while can be to CPU/PCH Remote analysis, reduce the dependence to special Debug instruments and improve Debug efficiency.
Brief description of the drawings
Fig. 1 in the prior art mainboard carry out debug block schematic illustration;
Mainboard carries out debug block schematic illustration in Fig. 2 present invention;
Mainboard carries out debug block schematic illustration in Fig. 3 present invention specific implementations.
Embodiment
The present invention provides a kind of method that long-range Debug is carried out using BMC, at BMC and the CPU/PCH end of server master board Between set up logic circuit, BMC is connected one to one master signal and CPU/PCH ends by logic circuit, further according to situation BMC and the master signal transmission direction at CPU/PCH ends are controlled by logic circuit, make master signal flow direction correct, realization pair CPU/PCH carries out long-range debug.
A kind of logic circuit is provided simultaneously, is arranged between BMC the and CPU/PCH ends of server master board, BMC is by patrolling Collect circuit master signal and CPU/PCH ends connect one to one, passing through logic circuit further according to situation controls BMC and CPU/ The master signal transmission direction at PCH ends, make master signal flow direction correct, realize and long-range debug is carried out to CPU/PCH.
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, to this hair Bright further description.
Using the inventive method, logic circuit is set up between BMC the and CPU/PCH ends of server master board, BMC is by patrolling Collect circuit master signal and CPU/PCH ends connect one to one, wherein BMC generally has TCK/TMS/TDI/TDO/TRST etc. main Signal is controlled, TCK/TDO/TRST/TMS signals are that master control sends signal, i.e. BMC is sent to CPU/PCH ends, and TDI receives for master control Signal, the flow direction of two kinds of signals is different,
BMC and the master signal at CPU/PCH ends is according to circumstances controlled to transmit by the level conversion circuit inside logic circuit again Direction, wherein BMC chip operating voltage are 3.3V, and CPU/PCH operating voltages are 1.05V, and both level mismatch, level conversion Circuit realizes the flow direction difference according to two kinds of master signals using voltage conversion chip, and adjustment master signal flows to correct;
MAC built in BMC combines with onboard PHY chip carries out remote management, realizes that BMC can be configured to using BMC is remotely accessed Master patterns, realize and long-range debug is carried out to CPU/PCH.
The above-mentioned output when it is implemented, the voltage conversion chip that level conversion circuit utilizes can be opened a way by drain electrode, Pull-up resistor can be added in the input/output terminal of voltage conversion chip, prevent that line level is abnormal, influence normal function.
And working as above-mentioned server master board includes XDP connectors, it is connected with CPU/PCH ends, can be by logic circuit Gating switch circuit is also connected with BMC, gating switch circuit include data strobe chip and its connection with door;
To avoid ITP instruments and BMC in XDP modes while being used as master control, while reduce the signal quality that signal wire diverging band comes Influence, increase gating switch circuit selects to visit CPU/PCH ends according to the master mode for carrying out debug in logic circuit The link asked:
When ITP instruments insert XDP interfaces, XDP signals in place can be set to 0 automatically, i.e. low level, with door after 0 electric potential signal is received, Logic low is exported to close the data transmission link between BMC and CPU/PCH, and data receiver link can not be handled, this When CPU/PCH is conducted interviews only XDP/ITP circuits;
And when XDP is not inserted into, then XDP signal acquiescences in place are set to 1, i.e. high level, are completely controlled by with the output state of door BMC Select pins, when this pin is arranged to 1, high level logic is exported with door, BMC circuits are opened, and BMC can be right CPU/PCH ends conduct interviews, and due to now not external ITP instruments of XDP, cabling is shorter, and influence caused by signal bifurcated can be neglected.
In above-mentioned specific implementation, BMC, logic circuit, XDPS and CPU/PCH ends are connected using jtag bus, and then Access CPU/PCH internal datas, register value, the highly dense connectors of 60 Pin that it can be standard that wherein XDP, which is, level conversion line Road can utilize the GTL2014 chips of NXP companies, and data strobe chip can use the SN74CBTLV3126DR of TI companies, and BMC can The AST2500 chips of ASPEED companies are selected, PHY chip can use the RTL8211FD, CPU/PCH Intel of Marvel companies Corresponding platform chip.

Claims (10)

  1. A kind of 1. method that long-range Debug is carried out using BMC, it is characterised in that BMC and the CPU/PCH end of server master board it Between set up logic circuit, master signal and CPU/PCH ends are connected one to one, led to further according to situation by BMC by logic circuit Logic circuit control BMC and the master signal transmission direction at CPU/PCH ends are crossed, makes master signal flow direction correct, realizes to CPU/ PCH carries out long-range debug.
  2. 2. according to the method for claim 1, it is characterised in that the level conversion circuit inside logic circuit utilization is according to feelings Condition controls BMC and the master signal transmission direction at CPU/PCH ends, makes master signal flow direction correct.
  3. 3. according to the method for claim 2, it is characterised in that level conversion circuit sends signal according to master control and connect with master control Number flow direction of collecting mail is different, control BMC and the master signal transmission direction at CPU/PCH ends.
  4. 4. according to the method described in claim 1-3, it is characterised in that include XDP connectors on server master board, with CPU/PCH End is connected, and is also connected with BMC by the gating switch circuit in logic circuit.
  5. 5. according to the method for claim 4, it is characterised in that gating switch circuit according to carry out debug master mode, Select the link to be conducted interviews to CPU/PCH ends.
  6. 6. a kind of logic circuit, it is characterised in that be arranged between BMC the and CPU/PCH ends of server master board, BMC is by patrolling Collect circuit master signal and CPU/PCH ends connect one to one, passing through logic circuit further according to situation controls BMC and CPU/ The master signal transmission direction at PCH ends, make master signal flow direction correct, realize and long-range debug is carried out to CPU/PCH.
  7. 7. logic circuit according to claim 6, it is characterised in that logic circuit includes level shifting circuit, according to circumstances BMC and the master signal transmission direction at CPU/PCH ends are controlled, makes master signal flow direction correct.
  8. 8. logic circuit according to claim 7, it is characterised in that the level shifting circuit sends signal according to master control It is different from master control reception signal flow direction, control BMC and the master signal transmission direction at CPU/PCH ends.
  9. 9. according to the logic circuit described in claim 6-8, it is characterised in that when including XDP connectors on server master board, with CPU/PCH ends are connected, then logic circuit also includes gating switch circuit, XDP connectors is also connected with BMC.
  10. 10. logic circuit according to claim 9, it is characterised in that gating switch circuit is according to the master control for carrying out debug Mode, select the link to be conducted interviews to CPU/PCH ends.
CN201710813190.2A 2017-09-11 2017-09-11 A kind of method that long-range Debug is carried out using BMC Pending CN107688540A (en)

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CN201710813190.2A CN107688540A (en) 2017-09-11 2017-09-11 A kind of method that long-range Debug is carried out using BMC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710813190.2A CN107688540A (en) 2017-09-11 2017-09-11 A kind of method that long-range Debug is carried out using BMC

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109101383A (en) * 2018-08-09 2018-12-28 郑州云海信息技术有限公司 A kind of test method and system of memory detection
CN109344031A (en) * 2018-09-25 2019-02-15 郑州云海信息技术有限公司 A kind of condition detection method of storage system, device, equipment and storage medium
CN114860636A (en) * 2022-05-31 2022-08-05 苏州浪潮智能科技有限公司 Server user interface panel, server, use method and workstation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102708034A (en) * 2012-05-14 2012-10-03 江苏中科梦兰电子科技有限公司 Computer remote and local monitoring system based on CPU (central processing unit) with serial port function
CN104579802A (en) * 2015-02-15 2015-04-29 浪潮电子信息产业股份有限公司 Method for fast fault restoration of multipath server
CN104850485A (en) * 2015-05-25 2015-08-19 深圳国鑫恒宇技术有限公司 BMC based method and system for remote diagnosis of server startup failure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102708034A (en) * 2012-05-14 2012-10-03 江苏中科梦兰电子科技有限公司 Computer remote and local monitoring system based on CPU (central processing unit) with serial port function
CN104579802A (en) * 2015-02-15 2015-04-29 浪潮电子信息产业股份有限公司 Method for fast fault restoration of multipath server
CN104850485A (en) * 2015-05-25 2015-08-19 深圳国鑫恒宇技术有限公司 BMC based method and system for remote diagnosis of server startup failure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109101383A (en) * 2018-08-09 2018-12-28 郑州云海信息技术有限公司 A kind of test method and system of memory detection
CN109344031A (en) * 2018-09-25 2019-02-15 郑州云海信息技术有限公司 A kind of condition detection method of storage system, device, equipment and storage medium
CN114860636A (en) * 2022-05-31 2022-08-05 苏州浪潮智能科技有限公司 Server user interface panel, server, use method and workstation
CN114860636B (en) * 2022-05-31 2023-07-18 苏州浪潮智能科技有限公司 Server user interface panel, server, using method and workstation

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Application publication date: 20180213

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