CN104579802A - Method for quickly recovering faults of multi-path server - Google Patents

Abstract

The present invention provides a method for fast fault recovery of multi-channel servers, and relates to multi-channel server architecture technology. The invention allows the DMI bus of the PCH to be connected to the main CPU and a slave CPU through a PCIE switch chip, and the switching of the switch chip is controlled by the PCH and the BMC. Common control; when the slave CPU fails, the system shields the slave CPU; when the master CPU fails, the BIOS or BMC automatically switches the DMI bus to the slave CPU, and shields the failed master CPU, so that the system can quickly recover from the fault Central recovery, that is, the fault shielding of any CPU in the server is realized. Reduce the downtime of server failure recovery, and minimize the loss caused by system downtime due to CPU failure.

Description

A Fast Fault Recovery Method for Multi-way Servers

technical field

The invention relates to a multi-path server architecture technology, in particular to a method for fast failure recovery of a multi-way server.

Background technique

In a common multi-channel server architecture, the DMI bus of the south bridge chip (PCH) is connected to the main CPU, as shown in Figure 1. When the system is turned on, PCH obtains system setting information, device drivers, and self-inspection programs from the BIOS, and completes the self-inspection of all CPUs and memory through the DMI bus with the main CPU. After the self-test is completed, the BIOS will start to guide the operating system and complete the boot. In this server structure design, the system can shield the faulty slave CPU, but if the master CPU fails, the DMI bus between the PCH and the PCH cannot work, the BIOS program cannot be loaded, the system cannot shield the master CPU, and must be replaced manually The failure recovery is completed by the main CPU, which increases the downtime of the server, which is very unfavorable for the server of the key application.

Contents of the invention

In order to solve this problem, the present invention proposes a new fast fault recovery method for multi-path servers.

Technical scheme of the present invention is:

The DMI bus of the PCH is connected to the master CPU and a slave CPU through a PCIE switch chip, and the switching of the switch chip is jointly controlled by the PCH and the management controller (BMC). Since the DMI bus uses the PCIE protocol, the use of a PCIE switch chip can ensure the signal integrity of the DMI bus. Under this design, when the slave CPU fails, the system can shield the slave CPU; when the master CPU fails, the BIOS or BMC will automatically switch the DMI bus to the slave CPU and shield the failed master CPU, making The system can quickly recover from faults, which means that any CPU fault shielding in the server is realized, which greatly reduces the downtime of the server during fault recovery, and minimizes the losses caused by system downtime caused by CPU faults. Using PCH and BMC dual-control switch mode can ensure that the switch chip can switch stably and quickly when the main CPU fails.

The control signal of the switch chip is jointly controlled by the GPIO port of the PCH and the BMC, and the DMI bus of the PCH is selected to be connected to the master CPU or the slave CPU through the control signal.

The Switch chip selects the DMI bus of the main CPU by default, and the control signal is high level. In the default state, both the GPIO port of the PCH and the BMC release the control over the control signal; when the main CPU fails when the system is running, the BMC will detect When the failure of the main CPU is detected, the control signal is automatically pulled down, and the system is restarted once, and the DMI bus switching is completed after the restart.

When the main CPU fails during the system power-on self-check, the BIOS will automatically respond according to the self-check code of the CPU, control the GPIO port of the PCH to pull down the control signal of the switch chip, switch to the slave CPU and perform a hot restart to re-check the self-check, complete DMI bus switching.

This design method makes when the main CPU fails, the BIOS or BMC will automatically switch the DMI bus to the slave CPU, and shield the failed main CPU, so that the system can quickly recover from the failure and greatly reduce the recovery time of the server. Downtime minimizes losses caused by system downtime due to CPU failure.

Description of drawings

Fig. 1 is a schematic diagram of a connection structure in the prior art.

Fig. 2 is a schematic diagram of the connection structure of the present invention.

Detailed ways

The content of the present invention is described in more detail below:

as shown in picture 2,

1. The invention consists of main CPU, slave CPU, switch chip, PCH and BMC;

2. Both the DMI bus of the master CPU and the slave CPU are connected to the switch chip, and the other end of the chip is connected to the PCH of the system. The control signal of the switch chip is jointly controlled by the GPIO port of the PCH and the BMC, and the DMI of the PCH is selected through the control signal. The bus is connected to the master CPU or the slave CPU;

3. The Switch chip selects the DMI bus of the main CPU by default (the control signal is high level). In the default state, both the GPIO port of the PCH and the BMC release the control over the control signal. When the main CPU fails when the system OS is running, the BMC will detect the failure of the main CPU, and automatically pull down the control signal, and perform a system restart, and complete the DMI bus switching after restarting;

4. When the main CPU fails during the system power-on self-test, the BIOS will automatically respond according to the self-test code of the CPU, control the GPIO port of the PCH to pull down the control signal of the switch chip, switch to the slave CPU and perform a hot restart to re-self-test , to complete the switching of the DMI bus.

Claims (4)

1. a method for multipath server fast failure recovery, is characterized in that,

The DMI bus of PCH is connected from CPU with one with host CPU by a PCIE switch chip, and the switching of switch chip is by PCH and BMC co-controlling; When breaking down from CPU, system should shield from CPU; When host CPU breaks down, BIOS or BMC automatically by DMI bus switch to from CPU, and mask the host CPU of fault, system can be recovered fast from fault, namely achieve the fault masking of any one CPU in server.

2. method according to claim 1, is characterized in that, the control signal of switch chip, by the GPIO port of PCH and BMC co-controlling, selects the DMI bus of PCH to be connected to host CPU by control signal or from CPU.

3. method according to claim 2, is characterized in that, Switch chip acquiescence selects the DMI bus of host CPU, and control signal is high level, and under default conditions, the GPIO port of PCH and BMC all discharge the control to this control signal; After when system cloud gray model, host CPU breaks down, BMC can detect the fault of host CPU, and automatically control signal is dragged down, and carries out primary system and restart, and completes the switching of DMI bus after restarting.

4. method according to claim 3, it is characterized in that, when when system boot self-inspection, host CPU breaks down, BIOS can respond according to the self-inspection code of CPU automatically, the GPIO port of control PCH drags down the control signal of switch chip, be switched to from CPU and carry out hot restart self-inspection again, completing the switching of DMI bus.