CN211375588U

CN211375588U - Multi-debugging interface switching circuit

Info

Publication number: CN211375588U
Application number: CN202020445736.0U
Authority: CN
Inventors: 何蒙
Original assignee: Beijing Runke General Technology Co Ltd
Current assignee: Beijing Runke General Technology Co Ltd
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2020-08-28
Anticipated expiration: 2030-03-31

Abstract

The utility model discloses a many debugging interfaces switching circuit, include: net gape, PHY chip, ZYNQ chip, at least one FPGA drive circuit and at least one SOC drive circuit, FPGA drive circuit includes: contact pin and FPGA chip on first driver, the JTAG board, SOC drive circuit includes: the second driver, the pin on the serial port board, the transceiver and the SOC chip. When the board card is preliminarily debugged, the FPGA chip and the SOC chip are debugged by directly using the contact pins on the JTAG board and the contact pins on the serial port board on the board card, and after the board card is installed on the board card shell to be made into the whole equipment, because the programmable logic of the ZYNQ chip can simulate debugging signals, the FPGA chip and the SOC chip can be debugged through the network interface. Therefore, under the multi-FPGA chip and multi-SOC chip system, extra connectors and cables are not needed, and the design of the appearance structure of the equipment and the cost control are facilitated.

Description

Multi-debugging interface switching circuit

Technical Field

The utility model relates to a debugging interface technical field, more specifically the theory relates to a many debugging interfaces switch circuit.

Background

With the increase of the complexity of an electronic system, more and more devices such as a Central Processing Unit (CPU), a Field Programmable Gate Array (FPGA), a Digital Signal Processing (DSP), and the like are integrated by a single board card, and more debugging interfaces, such as an RS232 interface, an RS422 interface, a Joint Test Action Group (JTAG) interface, and the like, used for monitoring the working state of the device or debugging the device on the board card are also included.

In the board debugging stage, an on-board pin provided on the board is generally connected with a debugging interface for debugging, or a connector or a cable is used to lead out each debugging interface for debugging.

However, the on-board pins provided on the board card can only be used when the board card is preliminarily debugged, and cannot be used when the board card is installed on a housing or is in a working environment such as a chassis. The manner of leading out each debug interface by using a connector or a cable is mainly suitable for the case of few debug interfaces, and the number of debug interfaces is correspondingly increased under multiple soc (system on Chip technology) chips and multiple FPGA (field programmable Gate Array) systems, so that the number of connectors or cables used when the debug interfaces are led out is increased, which is not favorable for the appearance structure design and cost control of the device.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model discloses a many debugging interfaces switch circuit to the realization only needs an existing external communication interface when complete machine equipment debugs, also is the net gape, can accomplish the debugging to FPGA chip and SOC chip, and need not draw forth each debugging interface specially, thereby under many FPGA chips and many SOC chip systems, need not additionally to increase connector and cable, thereby does benefit to the exterior structure design and the cost control of equipment.

A multi-debug interface switching circuit, comprising: the system comprises a network port, a port physical layer (PHY) chip, a ZYNQ chip 13, at least one Field Programmable Gate Array (FPGA) driving circuit and at least one SOC driving circuit;

the network port is used for connecting with a PC;

the ZYNQ chip is connected with the internet access through the PHY chip and is provided with programmable logic capable of simulating debugging signals;

the FPGA drive circuit comprises: the device comprises a first driver, a contact pin on a JTAG board and an FPGA chip, wherein the first driver is respectively connected with the contact pin on the JTAG board and the FPGA chip, an enabling end of the first driver is connected with the ZYNQ chip, and meanwhile, a common end of the first driver and the FPGA chip is connected with the ZYNQ chip;

the SOC drive circuit includes: contact pin, transceiver and SOC chip on second driver, the serial port board, the second driver respectively with the transceiver with the SOC chip is connected, the transceiver with contact pin connection on the serial port board, the enable end of second driver with ZYNQ chip connects, simultaneously, the second driver with the common port of SOC chip with ZYNQ chip connects.

Optionally, the ZYNQ chip has a processing subsystem PS terminal and a programmable logic PL terminal, the PS terminal is connected to the network port through the PHY chip, and the PL terminal is connected to the enable terminal of the first driver, the common terminal of the first driver and the FPGA chip, the enable terminal of the second driver, and the common terminal of the second driver and the SOC chip, respectively.

Optionally, the common terminal of the first driver and the FPGA chip includes: the test device comprises a test clock port, a test data input port, a test data output port and a test mode selection port.

Optionally, the pins on the serial port plate include: RS232 on-board pins and RS422 on-board pins.

Optionally, the transceiver includes: RS232 transceiver and RS422 transceiver.

According to the above technical scheme, the utility model discloses a many debugging interfaces switching circuit, include: net gape, PHY chip, ZYNQ chip, at least one FPGA drive circuit and at least one SOC drive circuit, FPGA drive circuit includes: contact pin and FPGA chip on first driver, the JTAG board, SOC drive circuit includes: the second driver, contact pin on the string oral plate, transceiver and SOC chip, when the integrated circuit board is tentatively debugged, first driver and second driver switch on, the debugging to FPGA chip and SOC chip is accomplished to contact pin on the JTAG on the direct use integrated circuit board this moment board and the last contact pin of string oral plate, after the integrated circuit board shell is made to the integrated circuit board installation, first driver and second driver are closed, because the programmable logic that ZYNQ chip has can simulate the debugging signal, consequently FPGA chip and SOC chip accessible net gape are debugged. The utility model discloses when complete machine equipment debugs, only need an existing external communication interface, also be the net gape, can accomplish the debugging to FPGA chip and SOC chip, and need not draw forth each debugging interface specially to under many FPGA chips and many SOC chip systems, need not additionally to increase connector and cable, thereby do benefit to the exterior structure design and the cost control of equipment.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the disclosed drawings without creative efforts.

Fig. 1 is a circuit block diagram of a multi-debug interface switching circuit disclosed in an embodiment of the present invention;

fig. 2 is a JTAG driving circuit diagram disclosed in an embodiment of the present invention;

fig. 3 is a circuit block diagram of another multi-debug interface switching circuit disclosed in the embodiment of the present invention;

fig. 4 is a circuit diagram of an RS232 external line disclosed in the embodiment of the present invention;

fig. 5 is a circuit diagram of an RS422 external line according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The embodiment of the utility model discloses many debugging interfaces switching circuit, include: net gape, PHY chip, ZYNQ chip, at least one FPGA drive circuit and at least one SOC drive circuit, FPGA drive circuit includes: contact pin and FPGA chip on first driver, the JTAG board, SOC drive circuit includes: the second driver, contact pin on the string oral plate, transceiver and SOC chip, when the integrated circuit board is tentatively debugged, first driver and second driver switch on, the debugging to FPGA chip and SOC chip is accomplished to contact pin on the JTAG on the direct use integrated circuit board this moment board and the last contact pin of string oral plate, after the integrated circuit board shell is made to the integrated circuit board installation, first driver and second driver are closed, because the programmable logic that ZYNQ chip has can simulate the debugging signal, consequently FPGA chip and SOC chip accessible net gape are debugged. The utility model discloses when complete machine equipment debugs, only need an existing external communication interface, also be the net gape, can accomplish the debugging to FPGA chip and SOC chip, and need not draw forth each debugging interface specially to under many FPGA chips and many SOC chip systems, need not additionally to increase connector and cable, thereby do benefit to the exterior structure design and the cost control of equipment.

Referring to fig. 1, an embodiment of the present invention discloses a circuit block diagram of a multi-debug interface switching circuit, where the circuit includes: a network port 11, a PHY (Physical layer) Chip 12, a ZYNQ Chip 13, at least one FPGA (field programmable Gate Array) drive circuit 14, and at least one SOC (System-on-a-Chip) drive circuit 15.

Wherein:

the network port 11 is used for connecting with a PC, and in practical applications, the network port 11 can be led out through the RJ45 interface, so that the network port 11 can be connected with the PC through the RJ45 interface and the PHY chip 12 in sequence.

The ZYNQ chip 13 is connected to the network port 11 via the PHY chip 12.

Specifically, the ZYNQ chip 13 has a PS (Processing System) terminal and a PL (Programmable Logic) terminal, and the PS terminal of the ZYNQ chip 13 is connected to the network port 11 through the PHY chip 12, where the Programmable Logic in the ZYNQ chip 13 can simulate a debug signal.

The FPGA driving circuit 14 includes: the first driver 141, the JTAG board upper pin 142 and the FPGA chip 143, the first driver 141 is connected to the JTAG board upper pin 142 and the FPGA chip 143, the enable terminal of the first driver 141 is connected to the ZYNQ chip 13, specifically to the PL terminal of the ZYNQ chip 13, and meanwhile, the common terminal of the first driver 141 and the FPGA chip 143 is connected to the ZYNQ chip 13, specifically to the PL terminal of the ZYNQ chip 13.

Specifically, referring to fig. 1, the enable terminal FPGA _ EN of the first driver 141 is connected to the PL terminal of the ZYNQ chip 13, and meanwhile, the common terminal of the first driver 141 and the FPGA chip 143 includes: a TCK (test clock) port, a TDI (test data input) port, a TDO (test data output) port, and a TMS (test mode select) port are connected to the PL terminal of the ZYNQ chip 13.

Referring to the JTAG driving circuit diagram shown in fig. 2, patch pin signals FPGA _ TCK, FPGA _ TDO, FPGA _ TDI, and FPGA _ TMS are transmitted between the first driver 141 and the pin 142 on the JTAG board.

The SOC drive circuit 15 includes: second driver 151, string port board goes up contact pin 152, transceiver 153 and SOC chip 154, second driver 151 is connected with transceiver 153 and SOC chip 154 respectively, transceiver 153 is connected with string port board goes up contact pin 152, and the enable end of second driver 151 is connected with ZYNQ chip 13, specifically is connected with the PL end of ZYNQ chip 13, and simultaneously, the common port of second driver 151 and SOC chip 154 is connected with ZYNQ chip 13, specifically is connected with the PL end of ZYNQ chip 13.

Specifically, referring to fig. 1, the enable terminal SOC _ EN of the second driver 151 is connected to the PL terminal of the ZYNQ chip 13, and meanwhile, the common terminal of the second driver 151 and the SOC chip 154 includes: the test input port and the test output port are connected to the PL terminal of the ZYNQ chip 13.

In this embodiment, the ZYNQ chip 13 is configured to output a conduction electrical signal when the board card uses the pin on the board to perform the preliminary debugging, where the conduction electrical signal is used to conduct the first driver 141 and the second driver 151; the ZYNQ chip 13 is also configured to output a shutdown electrical signal after the board card is made into the whole device, and can simulate a debugging signal, where the shutdown electrical signal output by the PC is transmitted to the ZYNQ chip 13 through the PHY chip 12 by the gateway 11.

For ease of understanding, the following description of the operating principle of the multi-debug interface switching circuit is as follows:

when the board card is debugged preliminarily, the pin on the board is used for debugging, and the pin on the board comprises: the pin 142 on the JTAG board and the pin 152 on the serial port board make the enable terminal FPGA _ EN of the first driver 141 and the enable terminal SOC _ EN of the second driver 151 low level through the PL terminal of the ZYNQ chip 13, and set the ports of the PL terminal connected to the FPGA chip 143 and the SOC chip 154 to high impedance state, at this time, the first driver 141 and the second driver 151 are simultaneously turned on, and the JTAG signal of the pin 142 on the JTAG board is output to the FPGA chip 143 through the first driver 141, so that the pin 142 on the JTAG board can be directly used to complete debugging of the FPGA chip 143; serial signals of the serial port board upper contact 152 sequentially pass through the second driver 151 and the transceiver 153 and then are output to the SOC chip 154, so that the serial port board upper contact 152 can be directly used to complete debugging of the SOC chip 154.

When the board card is initially debugged and is made into a complete machine device, for example, after the board card is mounted on a chassis or an integrated chassis, the network port 11 transmits a shutdown electrical signal output by the PC to the ZYNQ chip 13 through the PHY chip 12, and controls the enable terminal FPGA _ EN of the first driver 141 and the enable terminal SOC _ EN of the second driver 151 to be at a high level through the PL terminal of the ZYNQ chip 13, at this time, the first driver 141 and the second driver 151 are both shut down, and programmable logic analog debugging signals of the PL terminal of the ZYNQ chip 13, such as JTAG (Universal Asynchronous Receiver Transmitter/Transmitter) signals, for example, the FPGA chip 143 and the SOC chip 154 can be debugged through the network port 11.

To sum up, the utility model discloses a many debugging interfaces switching circuit includes: net gape 11, PHY chip 12, ZYNQ chip 13, at least one FPGA drive circuit 14 and at least one SOC drive circuit 15, FPGA drive circuit 14 includes: a first driver 141, a JTAG board upper pin 142, and an FPGA chip 143, and the SOC driving circuit 15 includes: second driver 151, string port board goes up contact pin 152, transceiver 153 and SOC chip 154, when the integrated circuit board is debugged preliminarily, first driver 141 and second driver 151 switch on, this moment direct use on the JTAG board on the integrated circuit board contact pin 142 and the string port board on contact pin 152 accomplish the debugging to FPGA chip 143 and SOC chip 154, after the integrated circuit board is installed to the integrated circuit board shell and is made complete quick-witted equipment, first driver 141 and second driver 151 close, because the programmable logic that ZYNQ chip 13 has can simulate the debugging signal, consequently FPGA chip 143 and SOC chip 154 accessible internet access 11 are debugged. The utility model discloses when complete machine equipment debugs, only need an existing external communication interface, also be net gape 11, can accomplish the debugging to FPGA chip 143 and SOC chip 154, and need not draw forth each debugging interface specially to under many FPGA chip 143 and many SOC chip 154 systems, need not additionally to increase connector and cable, thereby do benefit to the exterior structure design and the cost control of equipment.

It should be noted that, in different SOC driving circuits 15, different transceivers 153 correspond to different pins 152 on the serial port board.

For example, referring to a circuit block diagram of a multi-debug interface switching circuit shown in fig. 3, the switching circuit includes two SOC driving circuits, where the first SOC driving circuit includes: driver A, RS232 transceiver, SOC1 chip, and pins on RS232 board. The enable terminal SOC1_ EN of driver A is connected to the PL terminal of ZYNQ chip 13, and the common terminal of driver A and SOC1 chips includes: UART _ T (serial transmitter) and UART _ R (serial receiver) connected to the PL terminal of the ZYNQ chip 13. Referring to the RS232 outside line circuit diagram shown in fig. 4, the signals SOC1_ UART _ T and SOC1_ UART _ R of the driver a are connected to the RS232 transceiver, and the on-board pin signals 232_ T and 232_ R passing through the RS232 transceiver are connected to the on-board pin of the RS 232.

The second SOC driving circuit includes: driver B, RS422 transceiver, SOC2 chip and RS422 on-board pins, driver B enable SOC2_ EN connected to ZYNQ chip 13 PL, driver B and SOC2 chip common, including: RO (receive output) and DI (data input) are connected to the PL terminal of the ZYNQ chip 13. In conjunction with the RS422 outside line circuit diagram shown in fig. 5, the signals SOC2_ RO and SOC2_ DI of the driver B are connected to the RS422 transceiver, and the on-board pin signals RS422_ A, RS422_ B, RS422_ Y, RS422_ Z after passing through the RS422 transceiver are connected to the on-board pins of the on-board RS 422.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-debug interface switching circuit, comprising: the system comprises a network port, a port physical layer (PHY) chip, a ZYNQ chip, at least one Field Programmable Gate Array (FPGA) driving circuit and at least one SOC driving circuit;

the network port is used for connecting with a PC;

2. The multi-debug interface switching circuit according to claim 1, wherein said ZYNQ chip has a processing subsystem PS terminal and a programmable logic PL terminal, said PS terminal is connected to said network port through said PHY chip, and said PL terminals are respectively connected to an enable terminal of said first driver, a common terminal of said first driver and said FPGA chip, an enable terminal of said second driver, and a common terminal of said second driver and said SOC chip.

3. The multi-debug interface switching circuitry of claim 1, wherein the common terminal of said first driver and said FPGA chip comprises: the test device comprises a test clock port, a test data input port, a test data output port and a test mode selection port.

4. The multi-debug interface switching circuitry of claim 1, wherein said on-board pins of said serial port comprise: RS232 on-board pins and RS422 on-board pins.

5. The multi-debug interface switching circuitry of claim 1, wherein said transceiver comprises: RS232 transceiver and RS422 transceiver.