CN112306773A - Fault detection platform of FC node machine with standard serial host interface - Google Patents
Fault detection platform of FC node machine with standard serial host interface Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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Abstract
The invention discloses a fault detection platform of an FC node machine with a standard serial host interface, which comprises a detection platform motherboard and a detection platform structural member, wherein the detection platform motherboard is arranged above the detection platform structural member, and the detection platform motherboard is fixed by the detection platform structural member and dissipates heat to the detection platform motherboard; the test platform motherboard includes: the system comprises an external interface unit, a standard host interface unit, an FC interface unit, an FPGA with a built-in processor and a processor circuit; the fault detection platform is used for testing FC electrical interface node machines and optical interface node machines supporting various types with PCIe host interfaces or SRIO host interfaces in two test modes, wherein the two test modes comprise: the FC node machine pair test mode and the FC node machine surrounding test mode. The problems that the fault detection environment of the FC node machine of the existing standard serial host interface is complex to build, and the expandability and the universality are not high are solved.
Description
The technical field is as follows:
the present invention relates to, but not limited to, computer hardware technologies, and in particular, to a fault detection platform for an FC node machine having a standard serial host interface.
Background art:
with the rapid development of an onboard FC network, FC node devices with standard serial host interfaces are developed and used in large quantities, and the host interfaces adopt standard PCIe or SRIO interfaces to provide an FC optical interface or an FC electrical interface to the outside. The host machine realizes the functions of communication management, equipment management, time management, network management and the like of the FC node machine through a standard serial interface. With the increasing delivery and use quantity of FC node machines, the quantity of fault parts in the production debugging process and the parts return to the factory is increased. In the troubleshooting process, relevant test environments need to be built according to different fault phenomena to carry out targeted troubleshooting on the host interface function, the FC interface function, the communication function, the signal characteristic and the like of the FC node machine product.
The traditional troubleshooting environment is built, a special debugging tool needs to be designed for different electric interface FC node machine products and optical interface FC node machine products, functions such as power supply, PCIe/SRIO host interface leading-out, FC interface electric/optical signal leading-out and the like are provided for the products, a special CPU embedded host environment and related tools need to be designed, and a PCIe/SRIO host interface and an embedded debugging environment of a CPU are provided. The CPU tool and the FC node machine debugging and testing tool are interconnected and communicated through PCIe/SRIO high-speed cables, and the two sets of tools are low in maintenance and use convenience, expansibility and universality. In addition, in order to construct an FC simulation node machine environment to test an FC node machine, an FC simulation card or an FC node machine matched with an external embedded CPU environment needs to be additionally configured and a special driver and a test program are developed, so that the environment construction is complex.
The invention content is as follows:
the purpose of the invention is:
the embodiment of the invention provides a fault detection platform of an FC node machine with a standard serial host interface, which aims to solve the problems of complex construction of a fault detection environment, low expandability, low universality and the like of the FC node machine with the existing standard serial host interface.
The technical solution of the invention is as follows:
the embodiment of the invention provides a fault detection platform of an FC node machine with a standard serial host interface, which is characterized by comprising the following steps: detecting a platform mother board and detecting a platform structural member;
the detection platform motherboard is arranged above the detection platform structural member, and is fixed through the detection platform structural member and dissipates heat to the detection platform motherboard;
the test platform motherboard includes: the system comprises an external interface unit, a standard host interface unit, an FC interface unit, an FPGA with a built-in processor and a processor circuit;
the fault detection platform is used for testing FC electrical interface node machines and optical interface node machines supporting various types with PCIe host interfaces or SRIO host interfaces in two test modes, wherein the two test modes comprise: the FC node machine pair test mode and the FC node machine surrounding test mode.
Alternatively, in a fault detection platform for FC node machines with standard serial host interfaces as described above,
the standard host interface unit of the detection platform motherboard comprises: the system comprises a standard host interface, a host interface exchange chip, an electrical interface FC node machine connector and an optical interface FC node machine which are positioned on an FPGA;
the standard host interface unit is used for connecting a standard PCIe or SRIO host interface in the detection platform motherboard with the electric interface FC node machine and the optical interface FC node machine so as to realize adaptation with the FC node machine; the host interface switching core comprises an SRIO switching chip PCIe or an SRIO switching chip;
the host interface comprises a standard PCIe host interface and an SRIO host interface which are based on FPGA and obtained through IP core instantiation, and the external 2-path host interface is realized through a PCIe exchange chip or an SRIO exchange chip and is used for interconnecting PCIe interface signals or SRIO interface signals on 2 FC node machine connectors.
Alternatively, in a fault detection platform for FC node machines with standard serial host interfaces as described above,
the external interface unit of the detection platform motherboard comprises: the system comprises an external serial port, a JTAG interface, an FC optical interface and a power interface;
the serial port is connected with the computer and used for displaying the test program and the test result running on the processor in real time through the computer;
the JTAG interface is respectively connected with 2 FC node machine connectors, and JTAG signals on the FC node machines are led out to the JTAG interface through the JTAG signal interconnection of the FC node machine connectors and the FC node machines;
the FC optical interface is an external optical communication interface of an FC interface unit configured on the detection platform, and is connected to the optical interface FC node machine and used for realizing interconnection with the optical communication interface of the optical interface FC node machine;
and the power interface is used for converting an external 220V power supply into a power supply of the platform, monitoring the working current of the platform in real time and supplying power for the test platform motherboard and the FC node machine.
Alternatively, in a fault detection platform for FC node machines with standard serial host interfaces as described above,
the FC interface unit of the detection platform motherboard comprises: the system comprises 2 paths of FC interfaces and a photoelectric transceiver which are arranged in an FPGA and are used for providing 2 paths of FC electric signals to the outside, wherein 1 path of FC interfaces is connected with an FC node machine connector of an electric interface to realize the interconnection of the FC interface electric signals and the FC electric signals on the FC node machine connector of the electric interface; the other 1 channel of FC interface is connected with a photoelectric transceiver, the photoelectric transceiver is connected to an optical port on the optical interface FC node mechanical connector through an FC optical interface and is used for converting the channel of FC interface electrical signal into an FC interface optical signal through the photoelectric transceiver, and the FC interface optical signal is transmitted to the FC node machine through the FC optical interface and the optical port on the optical interface FC node mechanical connector;
the 2 FC interfaces on the FPGA are obtained through FC-IP core instantiation, and the standard FC node machine is simulated functionally, so that point-to-point interconnection test of the FC interfaces and the FC node machine to be tested is realized.
Alternatively, in a fault detection platform for FC node machines with standard serial host interfaces as described above,
the processor and the processor circuit for detecting the platform motherboard comprise: the processor is arranged in the FPGA, and the storage circuit, the clock circuit, the reset circuit and the power circuit are arranged in the FPGA;
in the fault detection platform, the functions realized by the processor and the processor circuit comprise:
1) selecting a test mode and an FC interface channel and printing a test result;
2) initializing a PCIe or SRIO standard host interface;
3) performing BIT test on resources on a tested FC node board;
4) performing equipment management and communication management on the FC node machine to be tested;
5) and carrying out communication management on the FC interface in the node machine pair test mode to realize point-to-point communication test with the FC node machine to be tested.
Alternatively, in a fault detection platform for FC node machines with standard serial host interfaces as described above,
the fault detection platform is further used for selecting a test mode through serial port input and selecting which FC interface is adopted for testing through the serial port input before executing the test, and enabling the electric interface FC node machine to be tested or the optical interface FC node machine to be tested.
Alternatively, in a fault detection platform for FC node machines with standard serial host interfaces as described above,
under the opposite-node machine testing mode, the FC interface is used for simulating the function of the FC node machine, and a processor built in the FPGA is used for carrying out communication management on the FC interface so as to realize the point-to-point FC transmission testing function of the FC interface and the FC node machine to be tested.
Alternatively, in a fault detection platform for FC node machines with standard serial host interfaces as described above,
in the surrounding test mode, the FC interface is set to be in an external self-surrounding mode and is used for sending FC messages received from the FC interface to an opposite-end FC node machine to be tested after the FC messages are automatically surrounded through the outside, in the surrounding test mode, the FPGA of the FC node machine to be tested is connected through the JTAG interface and the standard host interface, and the test data flow realizes external surrounding through the FC interface of the FPGA on the fault detection platform so as to test indexes such as stability and error rate of a communication link.
The invention has the advantages that:
1) the operation is convenient: the debugging mode of the product debugging tool and the CPU embedded host environment is separated, and the detection of the FC node machine can be realized by a single fault detection platform;
2) FC analog node: aiming at the point-to-point test of an FC port of an FC node machine, an FC simulation card or an FC node machine environment matched with an external embedded CPU environment does not need to be additionally constructed, and an FC interface is designed through FPGA logic to simulate an FC external node;
3) two test modes are provided: providing two test modes of a node machine pairing test and a surrounding test, and realizing point-to-point communication test with the FC node machine to be tested and providing an external surrounding test for the FC node machine to be tested;
4) the architecture is simplified: the SOPC framework based on the FPGA is designed, and a CPU module is not required to be provided independently for detection;
5) the universality is good: the detection platform is designed to provide an electrical interface FC node machine connector and an optical interface FC node machine connector, so that different types of FC node machines can be tested;
6) the expansibility is good: adaptation to FC node machines of different host interfaces such as PCIe/SRIO can be realized by filling different FPGA logics, and related test functions can be improved and perfected by upgrading the logics;
7) automated testing: the automatic test can be realized, and the test result can be displayed in real time through the serial port.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic structural diagram of a fault detection platform of an FC node machine having a standard serial host interface according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a fault detection platform of an FC node machine with a standard serial host interface according to an embodiment of the present invention.
The specific implementation mode is as follows:
in order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The embodiment of the invention provides a miniaturized fault detection platform of an FC node machine with a standard serial host interface aiming at the problems of complex construction, low expandability and low universality of a fault detection environment of the FC node machine with the standard serial host interface, and particularly relates to a fault detection platform aiming at a FC node machine with a standard PCIe/SRIO host interface in a test system and a design method. The miniaturized fault detection platform supports various FC electrical interface node machines and FC optical interface node machine products with PCIe/SRIO standard serial host interfaces, and can conveniently complete module detection and fault positioning work based on the fault detection platform.
The following specific embodiments of the present invention may be combined, and the same or similar concepts or processes may not be described in detail in some embodiments.
Fig. 1 is a schematic structural diagram of a use of a fault detection platform of an FC node machine having a standard serial host interface according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a principle of a fault detection platform of an FC node machine having a standard serial host interface according to an embodiment of the present invention.
Referring to fig. 1 and fig. 2, a fault detection platform of an FC node machine with a standard serial host interface according to an embodiment of the present invention may include: the detection platform comprises a detection platform mother board and a detection platform structural member.
The detection platform motherboard in the embodiment of the invention is arranged above the detection platform structural member, and the detection platform motherboard is fixed through the detection platform structural member and is radiated.
The detection platform motherboard in the embodiment of the invention comprises: the system comprises an external interface unit, a standard host interface unit, an FC interface unit, an FPGA with a built-in processor and a processor circuit.
The fault detection platform in the embodiment of the invention can test the FC electrical interface node machine and the optical interface node machine supporting various types of PCIe host interfaces or SRIO host interfaces in two test modes based on the hardware structure, wherein the two test modes comprise: the FC node machine pair test mode and the FC node machine surrounding test mode.
The embodiment of the invention provides a fault detection platform, which consists of a detection platform motherboard and a detection platform structural member; the detection platform motherboard is designed based on an SOPC framework by adopting an FPGA with an embedded processor core, and is provided with a related power supply circuit, a clock circuit, a reset circuit and a storage circuit, and a serial port, a JTAG interface, an optical interface and a power supply interface. The electric interface connector and the photoelectric mixed connector are designed aiming at various FC electric interface node machines and optical interface node machine products with PCIe/SRIO standard host interfaces, and the coupling with various FC node machines is realized. The FPGA design provides PCIe/SRIO standard interface signals, and the interconnection with corresponding PCIe/SRIO standard host interface signals on the connector is realized through PCIe/SRIO switch; the FPGA design provides 2 paths of FC electrical interface signals, 1 path is interconnected with an electrical interface FC node machine connector, and 1 path is provided with an optical interface through a photoelectric transceiver and can be interconnected with the optical interface FC node machine connector through optical fibers; the FPGA embedded processor runs the test case, and is designed to provide a serial port, so that the real-time display of the test result is realized. The detection platform motherboard provides a JTAG interface, and is interconnected with the electrical interface FC node machine connector and the optical interface FC node machine connector to realize the leading-out of the JTAG interface of the FC node machine. The detection platform motherboard provides a power interface to supply power to the motherboard and the FC node machine to be tested. The detection platform structural member realizes the fixation and heat dissipation of the motherboard.
The following describes in detail the specific structure and implementation function of the motherboard of the inspection platform in the embodiment of the present invention.
(1) External interface unit
The test platform motherboard of the fault detection platform provides a serial port, a JTAG interface, an FC optical interface and a power interface to the outside, namely the external interface unit comprises: the device comprises an external serial port, a JTAG interface, an FC optical interface and a power interface.
The serial port is connected with the computer, and the computer is used for displaying the test program and the test result which run on the processor in real time; the JTAG interface is respectively connected with 2 FC node machine connectors, and JTAG signals on the FC node machine are led out to the JTAG interface through the JTAG signal interconnection of the FC node machine connectors and the FC node machine; the FC optical interface is an external optical communication interface of an FC interface unit configured on the fault detection platform, is connected to the optical interface FC node machine, and can realize interconnection with the optical communication interface of the optical interface FC node machine; the power supply interface realizes the functions of external 220V mains supply power supply, power supply conversion and current monitoring, specifically converts an external 220V power supply into a power supply of the platform, monitors the working current of the platform in real time, and supplies power for a test platform motherboard and an FC node machine.
(2) Standard host interface design
The detection platform motherboard of fault detection platform still provides electrical interface FC node machine connector and optical interface FC node machine and links the machine, and this standard host computer interface unit includes: the system comprises a standard host interface positioned on the FPGA, a host interface exchange chip, an electrical interface FC node machine connector and an optical interface FC node machine connecting machine.
Wherein, standard host interface unit can link to each other standard PCIe or SRIO host interface in the test platform motherboard with electric interface FC node machine and optical interface FC node machine to realize the adaptation with FC node machine, and host interface switching core includes SRIO switching chip PCIe or SRIO switching chip.
The host interface is designed and realized based on standard PCIe or RapidIO IP core of FPGA, and realizes external PCIe or SRIO interface by different test logics filled in FPGA, namely the host interface comprises standard PCIe host interface and SRIO host interface which are based on FPGA and obtained by IP core instantiation, and realizes external 2-path host interface by PCIe exchange chip or SRIO exchange chip, so as to be convenient for interconnection with related PCIe interface signal or SRIO interface signal on 2 FC node machine connectors.
(3) FC interface unit
FC interface unit of the test platform motherboard, including: 2 paths of FC interfaces and photoelectric transceivers are realized based on FPGA design, and 2 paths of FC electrical signals are provided externally, wherein 1 path of FC interfaces is connected with an electrical interface FC node machine connector, and the 1 path of FC interface electrical signals are connected with FC electrical signals on the electrical interface FC node machine connector; in addition, the 1 channel FC interface is connected with a photoelectric transceiver, the photoelectric transceiver is connected to an optical port on the optical interface FC node machine connector through an FC optical interface, the FC interface electrical signal realizes photoelectric conversion through the photoelectric transceiver, and a related optical signal is connected to the FC optical interface and is connected with an optical signal on the optical interface FC node machine connector.
The 2 FC interfaces on the FPGA are obtained through FC-IP core instantiation, and the standard FC node machine is simulated functionally, so that point-to-point interconnection test of the FC interfaces and the FC node machine to be tested is realized. Meanwhile, the FC interface design provides 2 test modes: 1) a node machine-to-node testing mode; 2) and the test mode is surrounded, and the test mode can be selected to be adopted for testing through serial port input. Under the node machine to-node testing mode, the FC interface design simulates the function of the FC node machine, and the FPGA built-in processor realizes the communication management of the FC interface so as to realize the point-to-point FC transmission testing function with the tested FC node machine. Under the test mode of encircleing, the FC interface design is outside from encircleing the mode, and will follow the FC message that the FC interface received and send to the opposite terminal by this FC interface after encircleing by oneself through the outside again, under the test mode of encircleing, through the FPGA of JTAG interface connection quilt test FC node machine, carry out Ibert test through Xilinx ChipScope software, the test data stream realizes outside encircleing through the FC interface of FPGA design on the fault detection platform, with indexes such as test communication link stability and error rate. The FC interface can be selected to be used for testing through serial port input, and the test of the electrical interface FC interface module or the test of the optical interface FC interface module can be enabled and carried out.
(4) High speed signal design aspect of motherboard
The fault detection platform relates to transmission of high-speed serial data such as FC, PCIe and SRIO, strictly follows the design requirements of signal integrity and high-speed signal transmission in PCB design, has reasonable related layout and wiring, and adopts a high-speed connector to realize interconnection with an FC interface module to be tested so as to ensure stable transmission of test signals.
(5) Processor and processor circuit
Based on a processor and related storage, clock and reset circuits which are built in an FPGA (field programmable gate array), a fault detection platform under an SOPC (system on a chip) framework is constructed, and the processor circuit specifically comprise: the processor is arranged in the FPGA, and the storage circuit, the clock circuit, the reset circuit and the power circuit are arranged in the FPGA; the following functions are realized by a processor and a processor circuit:
1) selecting a test mode and an FC interface channel and printing a test result; 2) initializing a PCIe or SRIO standard host interface; 3) performing BIT test on resources on a tested FC node board; 4) performing equipment management and communication management on the FC node machine to be tested; 5) and carrying out communication management on the FC interface in the node machine pair test mode to realize point-to-point communication test with the FC node machine to be tested.
The fault detection platform provided by the embodiment of the invention can also select a test mode through serial port input before executing the test, select which FC interface to use for testing through the serial port input, and test the electric interface FC node machine or test the optical interface FC node machine.
In the specific implementation, under the node machine pair transmission test mode, the FC node machine function is simulated through the FC interface, and the FC interface is subjected to communication management through a processor built in the FPGA, so that the point-to-point FC transmission test function of the FC interface and the FC node machine to be tested is realized.
Under the surrounding test mode, the FC interface is set to be an external self-surrounding mode and used for sending FC information received from the FC interface to an opposite-end FC node machine to be tested after the FC information is automatically surrounded through the outside, under the surrounding test mode, the FPGA of the FC node machine to be tested is connected through the JTAG interface and the standard host interface, the test data flow is surrounded through the FC interface of the FPGA on the fault detection platform to achieve the external surrounding, and therefore the indexes such as the stability and the error rate of a communication link can be tested.
The fault detection platform of the FC node machine of the miniaturized standard serial host interface provided by the embodiment of the invention is designed based on the SOPC framework of the FPGA, and a CPU module is not required to be provided independently for detection; aiming at the point-to-point test of the FC port of the FC node machine, an FC simulation card or an FC node machine environment matched with an external embedded CPU environment does not need to be additionally constructed, and an FC interface is designed through FPGA logic to simulate an FC external node; the detection platform is designed to provide an electrical interface FC node machine connector and an optical interface FC node machine connector, so that different types of FC node machines can be tested; adaptation to FC node machines of different host interfaces such as PCIe/RapidIO can be realized by filling different FPGA logics, and related test functions can be improved and perfected by upgrading the logics; the processor runs a test program, so that automatic test can be realized, and a test result is displayed in real time through the serial port. The machine fault detection platform supports various FC electrical interface node machines and optical interface node machine products with PCIe/RapidIO standard host interfaces to test in two test modes, provides simulation FC nodes, has simplified structure compared with the traditional test environment, good universality and expansibility, and can automatically complete module detection and fault positioning work based on the fault detection platform.
Therefore, the fault detection platform in the embodiment of the invention has the following advantages:
1) the operation is convenient: the debugging mode of the product debugging tool and the CPU embedded host environment is separated, and the detection of the FC node machine can be realized by a single fault detection platform;
2) FC analog node: aiming at the point-to-point test of an FC port of an FC node machine, an FC simulation card or an FC node machine environment matched with an external embedded CPU environment does not need to be additionally constructed, and an FC interface is designed through FPGA logic to simulate an FC external node;
3) two test modes are provided: providing two test modes of a node machine pairing test and a surrounding test, and realizing point-to-point communication test with the FC node machine to be tested and providing an external surrounding test for the FC node machine to be tested;
4) the architecture is simplified: the SOPC framework based on the FPGA is designed, and a CPU module is not required to be provided independently for detection;
5) the universality is good: the detection platform is designed to provide an electrical interface FC node machine connector and an optical interface FC node machine connector, so that different types of FC node machines can be tested;
6) the expansibility is good: adaptation to FC node machines of different host interfaces such as PCIe/SRIO can be realized by filling different FPGA logics, and related test functions can be improved and perfected by upgrading the logics;
7) automated testing: the automatic test can be realized, and the test result can be displayed in real time through the serial port.
Claims (8)
1. A fault detection platform for a FC node machine having a standard serial host interface, the fault detection platform comprising: detecting a platform mother board and detecting a platform structural member;
the detection platform motherboard is arranged above the detection platform structural member, and is fixed through the detection platform structural member and dissipates heat to the detection platform motherboard;
the test platform motherboard includes: the system comprises an external interface unit, a standard host interface unit, an FC interface unit, an FPGA with a built-in processor and a processor circuit;
the fault detection platform is used for testing FC electrical interface node machines and optical interface node machines supporting various types with PCIe host interfaces or SRIO host interfaces in two test modes, wherein the two test modes comprise: the FC node machine pair test mode and the FC node machine surrounding test mode.
2. The FC node machine fault detection platform with a standard serial host interface of claim 1,
the standard host interface unit of the detection platform motherboard comprises: the system comprises a standard host interface, a host interface exchange chip, an electrical interface FC node machine connector and an optical interface FC node machine which are positioned on an FPGA;
the standard host interface unit is used for connecting a standard PCIe or SRIO host interface in the detection platform motherboard with the electric interface FC node machine and the optical interface FC node machine so as to realize adaptation with the FC node machine; the host interface switching core comprises an SRIO switching chip PCIe or an SRIO switching chip;
the host interface comprises a standard PCIe host interface and an SRIO host interface which are based on FPGA and obtained through IP core instantiation, and the external 2-path host interface is realized through a PCIe exchange chip or an SRIO exchange chip and is used for interconnecting PCIe interface signals or SRIO interface signals on 2 FC node machine connectors.
3. The FC node machine fault detection platform with a standard serial host interface of claim 2,
the external interface unit of the detection platform motherboard comprises: the system comprises an external serial port, a JTAG interface, an FC optical interface and a power interface;
the serial port is connected with the computer and used for displaying the test program and the test result running on the processor in real time through the computer;
the JTAG interface is respectively connected with 2 FC node machine connectors, and JTAG signals on the FC node machines are led out to the JTAG interface through the JTAG signal interconnection of the FC node machine connectors and the FC node machines;
the FC optical interface is an external optical communication interface of an FC interface unit configured on the detection platform, and is connected to the optical interface FC node machine and used for realizing interconnection with the optical communication interface of the optical interface FC node machine;
and the power interface is used for converting an external 220V power supply into a power supply of the platform, monitoring the working current of the platform in real time and supplying power for the test platform motherboard and the FC node machine.
4. The FC node machine fault detection platform with a standard serial host interface of claim 3,
the FC interface unit of the detection platform motherboard comprises: the system comprises 2 paths of FC interfaces and a photoelectric transceiver which are arranged in an FPGA and are used for providing 2 paths of FC electric signals to the outside, wherein 1 path of FC interfaces is connected with an FC node machine connector of an electric interface to realize the interconnection of the FC interface electric signals and the FC electric signals on the FC node machine connector of the electric interface; the other 1 channel of FC interface is connected with a photoelectric transceiver, the photoelectric transceiver is connected to an optical port on the optical interface FC node mechanical connector through an FC optical interface and is used for converting the channel of FC interface electrical signal into an FC interface optical signal through the photoelectric transceiver, and the FC interface optical signal is transmitted to the FC node machine through the FC optical interface and the optical port on the optical interface FC node mechanical connector;
the 2 FC interfaces on the FPGA are obtained through FC-IP core instantiation, and the standard FC node machine is simulated functionally, so that point-to-point interconnection test of the FC interfaces and the FC node machine to be tested is realized.
5. The FC node machine fault detection platform with a standard serial host interface of claim 4,
the processor and the processor circuit for detecting the platform motherboard comprise: the processor is arranged in the FPGA, and the storage circuit, the clock circuit, the reset circuit and the power circuit are arranged in the FPGA;
in the fault detection platform, the functions realized by the processor and the processor circuit comprise:
1) selecting a test mode and an FC interface channel and printing a test result;
2) initializing a PCIe or SRIO standard host interface;
3) performing BIT test on resources on a tested FC node board;
4) performing equipment management and communication management on the FC node machine to be tested;
5) and carrying out communication management on the FC interface in the node machine pair test mode to realize point-to-point communication test with the FC node machine to be tested.
6. The FC node machine fault detection platform with the standard serial host interface of any one of claims 1 to 5,
the fault detection platform is further used for selecting a test mode through serial port input and selecting which FC interface is adopted for testing through the serial port input before executing the test, and enabling the electric interface FC node machine to be tested or the optical interface FC node machine to be tested.
7. The FC node machine fault detection platform with a standard serial host interface of claim 6,
under the opposite-node machine testing mode, the FC interface is used for simulating the function of the FC node machine, and a processor built in the FPGA is used for carrying out communication management on the FC interface so as to realize the point-to-point FC transmission testing function of the FC interface and the FC node machine to be tested.
8. The FC node machine fault detection platform with a standard serial host interface of claim 7,
in the surrounding test mode, the FC interface is set to be in an external self-surrounding mode and is used for sending FC messages received from the FC interface to an opposite-end FC node machine to be tested after the FC messages are automatically surrounded through the outside, in the surrounding test mode, the FPGA of the FC node machine to be tested is connected through the JTAG interface and the standard host interface, and the test data flow realizes external surrounding through the FC interface of the FPGA on the fault detection platform so as to test indexes such as stability and error rate of a communication link.
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