CN104050061A - Multi-main-control-panel redundant backup system based on PCIe bus - Google Patents
Multi-main-control-panel redundant backup system based on PCIe bus Download PDFInfo
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Abstract
The invention discloses a multi-main-control-panel redundant backup system based on a PCIe bus. The system comprises a main board circuit A (12), a main board circuit B (13), a main board circuit C (14), a PCIe switching circuit (15), an FC channel card circuit (10) and a PCIeRaid card circuit (11). After the system is powered on, a test computer transmits an initial configuration file into a PCIe management chip (7), and then the PCIe management chip (7) writes the initial configuration file into a serial EEPROM (8) in a programming mode. After programming writing is completed, the system is restarted, and the PCIe management chip (7) reads the initial configuration file in the serial EEPROM (8) through an SMBus for the purpose of configuring a port register of the PCIe management chip (7), a partition pattern and a clock pattern. The multi-main-control-panel redundant backup system achieves real-time switching in a failure, and the real-time performance of the system is improved.
Description
Technical field
The present invention relates to a kind of many master control board redundancies standby system, particularly a kind of based on many master control board redundancies of PCIe bus standby system.
Background technology
Many master control board redundancies standby system is mainly used in the application of high safety, highly-reliable system, when system occurs carrying out localization of fault when abnormal and standby system switches.Many master control board redundancies standby system in the past, comprising: mainboard, PCI peripheral hardware board, board condition monitoring system, I2C controller, CPU processor and BMC controller.Board condition monitoring system is for voltage, electric current and temperature signal on analog input card, and whether detection system running status is normal.But many master control board redundancies standby system is in the past the fault-tolerant computer based on CPCI bus, in the time that standby system switches, computer system need be restarted so that PCI equipment is carried out to re-enumeration allocation space, this process can not meet the requirement of high-performance real-time computer, and the requirement of the high speed development that computer system based on cpci bus can not meet microprocessor, storer and interconnection network to the processing of data high-speed transfer.
Summary of the invention
The object of the present invention is to provide a kind ofly based on many master control board redundancies of PCIe bus standby system, while solving the computer system switched system of tradition based on cpci bus, need restart high speed development that computer system and cpci bus can not meet microprocessor, storer and the interconnection network problem to the processing of data high-speed transfer.
A kind of based on many master control board redundancies of PCIe bus standby system, comprise: motherboard circuit A, motherboard circuit B, motherboard circuit C, PCIe switched circuit, FC channel card circuit and PCIe Raid card circuit, wherein motherboard circuit A comprises: CPU processor A and PCIe controller A, motherboard circuit B comprises: CPU processor B and PCIe controller B, motherboard circuit C comprises: CPU processor C and PCIe controller C, PCIe switched circuit comprises: PCIe managing chip, serial EEPROM and clock chip.
PCIe controller A is two-way connection of port a with PCIe managing chip by PCIe bus, PCIe controller B is two-way connection of port b with PCIe managing chip by PCIe bus, PCIe controller C is two-way connection of port c with PCIe managing chip by PCIe bus, test computer is connected with PCIe managing chip is two-way by SMBus bus, FC channel card circuit is two-way connection of port e with PCIe managing chip by PCIe bus, and PCIe Raid card circuit is two-way connection of port d with PCIe managing chip by PCIe bus; In motherboard circuit A, CPU processor A and two-way connection of PCIe controller A; In motherboard circuit B, CPU processor B and two-way connection of PCIe controller B; In motherboard circuit C, CPU processor C and two-way connection of PCIe controller C; In PCIe switched circuit, PCIe managing chip is connected by SMBus bus is two-way with serial EEPROM, and the output terminal of clock chip is connected with the input end of PCIe managing chip.
After many master control board redundancies standby system based on PCIe bus powers on, first test computer is sent to initial configuration file in PCIe managing chip by SMBus bus, then PCIe managing chip passes through the total line writing of SMBus in serial EEPROM by initial configuration file, completes the programming of initial configuration file.The content of initial configuration file is the setting to PCIe managing chip, comprising: it is Combined-operating mode that port a is set, and port a, simultaneously as uplink port and non-transparent bridge, is expressed as P2P+NT, and the setting of port b is identical with port a; It is single mode of operation that port c is set, and port c, only as non-transparent bridge, is expressed as NT; It is single mode of operation that port d is set, and port d, only as downlink port, is expressed as P2P, and the setting of port e is identical with port d; Subregion k is set and comprises port a and port d; Subregion m is set and comprises port b and port e; Subregion n is set and comprises port c; The clock module that PCIe managing chip is set is global clock pattern.
After programming, restarting systems, PCIe managing chip reads the initial configuration file of serial EEPROM by SMBus bus, for port register, compartment model and the clock module of PCI allocation e managing chip.After configuration, PCIe managing chip is communicated with the port a in subregion k and port d, and now PCIe Raid card circuit is as the downstream PCIe equipment of CPU processor A; PCIe managing chip is communicated with the port b in subregion m and port e, and now FC channel card circuit is as the downstream PCIe equipment of CPU processor B; The mode of operation of subregion n middle port c is made as non-transparent bridge by PCIe managing chip, now CPU processor C does not have the PCIe equipment in downstream, CPU processor C is as spare main plate circuit, for taking over CPU processor A or CPU processor B corresponding downstream PCIe equipment while breaking down; PCIe managing chip provides global clock by clock chip.Then, CPU processor A carries out PCIe device scan completion system to PCIe Raid card circuit and enumerates, CPU processor B is carried out PCIe device scan completion system to FC channel card circuit and is enumerated, CPU processor C carries out equally PCIe device scan completion system and enumerates, the last normal operating system starting separately.
After CPU processor A, CPU processor B, CPU processor C normally start separately operating system, send heartbeat message by non-transparent bridge to CPU processor C by CPU processor A, CPU processor B, if CPU processor C received respectively the heartbeat message that CPU processor A and CPU processor B send in 1 second, CPU processor C, still in stand-by state, continues to detect the heartbeat message of CPU processor A and the transmission of CPU processor B.When CPU processor A occurs when abnormal, CPU processor A stops sending heartbeat message to CPU processor C, CPU processor C did not receive the heartbeat message that CPU processor A is sent in 1 second, trigger the fault recovery function of CPU processor C: change the mode of operation of PCIe managing chip port c into uplink port by non-transparent bridge dynamically by CPU processor C and add non-transparent bridge, port d in PCIe managing chip subregion k is removed, PCIe managing chip port d is joined to subregion n, the mode of operation of PCIe managing chip port a is added to non-transparent bridge by uplink port and change non-transparent bridge into.Then CPU processor C carries out the re-enumeration of PCIe scan bus and equipment, to identify the PCIe Raid card circuit arrangement that newly joins CPU processor C.The port c of PCIe managing chip and port d are communicated with and belong to same subregion n like this, and PCIe Raid card circuit transfers the PCIe equipment as CPU processor C to as the PCIe equipment of CPU processor A.When CPU processor B occurs when abnormal, its processing procedure and CPU processor A occur when abnormal identical.
In the time that CPU processor A, CPU processor B duty are all abnormal, trigger equally the fault recovery function of CPU processor C: change the mode of operation of the corresponding PCIe managing chip of CPU processor C port c into uplink port by non-transparent bridge dynamically and add non-transparent bridge, the downstream PCIe equipment of CPU processor A, CPU processor B is all switched to the downstream PCIe equipment of CPU processor C, the mode of operation of CPU processor A, the corresponding PCIe managing chip port a of CPU processor B and port b is added to non-transparent bridge by uplink port dynamically and change non-transparent bridge into.
The present invention has realized the many master control board redundancies standby system based on PCIe bus, makes system can tackle the even a few situations that mainboard is abnormal of certain piece, has improved the ability to ward off risks of system; Be applicable to the occasion that system stability, reliability tool are had high requirements.
Brief description of the drawings
A kind of structural representation based on many master control board redundancies of PCIe bus standby system of Fig. 1.
1.CPU processor A 2.PCIe controller A 3. CPU processor B 4. PCIe controller B 5.CPU processor C 6.PCIe controller C 7.PCIe managing chip 8. serial EEPROM 9. clock chip 10. FC channel card circuit 11. PCIe Raid card circuit 12. motherboard circuit A 13. motherboard circuit B 14. motherboard circuit C 15.PCIe switched circuits.
Embodiment
A kind of based on many master control board redundancies of PCIe bus standby system, comprise: motherboard circuit A12, motherboard circuit B13, motherboard circuit C14, PCIe switched circuit 15, FC channel card circuit 10 and PCIe Raid card circuit 11, wherein motherboard circuit A12 comprises: CPU processor A 1 and PCIe controller A2, motherboard circuit B13 comprises: CPU processor B 3 and PCIe controller B4, motherboard circuit C14 comprises: CPU processor C5 and PCIe controller C6, PCIe switched circuit 15 comprises: PCIe managing chip 7, serial EEPROM 8 and clock chip 9.
PCIe controller A2 is two-way connection of port a with PCIe managing chip 7 by PCIe bus, PCIe controller B4 is two-way connection of port b with PCIe managing chip 7 by PCIe bus, PCIe controller C6 is two-way connection of port c with PCIe managing chip 7 by PCIe bus, test computer is connected with PCIe managing chip 7 is two-way by SMBus bus, FC channel card circuit 10 is two-way connection of port e with PCIe managing chip 7 by PCIe bus, and PCIe Raid card circuit 11 is two-way connection of port d with PCIe managing chip 7 by PCIe bus; In motherboard circuit A12, CPU processor A 1 and two-way connection of PCIe controller A2; In motherboard circuit B13, CPU processor B 3 and two-way connection of PCIe controller B4; In motherboard circuit C14, CPU processor C5 and two-way connection of PCIe controller C6; In PCIe switched circuit 15, PCIe managing chip 7 is connected by SMBus bus is two-way with serial EEPROM 8, and the output terminal of clock chip 9 is connected with the input end of PCIe managing chip 7.
After many master control board redundancies standby system based on PCIe bus powers on, first test computer is sent to initial configuration file in PCIe managing chip 7 by SMBus bus, then PCIe managing chip 7 passes through the total line writing of SMBus in serial EEPROM 8 by initial configuration file, completes the programming of initial configuration file.The content of initial configuration file is the setting to PCIe managing chip 7, comprising: it is Combined-operating mode that port a is set, and port a, simultaneously as uplink port and non-transparent bridge, is expressed as P2P+NT, and the setting of port b is identical with port a; It is single mode of operation that port c is set, and port c, only as non-transparent bridge, is expressed as NT; It is single mode of operation that port d is set, and port d, only as downlink port, is expressed as P2P, and the setting of port e is identical with port d; Subregion k is set and comprises port a and port d; Subregion m is set and comprises port b and port e; Subregion n is set and comprises port c; The clock module that PCIe managing chip 7 is set is global clock pattern.
After programming, restarting systems, PCIe managing chip 7 reads the initial configuration file of serial EEPROM 8 by SMBus bus, for port register, compartment model and the clock module of PCI allocation e managing chip 7.After configuration, PCIe managing chip 7 is communicated with the port a in subregion k and port d, and now PCIe Raid card circuit 11 is as the downstream PCIe equipment of CPU processor A 1; PCIe managing chip 7 is communicated with the port b in subregion m and port e, and now FC channel card circuit 10 is as the downstream PCIe equipment of CPU processor B 3; The mode of operation of subregion n middle port c is made as non-transparent bridge by PCIe managing chip 7, now CPU processor C5 does not have the PCIe equipment in downstream, CPU processor C5 is as spare main plate circuit, for taking over CPU processor A 1 or CPU processor B 3 corresponding downstream PCIe equipment while breaking down; PCIe managing chip 7 provides global clock by clock chip 9.Then, CPU processor A 1 carries out PCIe device scan completion system to PCIe Raid card circuit 11 and enumerates, CPU processor B 3 is carried out PCIe device scan completion system to FC channel card circuit 10 and is enumerated, CPU processor C5 carries out equally PCIe device scan completion system and enumerates, the last normal operating system starting separately.
After CPU processor A 1, CPU processor B 3, CPU processor C5 normally start separately operating system, send heartbeat message by non-transparent bridge to CPU processor C5 by CPU processor A 1, CPU processor B 3, if CPU processor C5 received respectively the heartbeat message that CPU processor A 1 and CPU processor B 3 send in 1 second, CPU processor C5, still in stand-by state, continues the heartbeat message that detection CPU processor A 1 and CPU processor B 3 send.When CPU processor A 1 occurs when abnormal, CPU processor A 1 stops sending heartbeat message to CPU processor C5, CPU processor C5 did not receive the heartbeat message that CPU processor A 1 is sent in 1 second, trigger the fault recovery function of CPU processor C5: change the mode of operation of PCIe managing chip 7 port c into uplink port by non-transparent bridge dynamically by CPU processor C5 and add non-transparent bridge, port d in PCIe managing chip 7 subregion k is removed, PCIe managing chip 7 port d are joined to subregion n, the mode of operation of PCIe managing chip 7 port a is added to non-transparent bridge by uplink port and change non-transparent bridge into.Then CPU processor C5 carries out the re-enumeration of PCIe scan bus and equipment, to identify PCIe Raid card circuit 11 equipment that newly join CPU processor C5.The port c of PCIe managing chip 7 and port d are communicated with and belong to same subregion n like this, and PCIe Raid card circuit 11 transfers the PCIe equipment as CPU processor C5 to as the PCIe equipment of CPU processor A 1.When CPU processor B 3 occurs when abnormal, its processing procedure and CPU processor A 1 occur when abnormal identical.
In the time that CPU processor A 1, CPU processor B 3 duties are all abnormal, trigger equally the fault recovery function of CPU processor C5: change the mode of operation of the corresponding PCIe managing chip of CPU processor C5 7 port c into uplink port by non-transparent bridge dynamically and add non-transparent bridge, the downstream PCIe equipment of CPU processor A 1, CPU processor B 3 is all switched to the downstream PCIe equipment of CPU processor C5, the mode of operation of CPU processor A 1, the corresponding PCIe managing chip 7 port a of CPU processor B 3 and port b is added to non-transparent bridge by uplink port dynamically and change non-transparent bridge into.
Claims (1)
1. one kind based on many master control board redundancies of PCIe bus standby system, it is characterized in that comprising: motherboard circuit A(12), motherboard circuit B(13), motherboard circuit C(14), PCIe switched circuit (15), FC channel card circuit (10) and PCIe Raid card circuit (11), wherein motherboard circuit A(12) comprising: CPU processor A (1) and PCIe controller A(2), motherboard circuit B(13) comprising: CPU processor B (3) and PCIe controller B(4), motherboard circuit C(14) comprising: CPU processor C(5) and PCIe controller C(6), PCIe switched circuit (15) comprising: PCIe managing chip (7), serial EEPROM (8) and clock chip (9),
PCIe controller A(2) by two-way connection of port a of PCIe bus and PCIe managing chip (7), PCIe controller B(4) by two-way connection of port b of PCIe bus and PCIe managing chip (7), PCIe controller C(6) by two-way connection of port c of PCIe bus and PCIe managing chip (7), test computer is by SMBus bus and two-way connection of PCIe managing chip (7), FC channel card circuit (10) is two-way connection of port e with PCIe managing chip (7) by PCIe bus, PCIe Raid card circuit (11) is two-way connection of port d with PCIe managing chip (7) by PCIe bus, at motherboard circuit A(12) in, CPU processor A (1) and PCIe controller A(2) two-way connection, at motherboard circuit B(13) in, CPU processor B (3) and PCIe controller B(4) two-way connection, at motherboard circuit C(14) in, CPU processor C(5) with PCIe controller C(6) two-way connection, in PCIe switched circuit (15), PCIe managing chip (7) is connected by SMBus bus is two-way with serial EEPROM (8), and the output terminal of clock chip (9) is connected with the input end of PCIe managing chip (7),
After many master control board redundancies standby system based on PCIe bus powers on, first test computer is sent to initial configuration file in PCIe managing chip (7) by SMBus bus, then PCIe managing chip (7) passes through the total line writing of SMBus in serial EEPROM (8) by initial configuration file, completes the programming of initial configuration file; The content of initial configuration file is the setting to PCIe managing chip (7), comprising: it is Combined-operating mode that port a is set, and port a, simultaneously as uplink port and non-transparent bridge, is expressed as P2P+NT, and the setting of port b is identical with port a; It is single mode of operation that port c is set, and port c, only as non-transparent bridge, is expressed as NT; It is single mode of operation that port d is set, and port d, only as downlink port, is expressed as P2P, and the setting of port e is identical with port d; Subregion k is set and comprises port a and port d; Subregion m is set and comprises port b and port e; Subregion n is set and comprises port c; The clock module that PCIe managing chip (7) is set is global clock pattern;
After programming, restarting systems, PCIe managing chip (7) reads the initial configuration file of serial EEPROM (8) by SMBus bus, for port register, compartment model and the clock module of PCI allocation e managing chip (7); After configuration, PCIe managing chip (7) is communicated with the port a in subregion k and port d, and now PCIe Raid card circuit (11) is as the downstream PCIe equipment of CPU processor A (1); PCIe managing chip (7) is communicated with the port b in subregion m and port e, and now FC channel card circuit (10) is as the downstream PCIe equipment of CPU processor B (3); The mode of operation of subregion n middle port c is made as non-transparent bridge by PCIe managing chip (7), now CPU processor C(5) there is no the PCIe equipment in downstream, CPU processor C(5) as spare main plate circuit, for taking over CPU processor A (1) or CPU processor B (3) corresponding downstream PCIe equipment while breaking down; PCIe managing chip (7) provides global clock by clock chip (9); Then, CPU processor A (1) carries out PCIe device scan completion system to PCIe Raid card circuit (11) and enumerates, CPU processor B (3) is carried out PCIe device scan completion system to FC channel card circuit (10) and is enumerated, CPU processor C(5) carry out equally PCIe device scan completion system and enumerate, the last normal operating system starting separately;
Until CPU processor A (1), CPU processor B (3), CPU processor C(5) normally start separately after operating system, by CPU processor A (1), CPU processor B (3) by non-transparent bridge to CPU processor C(5) send heartbeat message, if CPU processor C(5) in 1 second, receive respectively the heartbeat message that CPU processor A (1) and CPU processor B (3) send, CPU processor C(5) still in stand-by state, continue to detect the heartbeat message of CPU processor A (1) and CPU processor B (3) transmission, when CPU processor A (1) occurs when abnormal, CPU processor A (1) stops to CPU processor C(5) transmission heartbeat message, CPU processor C(5) in 1 second, do not receive the heartbeat message that CPU processor A (1) is sent, trigger CPU processor C(5) fault recovery function: by CPU processor C(5) change the mode of operation of PCIe managing chip (7) port c into uplink port by non-transparent bridge dynamically and add non-transparent bridge, port d in PCIe managing chip (7) subregion k is removed, PCIe managing chip (7) port d is joined to subregion n, the mode of operation of PCIe managing chip (7) port a is added to non-transparent bridge by uplink port and change non-transparent bridge into, then CPU processor C(5) carry out the re-enumeration of PCIe scan bus and equipment, newly join CPU processor C(5 to identify) PCIe Raid card circuit (11) equipment, the port c of PCIe managing chip (7) and port d are communicated with and belong to same subregion n like this, and PCIe Raid card circuit (11) transfers to as CPU processor C(5 as the PCIe equipment of CPU processor A (1)) PCIe equipment, when CPU processor B (3) occurs when abnormal, its processing procedure and CPU processor A (1) occur when abnormal identical,
When CPU processor A (1), when CPU processor B (3) duty is all abnormal, trigger equally CPU processor C(5) fault recovery function: by CPU processor C(5) mode of operation of corresponding PCIe managing chip (7) port c changes uplink port into by non-transparent bridge dynamically and adds non-transparent bridge, by CPU processor A (1), the downstream PCIe equipment of CPU processor B (3) is all switched to CPU processor C(5) downstream PCIe equipment, by CPU processor A (1), the mode of operation of the corresponding PCIe managing chip of CPU processor B (3) (7) port a and port b adds non-transparent bridge by uplink port dynamically and changes non-transparent bridge into.
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| CN116049044B (en) * | 2023-03-28 | 2023-06-23 | 飞腾信息技术有限公司 | Control method of pcie equipment, computer equipment and system on chip |
| CN116881053A (en) * | 2023-09-06 | 2023-10-13 | 苏州浪潮智能科技有限公司 | Data processing method, exchange board, data processing system and data processing device |
| CN116881053B (en) * | 2023-09-06 | 2023-11-17 | 苏州浪潮智能科技有限公司 | Data processing method, exchange board, data processing system and data processing device |
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