CN116049044B - Control method of pcie equipment, computer equipment and system on chip - Google Patents

Control method of pcie equipment, computer equipment and system on chip Download PDF

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Publication number
CN116049044B
CN116049044B CN202310309557.2A CN202310309557A CN116049044B CN 116049044 B CN116049044 B CN 116049044B CN 202310309557 A CN202310309557 A CN 202310309557A CN 116049044 B CN116049044 B CN 116049044B
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root port
upstream
equipment
pcie
root
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CN116049044A (en
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朱佳平
朱青山
张明
刘明振
田雅芳
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Phytium Technology Co Ltd
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Phytium Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides a pcie device control method, a computer device and a system-on-chip, wherein the method is applied to the system-on-chip, the system-on-chip comprises a root complex RC device and an upstream device connected with the RC device, the RC device comprises at least one root port, and the method comprises the following steps: and under the condition that a first root port of the RC equipment is closed, the upstream equipment sends a first instruction to the RC equipment, wherein the first instruction carries first state information, and the first state information is used for representing that the first root port is closed. By the method, each party of the system on chip can confirm that the root port of the RC equipment is closed, so that the system power consumption can be reduced.

Description

Control method of pcie equipment, computer equipment and system on chip
Technical Field
The present application relates to the field of computer technologies, and in particular, to a pcie device control method, a computer device, and a system on a chip.
Background
The structure of a pc ie (peripheralcomponent interconnect express, high-speed serial computer expansion bus standard) system of a computer is usually fixed, i.e. several Root Ports (RP) exist in a Root Complex (RC) device, which is well established in hardware. In this structure, the system supports the running power consumption of all RPs in the RC, and even if the RP fails or there is no external device, additional power consumption is generated, thereby wasting the system power consumption.
Disclosure of Invention
Based on the above state of the art, the present application proposes a pcie device control method, a computer device and a system on chip, which can be used to reduce the root port power consumption in a pcie bus system.
In order to achieve the technical purpose, the application provides the following technical scheme:
in a first aspect, the present application proposes a pcie device control method, which is applied to a system on a chip, where the system on a chip includes a root complex RC device and an upstream device connected to the RC device, where the RC device includes at least one root port, and the method includes:
and under the condition that a first root port of the RC equipment is closed, the upstream equipment sends a first instruction to the RC equipment, wherein the first instruction carries first state information, and the first state information is used for representing that the first root port is closed.
In the method, an upstream device connected with the RC device can send a first instruction representing that a first root port in the RC device is closed to the RC device in the condition that the first root port is closed. The scheme can adapt to the working mode that the root port of the RC equipment is closed, and the upstream equipment can inform the RC equipment in time under the condition that the root port of the RC equipment is confirmed to be closed, so that all parties of the system on chip know the state that the root port is closed, the effective closing of the root port of the system on chip is realized, and the power consumption of the system can be reduced.
In some embodiments, the system on a chip further comprises a first clock circuit coupled to the first root port for providing a clock signal to the first root port;
the method further comprises the steps of:
the upstream device sends a second instruction to the first clock circuit, the second instruction being used to control the first clock circuit to turn off.
In the method, the upstream device sends an instruction to the first clock circuit for providing the clock signal for the first root port under the condition that the first root port is confirmed to be closed, and controls the first clock circuit to be closed, so that the system clock power consumption can be reduced.
In some embodiments, the method further comprises: the upstream device closes a first root port of the RC device.
In the method, the upstream device can actively close the root port of the RC device, so that the root port can be closed under appropriate conditions, and the power consumption of the root port of the RC device is reduced.
In some embodiments, the upstream device closes a first root port of the RC device, comprising:
the upstream device sets a port state parameter of the first root port to a target parameter value, the target parameter value representing port closure.
In the method, the upstream equipment realizes the closing of the first root port by modifying the port state parameter of the first root port, the implementation mode is more convenient and easy to execute, and the upstream equipment can realize the closing of the first root port without actually accessing the first root port.
In some embodiments, the method further comprises:
the upstream device detects whether a first root port of the RC device is idle and/or fails;
in the event that the first root port of the RC device is confirmed to be idle and/or malfunctioning, the upstream device closes the first root port of the RC device.
In the method, the upstream equipment detects the state of the first root port at first, and closes the first root port under the condition of ensuring that the first root port is idle and/or fails, so that the first root port is prevented from being closed by mistake, and the influence on the system work caused by the fact that the first root port is closed by mistake can be effectively avoided.
In some embodiments, the RC device further comprises a master bridge for connecting the upstream device and the at least one root port;
the upstream device sending a first instruction to the RC device, comprising:
The upstream device sends a first instruction to the master bridge.
In the method, the communication connection between the upstream equipment and the RC equipment is realized through the main equipment bridge, and the application of the main equipment bridge realizes the communication route between the upstream equipment and each root port of the RC equipment, thereby improving the communication efficiency.
In a second aspect, the present application proposes another pcie device control method, which is applied to a system on a chip, the system on a chip including a root complex RC device and an upstream device connected to the RC device, the RC device including at least one root port, the method comprising:
the RC equipment receives a first instruction sent by the upstream equipment, wherein the first instruction carries first state information, and the first state information is used for representing that a first root port in the RC equipment is closed.
In the method, the upstream device sends a first instruction representing that the first root port is closed to the RC device, so that the RC device can timely know that the first root port is closed, the RC device can timely adjust the state record of the first root port, operation and power consumption support corresponding to the first root port are stopped, and system power consumption can be reduced.
In some embodiments, the method further comprises:
the RC device sets a state identifier of the first root port to a closed state based on the first instruction.
In the method, after receiving a first instruction sent by upstream equipment, RC equipment sets a state identifier of a first root port according to the first instruction, so that the real-time state of the first root port can be accurately reflected through the state identifier of the first root port.
In some embodiments, the RC device further comprises a master bridge for connecting the upstream device and the at least one root port;
the RC equipment receives a first instruction sent by the upstream equipment, and the first instruction comprises:
the master device bridge receives a first instruction sent by the upstream device.
In the method, the communication connection between the upstream equipment and the RC equipment is realized through the main equipment bridge, and the application of the main equipment bridge realizes the communication route between the upstream equipment and each root port of the RC equipment, thereby improving the communication efficiency.
In a third aspect, the present application proposes a computer device comprising a system on chip as described in any one of the preceding claims.
In a system on a chip included in the computer device, an upstream device connected to the RC device can send a first instruction to the RC device indicating that a first root port in the RC device is closed. The system on chip can adapt to the working mode that the root port of the RC equipment is closed, and the upstream equipment can inform the RC equipment in time under the condition that the root port of the RC equipment is confirmed to be closed, so that all parties of the system on chip can know the state that the root port is closed, the effective closing of the root port of the system on chip is realized, and the power consumption of the system can be reduced.
In a fourth aspect, the present application proposes a system on a chip, comprising a root complex RC device and an upstream device connected to the RC device, the RC device comprising at least one root port;
the upstream device is used for executing the pcie device control method executed by the upstream device;
the RC equipment is used for executing the pcie equipment control method executed by the RC equipment.
In the system on chip, an upstream device connected with the RC device can send a first instruction to the RC device, wherein the first instruction indicates that a first root port in the RC device is closed. The system on chip can adapt to the working mode that the root port of the RC equipment is closed, and the upstream equipment can inform the RC equipment in time under the condition that the root port of the RC equipment is confirmed to be closed, so that all parties of the system on chip can know the state that the root port is closed, the effective closing of the root port of the system on chip is realized, and the power consumption of the system can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
Fig. 1 is a schematic topology diagram of a pcie bus system according to an embodiment of the present application.
Fig. 2 is a schematic diagram of an internal structure of an RC device according to an embodiment of the present application.
Fig. 3 is an application scenario schematic diagram of the pcie bus system provided in the embodiment of the present application.
Fig. 4 is a schematic process flow diagram of a pcie device control method and a pcie device scanning method provided in an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a system on chip according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of another system-on-chip provided in an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The high speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) is commonly used in data communications for computer systems, such as for communication between a processor and a high speed peripheral. In practice, the pcie bus system comprises a plurality of components that are interconnected point-to-point.
Fig. 1 shows a topology of a pcie bus system. Referring to fig. 1, the topology structure of the pcie bus system is a tree topology structure, and mainly includes pcie nodes such as Root Complex (RC) devices, switch devices (switches), terminal (EP) devices, and pcie-pci bridges (pcie-pci Bridge).
The RC device is a root of the PCIE bus, and may be located in a System On Chip (SOC), and connects an upstream device such as a processor (Central Processing Unit, CPU) and a Memory (Memory) in the SOC to the PCIE bus, and realizes connection between the upstream device and a downstream device such as a switching device, an EP device and a PCIE-PCI bridge mounted on the upstream device through the PCIE bus. The main function of the RC equipment is to complete address conversion from a memory domain to a pcie bus domain, interfaces of the pcie bus system and the peripheral equipment can be integrated in the RC equipment, a plurality of pcie interfaces can be led out, and each interface can be connected with a pcie node. The RC equipment can acquire the request information transmitted by the pcie node so as to access the memory, and correspondingly, the RC equipment can also send the request information of the processor to the EP equipment mounted on the system so as to realize the communication between the processor and the EP equipment.
The main function of the switching device is to extend the pcie link, and each data link of the pcie bus only covers two devices, which cannot meet the requirement, so that the switching device can be used for extending the pcie link.
EP devices, which may be understood as devices implementing independent functions in the pcie bus system, often support different functions, so that the pcie bus system as a whole can support diverse application functions. In practical application, EP equipment with typical meaning includes a graphics card, a network card, and the like, and meanwhile, the EP equipment is also an initiator and a responder of a pcie transaction.
The main role of the pcie-pci bridge is to make efficient compatibility with the second generation external component interconnect standard (peripheral component interconnect, pci), which is capable of supporting two functions: 1. the pcie bus system can be converted, so that a pci bus is obtained and stably connected with the pci equipment. 2. The method can effectively convert the pci bus, so that the pcie bus is obtained and is connected with the pcie node.
It should be understood that fig. 1 is only an example of a topology structure diagram of a pcie bus system, and in other examples, the switching device may be disposed inside the system on a chip, or a pcie-pci bridge may be disposed outside the system on a chip, etc., and the topology structure of a similar pcie bus system is not described in detail.
Fig. 2 shows a schematic diagram of the internal structure of an RC device. Referring to fig. 2, the RC includes a Host Bridge (HPB) therein, and the Host Bridge connects a plurality of Root Ports (RP). In fig. 2, there are illustrated 4 root ports in the RC device, and in fact, the number of root ports of the RC device may be flexibly set according to the requirements or according to the performance of the RC device.
The master bridge HPB is connected to the upstream device of the RC device and to the respective root ports RP of the RC device. Based on the connection relationship, the main device bridge HPB serves as a bridge between the upstream device of the RC device and the root port RP of the RC device, so as to realize data communication and routing between the upstream device of the RC device and the root port RP of the RC device.
The root port RP is used as an interface for carrying out data communication between the terminal equipment and the RC equipment and can be used for connecting the terminal equipment, so that the mounting of the terminal equipment on the RC equipment is realized. The plurality of root ports RP are numbered sequentially in the RC device to facilitate differentiation and addressing.
In connection with the above description, fig. 3 shows a schematic view of an application scenario of the pcie bus system. Referring to fig. 3, the processor may be connected to a plurality of RC devices at the same time, and the RC devices may be pre-numbered according to a sequence to facilitate distinguishing and management, and the RC devices are directly connected to the EP devices in a point-to-point manner through the root port RP.
In practical applications, the processor typically traverses the tree structure of the pcie bus system using a depth-first algorithm (Breadth First Serach, BFS) to implement an enumeration scan of the pcie device. Through the enumeration scanning, the processor can discover the pcie equipment in the whole system, and configure the pcie equipment discovered by scanning before normal use; if a certain pcie device is not found in the enumeration scanning process, the corresponding device will not be used subsequently, and therefore no access is requested to the pcie device subsequently.
The processor, while traversing the pcie tree structure, reads the device identifier of each device, for example, reads the Vendor ID of the device, if the read value is not FFFF, it indicates that there is a device in this location, and if it is FFFF, it indicates that there is no device. The VendorID is data fixed in the configuration space of the pcie device when leaving the factory, and represents each different device, and similarly, the processor can also find the designated pcie device through the VendorID value.
Referring to the pcie tree structure shown in fig. 3, it is not known to the CPU how the pcie tree is, at first, only knowing the existence of Bus0, what devices are under Bus 0. So CPU starts from Bus0, device0, first reads the Vendor ID of Fun0 in device0, if the returned value is not FFFF, then indicates the existence of the device, and continues to the next step; if FFFF is returned, then Fun0 is not present in device0, so the device is not present, continue probing Bus0, device1, fun0, and so on.
In the enumeration scanning process, the request of reading the VendorID sent by the CPU reaches the master device bridge HPB first, and the master device bridge HPB determines to which root port RP the current request needs to be forwarded, and then directly forwards the request to the root port RP for further processing. When receiving a request for reading the Vendor ID, the root port RP detects whether a pcie terminal device is connected under the root port RP, if the pcie terminal device is connected, a valid Vendor ID value of non-FFFF is returned, so that a CPU is informed that the current root port RP exists in a pcie device tree, and the next operation can be performed; if the pcie device is not connected, the FFFF is returned, so that the CPU is informed that the current root port is not connected with the pcie device.
In practical applications, the structure of the pcie bus system of a computer system is usually fixed, i.e. there are several Root Ports (RP) in a Root Complex (RC) device, which is well established in hardware. In this structure, the system supports the running power consumption of all RPs in the RC, and even if the RP fails or there is no external device, additional power consumption is generated, thereby wasting the system power consumption.
Based on the above problems, the embodiments of the present application provide a pcie device control method, which is applied to a system on a chip, where the system on a chip includes a root complex RC device and an upstream device connected to the RC device, where the RC device includes at least one root port RP.
Referring to fig. 4, the above-mentioned pcie device control method includes:
s101, an upstream device of the RC device detects whether a first root port of the RC device is idle and/or fails.
The upstream device of the RC device may be a processor, a memory, or the like. The first root port of the RC device represents any one or more of all root ports RP of the RC device.
Before enumeration scanning is performed on the pcie bus system, upstream equipment of the RC equipment detects the state of a root port of the RC equipment, confirms whether the root port is idle or not, and confirms whether the root port is faulty or not. The root port RP being idle means that the root port RP is not connected to the pcie terminal device, and the root port RP is unavailable if the root port RP fails.
Illustratively, the upstream device monitors whether the root port RP of the RC device is idle and/or failed, may confirm whether the root port RP is idle by reading a configuration file of the root port RP, and may confirm whether the root port RP is failed by sending handshake signals with the root port RP.
Or, the staff can send information or write information to the upstream device under the condition of confirming that the root port RP of the RC device is idle or faulty, so as to actively inform the upstream device that the root port RP of the RC device is idle and/or faulty.
In case it is confirmed that the first root port of the RC device is idle and/or failed, the upstream device of the RC device performs step S102, closing the first root port of the RC device.
Specifically, when the upstream device confirms that the first root port of the RC device is idle and/or fails, it may be determined that no valid pcie terminal device exists under the first root port. At this time, the upstream device controls the first root port to be closed, so that the system power consumption can be reduced.
As an example, the upstream device may send a close instruction to the first root port to control the first root port to close, or the upstream device may send a request to the computer system to cause the computer system to control the first root port of the RC device to close.
As another preferred embodiment, the upstream device implements the closing of the first root port by modifying a port state parameter of the first root port.
In particular, the system-on-chip is capable of initializing various hardware components of the system-on-chip by running program code of the system-on-chip, such as running system-on-chip firmware. In the program code of the system on chip, there is a port state parameter corresponding to the first root port of the RC device, where the port state parameter of the first root port is used to indicate the on-off state of the first root port, that is, may be used to indicate whether the first root port is closed. By modifying the port state parameter of the first root port, the program code can correspondingly operate the first root port when initializing the first root port.
Based on the above system structural feature, when the upstream device needs to close the first root port of the RC device, the port state parameter of the corresponding first root port in the on-chip system program code is set to be a target parameter value indicating that the port is closed. For example, assuming that a port is closed by 0 and open by 1, the upstream device may set the port state parameter of the corresponding first root port in the system-on-chip program code to 0.
After the upstream device sets the port state parameter of the first root port of the RC device to the target parameter value representing the port closing, when the on-chip system program code runs, for example, when the on-chip system is powered on and initialized, the first root port is initialized to the closing state, so that the closing of the first root port is realized.
In case it is confirmed that the first root port of the RC device is closed, the upstream device performs step S103, sending a first instruction to the main device bridge of the RC device.
The first instruction carries first state information, and the first state information is used for representing that the first root port is closed.
It will be appreciated that the upstream device, upon confirming that the first root port of the RC device is closed, sends an instruction to the RC device informing the RC that its first root port has been closed.
Specifically, referring to the pcie system structure schematic diagram shown in fig. 3, the upstream device is connected to the RC device, and specifically, the upstream device is connected to the main device bridge HPB of the RC device.
Thus, the upstream device sends a first instruction to the RC device, in particular to the primary device bridge HPB of the RC device, so that the primary device bridge HPB knows that the first root port connected thereto has been closed.
S104, the upstream device sends a second instruction to the first clock circuit.
The first clock circuit is a clock circuit which is arranged on the system on chip and is connected with the first root port and used for providing a clock signal for the first root port.
The first clock circuit may be disposed inside or outside the RC device, which is not limited in the embodiment of the present application, and meanwhile, a specific circuit structure, a working mode, and the like of the first clock circuit are not limited. In theory, in a computer system or the above-mentioned system on chip, a clock circuit capable of providing a clock signal to the first root port may be used as the above-mentioned first clock circuit.
When the upstream device confirms that the first root port is closed, a second instruction is sent to the first clock circuit to control the first clock circuit to be closed, so that the clock of the first root port is closed under the condition that the first root port is closed, and the clock power consumption is reduced.
It should be noted that the execution sequence of the steps S103 and S104 may be flexibly adjusted, the step S103 may be executed first, the step S104 may be executed first, the step S103 may be executed second, or the step S103 and the step S104 may be executed simultaneously.
S105, a main device bridge of the RC device receives a first instruction sent by an upstream device.
Specifically, corresponding to the upstream device executing the step S103, the RC device may receive the first instruction, and through the first state information in the first instruction, the RC device may determine that the first root port in the RC device has been closed.
Referring to the pcie system structure schematic diagram shown in fig. 3, the upstream device is connected to the RC device, specifically, the upstream device is connected to the main device bridge HPB of the RC device.
Thus, the RC device receives the first instruction from the upstream device, in particular the primary device bridge HPB of the RC device receives the first instruction sent by the upstream device, so that the primary device bridge HPB knows that the first root port connected thereto has been closed.
S106, the main equipment bridge of the RC equipment sets the state identifier of the first root port to be in a closed state based on the first instruction.
Specifically, a state identifier of the corresponding first root port is stored in the RC device, where the state identifier is used to represent a switch state of the first root port.
When the RC equipment receives the first instruction and confirms that the first root port is closed based on the first instruction, the state identifier corresponding to the first root port is set to be in a closed state.
Referring to the description of step S105, in a real scenario, since the first instruction is sent by the upstream device received by the master device bridge HPB, when step S106 is performed, the state identifier of the first root port is set to the off state by the master device bridge HPB in the RC device based on the first instruction.
At this point, the state identification of the first root port may be stored in the host bridge HPB.
Through the above processing procedure, it can be understood that the control method of the pcie device provided by the embodiment of the present application realizes that the RC device is controlled to be turned off by the upstream device of the RC device, so that the root port can be turned off in time when the root port of the RC device fails or the external device is not connected, and the system power consumption can be reduced. And in the method, an upstream device connected with the RC device can send a first instruction representing that a first root port in the RC device is closed to the RC device in the condition that the first root port in the RC device is closed. The scheme can adapt to the working mode that the root port of the RC equipment is closed, and the upstream equipment can inform the RC equipment in time under the condition that the root port of the RC equipment is confirmed to be closed, so that all parties of the system on chip know the state that the root port is closed, the effective closing of the root port of the system on chip is realized, and the system power consumption is reduced.
The processing procedure realizes the effective closing of the first root port of the RC equipment, and the upstream equipment can inform the RC equipment of the state information of the closed first root port in a command transmission mode.
However, closing the root port of the RC device may result in the original RC device enumeration scan process not being completed. For example, when the first root port of the RC device is closed, an access request sent by the system software of the upstream device for reading the device ID cannot reach the request destination corresponding to the first root port, and thus cannot respond to the access request, which results in that the upstream device cannot determine the specific structure of the pcie bus system.
In order to solve the above technical problems, the embodiments of the present application further provide a pcie device scanning method, which is applied to the above-mentioned system on chip, specifically, an RC device in the user system on chip, and executed after the above-mentioned pcie device control method is executed.
With continued reference to fig. 4, the method for scanning a pcie device may include all or part of the content of the method for controlling a pcie device shown in steps S101 to S106, and in particular includes the processing in steps S105 and S106, that is, the RC device, specifically, the host device bridge HPB in the RC device, receives a first instruction sent by an upstream device of the RC device, and when it is determined by the first instruction that the first root port is closed, sets the state identifier of the first root port to the closed state.
S107, the upstream device sends a first access request to a main device bridge of the RC device.
The first access request is used for requesting response information of whether the first root port of the RC equipment is connected with the pcie equipment or not.
Specifically, in the process of performing enumeration scanning of the pcie device by the upstream device, when a first root port of the RC device is scanned, a first access request is sent to the RC device, specifically, a first access request is sent to a main device bridge HPB of the RC device, and the first access request is used for requesting the RC device to feed back response information indicating whether the first root port is connected with the pcie device to the upstream device.
The specific information form and information content of the response information may be flexibly set, for example, when the first root port is connected to the pcie device, the response information may be set to an ID of the pcie device, and when the first root port is not connected to the pcie device, the response information may be set to identification information, such as FFFF, indicating that the first root port is connected to the pcie device.
S108, the primary device bridge of the RC device receives a first access request from an upstream device.
Referring to the RC architecture schematic shown in fig. 3 above, in the RC device, the main device bridge HPB is connected to the upstream device of the RC device and to the respective root ports RP of the RC device. Thus, the RC receives the first access request from the upstream device, in particular by the master bridge HPB in the RC device.
S109, the main device bridge of the RC device determines whether the first root port is closed or not by inquiring the state identification of the first root port.
Based on the processing in step S106, after receiving the first instruction sent by the upstream device of the RC device, the master device bridge HPB in the RC device sets the state identifier of the first root port of the RC device to the off state according to the first instruction.
On the basis of the above processing, after the main device bridge HPB of the RC device receives the first access request sent by the upstream device of the RC device, the status identifier of the first root port is first queried, and whether the status of the first root port is in a closed state is confirmed, so as to confirm whether the first root port is closed.
In case it is confirmed that the first root port is closed, the primary device bridge of the RC device performs step S110, transmitting the first response information to the upstream device.
The first response information indicates that the first root port is not connected with the pcie device.
Specifically, when the RC device confirms that the first root port is closed, first response information indicating that the first root port is not connected with the pcie device is generated. And sending the first response information to the upstream device, so that the upstream device determines that the pcie device is not mounted under the first root port.
The specific form and content of the first response information may be flexibly set, and in this embodiment of the present application, the first response information uses a specific identifier, such as FFFF. That is, when the RC device confirms that the first root port is closed, the identification code of FFFF is transmitted to the upstream device, so that the upstream device confirms that the first root port is not connected to the pcie device.
In case it is confirmed that the first root port is not closed, the master bridge of the RC device performs step S111 to forward the first access request to the first root port, so that the first root port responds to the first access request.
Specifically, when the RC device confirms that the first root port is not closed, the first access request is sent to the first root port, and the first root port is used for corresponding to the first access request, that is, the first root port reads the identification information of the pc ie device connected with the first access request, or reads the self identification information, and returns the read pc ie device identification information and/or the self identification information as response information to the first access request to the upstream device.
Referring to the description of the above embodiment, the RC device may receive the first access request sent by the upstream device, which may be received by the master device bridge HPB in the RC device, and query the status identifier of the first root port to determine whether the first root port is closed, or may be performed by the master device bridge HPB, so in this embodiment, when the master device bridge HPB confirms that the first root port is closed, the master device bridge HPB directly sends the first response information to the upstream device.
Similarly, if the master device bridge HPB confirms that the first root port is not closed by querying the status identifier of the first root port, the master device bridge HPB forwards the received first access request to the first root port, and the first root port responds to the first access request.
As can be seen from the foregoing description, in the pcie device scanning method provided in the embodiment of the present application, after receiving a first access request sent by an upstream device and used for requesting whether a first root port of an RC device is connected to a pcie device, the root complex RC device first confirms a state of the first root port, and when confirming that the first root port is closed, the RC device returns, to the upstream device, first response information indicating that the first root port is not connected to the pcie device, so as to implement a response to the first access request.
By the scheme, under the condition that the root port of the RC equipment is closed, the system software for executing the scanning of the pcie equipment can also receive the request response information, so that the scanning of the pcie equipment can be executed smoothly, and the system software can determine the pcie system structure.
Corresponding to the above embodiment, the embodiment of the present application further proposes a pcie device control method applied to an upstream device of an RC device, where the RC device and the upstream device connected to the RC device belong to the same system on a chip, and the RC device further includes at least one root port.
The method comprises the following steps:
and under the condition that the first root port of the RC equipment is closed, the upstream equipment connected with the RC equipment sends a first instruction to the RC equipment, wherein the first instruction carries first state information, and the first state information is used for representing that the first root port of the RC equipment is closed.
For a specific process of the method, reference may be made to the description of the corresponding content in the above embodiment. By the method, the upstream equipment realizes the identification of the closed state of the first root port, and informs the RC equipment of the information of the closed state of the first root port, so that all parties related to the first root port in the system on chip know the closed state of the first root port, and all parties can close the power consumption related to the first root port based on the closed state of the first root port, thereby being beneficial to reducing the power consumption of the system.
Meanwhile, the embodiment of the application also provides a pcie device control method applied to an RC device in a system-on-chip, in the system-on-chip, the RC device is connected with an upstream device, and the RC device comprises at least one root port, and the method comprises the following steps:
the RC equipment receives a first instruction sent by an upstream equipment connected with the RC equipment, wherein the first instruction carries first state information which is used for representing that a first root port in the RC equipment is closed.
For a specific process of the method, reference may be made to the description of the corresponding content in the above embodiment. In the method, the RC equipment receives the instruction sent by the upstream equipment and can acquire the closed state information of the first root port, so that the RC equipment can be beneficial to timely optimizing the power consumption support of the first root port and reducing the power consumption of the equipment.
In addition, the embodiment of the application also provides a pc ie device scanning method applied to an RC device of a system-on-chip, in the system-on-chip, the RC device is connected with an upstream device, and the method comprises the following steps:
the RC equipment receives a first access request from upstream equipment, wherein the first access request is used for requesting whether a first root port of the RC equipment is connected with response information of the pcie equipment or not;
the RC device sends first response information to the upstream device when confirming that the first root port is closed, wherein the first response information indicates that the first root port is not connected with the pcie device.
For a specific process of the method, reference may be made to the description of the corresponding content in the above embodiment. By executing the method, when the RC equipment confirms that the first root port is closed, the RC equipment returns first response information which indicates that the first root port is not connected with the pcie equipment to the upstream equipment, so that the response to the first access request is realized. By the scheme, under the condition that the root port of the RC equipment is closed, the system software for executing the scanning of the pcie equipment can also receive the request response information, so that the scanning of the pcie equipment can be executed smoothly, and the system software can determine the pcie system structure.
Based on the same technical concept as the method embodiment described above, the embodiment of the present application further proposes a system on a chip, as shown in fig. 5, including:
a root complex RC device 001 and an upstream device 002 connected to the RC device 001, at least one root port 003 included in the RC device 001.
The upstream device of the system on chip is configured to execute the processing procedure executed by the upstream device described in any one of the embodiments of the pcie device control method.
The RC equipment of the system on chip is used for executing the processing procedure executed by the RC equipment, which is introduced in any one of the pcie equipment control method embodiments.
In addition, another system on a chip is provided in the embodiments of the present application, and referring to fig. 6, the system on a chip includes:
a root complex RC device 011, and an upstream device 012 connected to the RC device 011;
wherein, the upstream device 012 is configured to send a first access request to the RC device 011, where the first access request is configured to request whether a response message of the pcie device is connected to a first root port of the RC device 011;
the RC device 011 is configured to receive the first access request, and when confirming that the first root port is closed, send first response information to the upstream device 012, where the first response information indicates that the first root port is not connected to the pcie device.
In some embodiments, the upstream device 012 includes a processor, and the RC device 011 includes a main device bridge for connecting the upstream device 012 of the RC device 011 and a root port of the RC device 011;
wherein the primary device bridge is configured to receive the first access request, and send the first response information to the upstream device 012 if the primary device bridge confirms that the first root port is closed.
In some embodiments, the master bridge is further configured to:
and forwarding the first access request to the first root port to enable the first root port to respond to the first access request under the condition that the first root port is not closed.
The specific working contents of each part of the system on chip and the specific structure of each part can be referred to the corresponding description in the embodiment of the method. Based on the structure of the system on chip and the functions of each part of the structure, the system on chip can close the root port of RC equipment in the pcie bus system, and can still ensure normal pcie equipment scanning enumeration realization logic in the state that the root port is closed, so that the system power consumption can be reduced under the condition that the normal pcie bus system working logic is not influenced.
The embodiment of the application also provides a computer device, which comprises the system on a chip described in any of the embodiments. Based on the application of the system on chip, the computer device can close the idle or failed RC device root port in time, so that the power consumption of the device can be reduced. And under the condition that the root port of the RC equipment is closed, the computer equipment can execute the normal pcie bus system scanning enumeration process, so that the power consumption of the equipment is reduced under the condition that the working logic of the normal pcie bus system is not influenced.
For the foregoing method embodiments, for simplicity of explanation, the methodologies are shown as a series of acts, but one of ordinary skill in the art will appreciate that the present application is not limited by the order of acts described, as some acts may, in accordance with the present application, occur in other orders or concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the apparatus class embodiments, the description is relatively simple as it is substantially similar to the method embodiments, and reference is made to the description of the method embodiments for relevant points.
The steps in the method of each embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs, and the technical features described in each embodiment can be replaced or combined.
In the embodiments provided in the present application, it should be understood that the disclosed terminal, apparatus and method may be implemented in other manners. For example, the above-described terminal embodiments are merely illustrative, and for example, the division of modules or sub-modules is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules or sub-modules illustrated as separate components may or may not be physically separate, and components that are modules or sub-modules may or may not be physical modules or sub-modules, i.e., may be located in one place, or may be distributed over multiple network modules or sub-modules. Some or all of the modules or sub-modules may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional module or sub-module in each embodiment of the present application may be integrated in one processing module, or each module or sub-module may exist alone physically, or two or more modules or sub-modules may be integrated in one module. The integrated modules or sub-modules may be implemented in hardware or in software functional modules or sub-modules.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software unit executed by a processor, or in a combination of the two. The software elements may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method of controlling a pcie device, applied to a system on a chip, the system on a chip including a root complex RC device and an upstream device connected to the RC device, the RC device including at least one root port, the method comprising:
the upstream device closing a first root port of the RC device; and under the condition that a first root port of the RC equipment is closed, the upstream equipment sends a first instruction to the RC equipment, wherein the first instruction carries first state information, and the first state information is used for representing that the first root port is closed.
2. The method of claim 1, wherein the system on a chip further comprises a first clock circuit coupled to the first root port for providing a clock signal to the first root port;
the method further comprises the steps of:
the upstream device sends a second instruction to the first clock circuit, the second instruction being used to control the first clock circuit to turn off.
3. The method of claim 1, wherein the upstream device closes a first root port of the RC device, comprising:
the upstream device sets a port state parameter of the first root port to a target parameter value, the target parameter value representing port closure.
4. A method according to any one of claims 1 to 3, characterized in that the method further comprises:
the upstream device detects whether a first root port of the RC device is idle and/or fails;
in the event that the first root port of the RC device is confirmed to be idle and/or malfunctioning, the upstream device closes the first root port of the RC device.
5. A method according to any one of claims 1 to 3, wherein the RC device further comprises a master bridge for connecting the upstream device and the at least one root port;
the upstream device sending a first instruction to the RC device, comprising:
the upstream device sends a first instruction to the master bridge.
6. A method of controlling a pcie device, applied to a system on a chip, the system on a chip including a root complex RC device and an upstream device connected to the RC device, the RC device including at least one root port, the method comprising:
the RC equipment receives a first instruction sent by the upstream equipment, wherein the first instruction carries first state information, and the first state information is information which is generated after the upstream equipment closes a first root port of the RC equipment and is used for representing that the first root port in the RC equipment is closed.
7. The method of claim 6, wherein the method further comprises:
the RC device sets a state identifier of the first root port to a closed state based on the first instruction.
8. The method according to claim 6 or 7, wherein the RC device further comprises a master bridge for connecting the upstream device and the at least one root port;
the RC equipment receives a first instruction sent by the upstream equipment, and the first instruction comprises:
the master device bridge receives a first instruction sent by the upstream device.
9. A computer device comprising a system on chip as claimed in any one of claims 1 to 8.
10. A system on a chip comprising a root complex RC device and an upstream device connected to the RC device, the RC device comprising at least one root port;
the upstream apparatus for executing the pcie apparatus control method according to any one of claims 1 to 5;
the RC device is configured to perform the pcie device control method according to any one of claims 6 to 8.
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