CN203537390U - Test system based on optical fiber channel - Google Patents
Test system based on optical fiber channel Download PDFInfo
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- CN203537390U CN203537390U CN201320565039.9U CN201320565039U CN203537390U CN 203537390 U CN203537390 U CN 203537390U CN 201320565039 U CN201320565039 U CN 201320565039U CN 203537390 U CN203537390 U CN 203537390U
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Abstract
The utility model discloses a test system based on an optical fiber channel in the technical field of optical fiber communication transmission. The test system comprises a first reference clock chip, a second reference clock chip, a central processor, an optical transceiver, an FPGA (Field Programmable Gate Array), an EPROM memory and a JTAG debugger. The first and second reference clock chips are connected with the central processor. The central processor, the EPROM memory, the JTAG debugger and the optical transceiver are all connected with the FPGA (Field Programmable Gate Array). The JTAG debugger is connected with the EPROM memory. The test system can test each module of the FPGA (Field Programmable Gate Array), can direction write a configuration program into the EPROM memory, and is short in project period, and convenient and flexible in development.
Description
Technical field
The utility model relates to fiber-optic communications traffic technical field, is a kind of optical fiber communication measurement, control or signal transmission system specifically.
Background technology
Optical fiber communication, is to utilize fiber optic transmission signal, a kind of communication mode transmitting to realize information.A pair of single mode optical fibre can be opened 35000 phones simultaneously, compare with telecommunication there is transmission frequency bandwidth, loss is low, loss evenly and is not subject to the impact of temperature, antijamming capability is strong, fidelity is high, signal security degree is high, reliable operation degree high, the host-host protocol of the high speed serialization ability that it adopts, has high reliability, high bandwidth, feature that real-time is high.Along with the development of the all-wave window optical fiber of the progress of optical fiber technology, particularly anhydrous peak, within the scope of the wide optical frequency from 1280nm to 1625nm, can realize low-loss, low dispersion transmission, transmission capacity is hundred times, several thousand times of even growths of up to ten thousand times.That simultaneously optical fiber communication adopts is point-to-point, star, chain, loop network topological structure, and intermediate equipment is few, does not need to carry out complicated protocol conversion.Just so, optical fiber telecommunications system becomes major flow communication system gradually.
Optical fiber telecommunications system not only comprises basic hardware system; also comprise monitoring management system; its major function is to carry out the monitoring of performance and operating state to forming the various connection devices of optical fiber telecommunications system; can auto-alarming while breaking down and processed, protection exchanging system is carried out automatically and controlled.It can also realize real-time demonstration and the storage to data simultaneously, and the data of storage are carried out to instant analysis processing.Monitoring management system not only can receive the optical-fibre channel data that optical transmitter and receiver sends, can also be directly and another Optical Network Terminal interconnect.
The operation of optical fiber telecommunications system and monitoring function are mainly to realize by optical-fibre channel data interface card.The systemic-function of optical-fibre channel data interface card and circuit logic more complicated, need more configurable logic block.This configurability is mainly realized by field programmable gate array (FPGA), design engineer utilizes the resource on FPGA many systemic-functions to be configured on the logical circuit of device, circuit quantity on reduction system circuit board, design engineer can also utilize the configurable characteristic of FPGA to change logic to increase or remove function, fix-up logic leak or improve performance.
The programmable gate array (FPGA) that optical-fibre channel data interface card adopts comprises bus control module, the optical-fibre channel data storage card operating state register group that optical-fibre channel data processing module, data buffer storage and computer are connected.The bus control module that wherein design engineer can be connected with computer optical-fibre channel data processing module is configured, by configuration adjustment, realize logic, make modules in best operating state, increase harmony and the stability of each module work of FPGA, and then improve the overall performance of FPGA.Also, by configuration optical-fibre channel data interface card, adapt to the light channel network at place, eliminate the problem of finding in practical application, thereby farthest meet operation and the monitoring requirements of fiber optic network.
The configurator of FPGA is arranged in EPROM, and when optical-fibre channel data interface card powers up, fpga chip reads in data in EPROM in sheet and programmes in RAM, and after having configured, FPGA enters operating state.With a slice FPGA, different programming datas, can produce different circuit functions, and FPGA is used very flexible.
During FPGA design, first by jtag test instrument, FPGA internal node is tested, concrete mode is that a plurality of devices that will test are cascaded by jtag interface, forms a JTAG chain, can realize each device is tested respectively.After having tested, then by JTAG, all parts on FPGA and FPGA integral body are programmed, after programming finishes, programming is write to EPROM.
Conventionally first with JTAG, EPROM is carried out to pre-programmed at present, then EPROM is installed to FPGA above, then start FPGA, FPGA and Qi Ge parts are tested, according to test result, adjust configuration programming, write EPROM, then test, until test passes.This method, need to repeatedly take off, install EPROM, this process easily causes EPROM to occur hardware damage, find misprogrammed, in the time of need to adjusting, can only, after all having tested, could complete by writing new configurator, this method is unfavorable for finding the Optimum Points of configurator, and construction period is longer simultaneously.
Utility model content
In order to overcome prior art when FPGA being tested by JTAG and writing configurator, adopt JTAG to carry out pre-programmed to EPROM, be installed to again on FPGA, then by JTAG, FPGA system or each parts are carried out to integrated testability, this scheme is long at construction period, configurator be cannot adjust in time and the optimization work point of FPGA all parts and relevant configurator found, the process of whole test is loaded down with trivial details, the technological deficiency that test period is long, the utility model provides a kind of test macro based on optical-fibre channel.
For solving above-mentioned technical problem, the utility model by the following technical solutions:
Test macro based on optical-fibre channel, comprise the first reference clock chip, the second reference clock chip, central processing unit, optical transceiver, FPGA field programmable gate array, FLASH memory, JTAG debugger, the first reference clock chip, the second reference clock chip, FLASH memory, JTAG debugger are all connected with central processing unit, JTAG debugger connects FLASH memory, and central processing unit, optical transceiver are all connected with FPGA field programmable gate array.
When the utility model comes into operation, the first step, checks, commissioning device: check between each module of test macro based on optical-fibre channel, whether optical transceiver be connected normally with fiber optic network hardware, if there is extremely, corrected.Second step, adds electric test equipment: start power supply, confirm that whether test macro and the connection device operating state based on optical-fibre channel be normal, after equipment is normal, just come into operation, the 3rd step, carry out debugging test assignment, first with JTAG debugger, test the modules of FPGA field programmable gate array, modules and FPGA field programmable gate array are programmed, the configurator writing is write to FLASH memory, allow FPGA field programmable gate array read in the configurator of FLASH memory, operation FPGA field programmable gate array, be in operation PGA field programmable gate array and each functional module thereof are tested, by test result, adjust or rewrite configurator, start again test, until the configuration of FPGA field programmable gate array meets monitoring and the operation task of connected fiber optic network completely.
The operation principle of common jtag test programming: by each logical device apportion, adopt eprom memory to carry out stored configuration program, adopt jtag test device to carry out scanning logic, a plurality of logical devices that it first will be tested are cascaded by jtag interface, form a JTAG chain, each chain has the test access port of oneself.First data are sent to jtag test device, activate the scanning logic of jtag test device, then JTAG chain is scanned, read the logical message of each logical device, again jtag test device is connected with FPGA field programmable gate array, jtag test device sends scan test signal to FPGA field programmable gate array, and jtag test device is read the configured in one piece logic of FPGA field programmable gate array.After having tested, then by jtag test device, all parts on FPGA field programmable gate array and FPGA field programmable gate array integral body are programmed, after programming finishes, programming is write to eprom memory.
Operation principle of the present utility model: adopt the central processing unit of integrated jtag test interface to set up test link, adopt FLASH memory to carry out stored configuration program, adopt FPGA field programmable gate array to inherit each functional module, adopt jtag test device to test each functional module of FPGA field programmable gate array and FPGA field programmable gate array oneself.FPGA field programmable gate array, FLASH memory, jtag test device are all connected with central processing unit, and FLASH memory connects jtag test device.During work, the jtag test interface of jtag test device by central processing unit use central processing unit and FPGA field programmable gate array with and the test link set up of each module carry out the test of integral body or individual module.After having tested, jtag test device is programmed to all parts on FPGA field programmable gate array and FPGA field programmable gate array integral body by central processing unit, after programming finishes, programming is write to FLASH memory.
With prior art, FPGA field programmable gate array is being carried out to test program, adopt function logic module and FPGA field programmable gate array separately to carry out, carry out again each module and the programming of FPGA field programmable gate array, after programming finishes, the technical scheme that programming is write to eprom memory is compared, logic testing link and programming link that the utility model adopts central processing unit to set up, use jtag test device directly FPGA field programmable gate array modules and integral body are tested and programmed, test link is stable, efficiently, test result is comprehensive, the testing engineering cycle is short.Good test result, has guaranteed quality and the operational efficiency of the configurator write below.After the configurator of FPG field programmable gate array and modules thereof has been write, FLASH memory writes direct.Simultaneously, next time is while starting FPGA field programmable gate array, directly read in the configurator of FLASH memory, realize the functional configuration of FPGA field programmable gate array, JTAG debugger can be debugged on the basis of new test program, until configurator meets the requirement of the fiber optic network of connection.FLASH memory had than the better erasable performance of eprom memory, larger memory capacity, safer, reliable, stable and longer useful life.
For further optimization, improve the adaptive capacity of FPGA field programmable gate array to fiber optic network, as preferentially, FPGA field programmable gate array comprises FC data processor, data buffer storage, PCI-Express processor, operating state register group, FC data processor, data buffer storage and PCI-Express processor are all connected with operating state register group, FC data processor connection data buffer memory, data buffer storage connects PCI-Express processor.
For monitoring and move the FPGA field programmable gate array of fiber optic network, light signal and the signal of telecommunication need to be changed mutually, realize the seamless link of fiber optic network and telecommunication network, this work completes by FC data processor conventionally; It also needs to carry out with computer the administration module of the PCI-Express exchanges data link of high-speed data clearing house need, i.e. PCI-Express processor; The message transmission rate difference of FC data processor and PCI-Express processor is very large, so need to realize message transmission rate adjustment, this realizes by data buffer storage; It also needs one for storing work order, hardware resource, and can manage it the memory of arithmetic and logic operation, be operating state register group.
It is more than the further improvement to the system structure optimization ability of the test macro based on optical-fibre channel.Adopt the FPGA field programmable gate array of above structure can adapt to monitoring and the operation of high speed fibre network completely, and can realize and computer carries out high-speed communication.
Those skilled in the art can freely select according to real work border and design requirement the parameter of assembly.
For further optimization, the bidirectional data transfers ability of the transfer of data of the test macro of raising based on optical-fibre channel, as preferentially, data buffer storage comprises reception buffer memory and sends buffer memory, FC data processor connects reception buffer memory, receive buffer memory and connect PCI-Express processor, PCI-Express processor connects transmission buffer memory, sends buffer memory and connects FC data processor.
It is more than the further improvement to the data transmission capabilities of the test macro based on optical-fibre channel.Bidirectional data transfers is exactly between two data cells, adopt to send line and acceptance line method independently separately, makes data on both direction, carry out transfer operation simultaneously.Data buffer storage is divided into receiving buffer memory and sending buffer memory and is configured in respectively transmission line and acceptance line, adopt this fifo queue of FIFO to realize DMA buffer memory parts, thereby can greatly improve forward efficiency, reduce Forwarding Delay, realize pipeline system and forwarded FC frame, more can solve the FC data processor data rate problem different from PCI Express data rate.
Those skilled in the art can freely select according to the actual requirements the reception buffer memory of data buffer storage and send the ratio of buffer memory.
For further optimization, improve FPGA field programmable gate array data-handling capacity, as preferentially, the test macro based on optical-fibre channel, also comprises data cache device SRAM, described data cache device SRAM connects FPGA field programmable gate array.
It is more than the further improvement to the data reading capability of the test macro based on optical-fibre channel.Data cache device SRAM has the function of static storage, does not need refresh circuit just can preserve the data of its storage inside, therefore has higher performance, and speed is fast, and read-write sequence is simple, working stability.Adopt data cache device SRAM for FPGA provides data cache, be conducive to improve the ability of the test macro deal with data based on optical-fibre channel, to adapt to more high speed, more jumbo transfer of data load.
Those skilled in the art can freely select the model of data cache device SRAM according to the actual requirements.
For further optimization, improve test macro based on optical-fibre channel and the communication capacity of computer, optical-fibre channel data processing module also comprises PCI-EXPRESS interface, PCI-EXPRESS interface connects FPGA field programmable gate array.
It is more than the further improvement to the test macro based on optical-fibre channel and computer data exchange capacity.PCI Express bus is point-to-point high-speed serial bus, and each PCI Express equipment has oneself independently data connection, has guaranteed the monopoly of passage, avoids the interference of other equipment.PCI Express bus is supported transmitted in both directions pattern, PCI Express bus every to data transfer bandwidth up to 4GB/s, bidirectional data transfers bandwidth has more than 8GB/s.
Those skilled in the art can freely select the model of PCI-EXPRESS interface according to the actual requirements.
For further optimization, the peripheral applications extended capability of the test macro of raising based on optical-fibre channel, as preferably, test macro based on optical-fibre channel, also comprise interface chip MAX1482, RS485 interface, RS422 interface, RS485 interface, RS422 interface are all connected with interface chip MAX1482, and interface chip MAX1482 connects FPGA field programmable gate array.
It is more than the further improvement to the application extension ability of the test macro based on optical-fibre channel.Computer and and smart machine be generally to communicate with data processing equipment by RS485 interface and RS422 interface, realize demonstration, the storage of data, thus monitoring and operation function.MAX1482 interface chip is lower powered full duplex interface chip, and it can realize communicating with RS485 interface, RS422 interface of low EMI and low reflection, and RS485 interface and RS422 interface are all full duplex communication interface.The system of this employing interface chip has abundant peripheral control interface and communication interface.
Those skilled in the art are the model of free option interface chip according to the actual requirements.
For further optimization, improve the circuit logic allocative abilities of the test macro based on optical-fibre channel, realize better systemic-function and circuit logic, as preferentially, FPGA field programmable gate array is Xilinx XC5VLX110T.
FPGA field programmable gate array, performance and the function of owned input-output unit able to programme, configurable logic block, digital dock administration module, embedded block RAM, interconnection resource, the embedded functional unit of bottom, embedded special-purpose each module of stone directly depend on its acp chip.。
It is more than the further improvement to the comprehensive configurable ability of test macro based on optical-fibre channel.Xilinx is the technology enterprise in advance of FPGA field programmable gate array industry, Virtex-5 family chip is first 65nm FPGA product of the whole world that Xilinx company releases, use 1.0V tri-gate oxidation layer process, the ExpressFabric framework of exploitation of innovation is also realized ultimate Integrated.XC5VLX110T belongs to the LXT platform that the high performance logic of low-power consumption serial i/O is optimized.
For further optimization, improve test macro based on the optical-fibre channel managerial ability to each module of system, as preferably, central processing unit is Cortex-M3 core ARM microprocessor LPC1769.
It is more than the further improvement to the system management ability of the test macro based on optical-fibre channel.Central processing unit, for controlling operating state and the buffer queue scheduling of fpga chip, manages FLASH configuring chip.Cortex-M3 core ARM microprocessor LPC1769, is that it has JTAG interface towards the chip of the low-power consumption in the embedded market of industry, supports JTAG debugging, and special instruction tracing unit is provided.
Those skilled in the art can freely select the model of central processing unit according to the actual requirements.
For further optimization, improve the light signal conversion of the test macro based on optical-fibre channel and transmitting-receiving ability as preferentially, the model of optical transceiver is FTRJ-8519-1-2.5.
It is more than the further improvement to the data-signal conversion of the test macro based on optical-fibre channel and transmitting-receiving ability.Adopt the FTRJ-8519-1-2.5 of Finisar company optical transceiver, it adopts 850nm laser, and 2.125Gbps transmission rate is provided, and has good shake and EMI characteristic.
Those skilled in the art are the model of free selective light transceiver according to the actual requirements.
Compared with prior art, the beneficial effects of the utility model are:
1. with prior art, FPGA field programmable gate array is being carried out to test program, adopt function logic module and FPGA field programmable gate array separately to carry out, carry out again each module and the programming of FPGA field programmable gate array, the technical scheme that programming is write to eprom memory is compared, logic testing link and programming link that the utility model adopts central processing unit to set up, use jtag test device directly FPGA field programmable gate array modules and integral body are tested and programmed, test link is stable, efficiently, test result is comprehensive, the testing engineering cycle is short.After the configurator of FPG field programmable gate array and modules thereof has been write, FLASH memory writes direct.Simultaneously, next time is while starting FPGA field programmable gate array, directly read in the configurator of FLASH memory, realize the functional configuration of FPGA field programmable gate array, JTAG debugger can be debugged on the basis of new test program, until configurator meets the requirement of the fiber optic network of connection.FLASH memory had than the better erasable performance of eprom memory, larger capacity, safer, reliable and longer life-span.
2. the utility model adopts and comprises FC data processor, data buffer storage, PCI-Express processor, operating state register group, the FPGA field programmable gate array of FC data processor, it can realize the transmission demand configuration FPGA field programmable gate array according to fiber optic network, farthest meet monitoring and the operation business of fiber optic network, its construction period is short, flexible configuration, customization cost is low, adopt Gbps level high-speed serial communication pattern PCI-Express interface can easily realize between computer and fiber data card and carry out large capacity, the exchanges data of high load capacity.
3. the utility model adopts interface chip MAX1482, RS485 interface, RS422 interface, can realize the access of more smart machine, realizes demonstration, the storage of data, thereby realizes the monitoring of fiber optic network and operation function.
The utility model has solved FPGA field programmable gate array has been carried out to test program, adopt function logic module and FPGA field programmable gate array separately to carry out test program, programming is write to eprom memory, formality is loaded down with trivial details, construction period is long, the technical problem that effect is undesirable, test link of the present utility model is stable, efficiently, test result is comprehensive, the testing engineering cycle is short, it can also be realized while starting FPGA field programmable gate array next time, directly read in the configurator of FLASH memory, realize the functional configuration of FPGA field programmable gate array, JTAG debugger can be debugged on the basis of new test program, until configurator meets the requirement of the fiber optic network of connection.It has good industrial value.。
Accompanying drawing explanation
In order to be illustrated more clearly in embodiment of the present utility model, will be briefly described describing the required accompanying drawing of using in the utility model embodiment below.Apparent, the accompanying drawing in the following describes is only some embodiment that record in the utility model, for a person skilled in the art, in the situation that not paying creative work, can also, according to accompanying drawing below, obtain other accompanying drawing.
Fig. 1 is structural representation of the present utility model.
Embodiment
In order to make those skilled in the art understand better the utility model, below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out to clear, complete description.Apparent, embodiment described below is only the part in the utility model embodiment, rather than all.The embodiment recording based on the utility model, other all embodiment that those skilled in the art obtain in the situation that not paying creative work, all in the scope of the utility model protection.
Embodiment mono-:
As shown in Figure 1, the utility model, comprise the first reference clock chip, the second reference clock chip, also comprise central processing unit, optical transceiver, FPGA field programmable gate array, FLASH memory, JTAG debugger, the first reference clock chip, the second reference clock chip, FLASH memory, JTAG debugger are all connected with central processing unit, JTAG debugger connects FLASH memory, and central processing unit, optical transceiver are all connected with FPGA field programmable gate array.
Those skilled in the art can freely select according to the requirement of practice of construction environment and workpiece the parameter of assembly.
Embodiment bis-:
In order to improve the system structure optimization ability of the test macro based on optical-fibre channel, the present embodiment improves further on the basis of embodiment mono-, the FPGA field programmable gate array of the present embodiment comprises FC data processor, data buffer storage, PCI-Express processor, operating state register group, FC data processor, data buffer storage and PCI-Express processor are all connected with operating state register group, FC data processor connection data buffer memory, data buffer storage connects PCI-Express processor.
Those skilled in the art can freely select according to real work border and design requirement the parameter of assembly.
Embodiment tri-:
In order to improve the data transmission capabilities of the test macro based on optical-fibre channel, the present embodiment improves further on the basis of embodiment bis-, the data buffer storage of the present embodiment comprises reception buffer memory and sends buffer memory, FC data processor connects reception buffer memory, receive buffer memory and connect PCI-Express processor, PCI-Express processor connects transmission buffer memory, sends buffer memory and connects FC data processor.
Those skilled in the art can freely select according to the actual requirements the reception buffer memory of data buffer storage and send the ratio of buffer memory.
Embodiment tetra-:
In order to improve the data reading capability of the test macro based on optical-fibre channel, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～tri-, the test macro based on optical-fibre channel of the present embodiment, also comprise data cache device SRAM, data cache device SRAM connects FPGA field programmable gate array.
Those skilled in the art can freely select the model of data cache device SRAM according to the actual requirements.
Embodiment five:
In order to improve test macro and the computer data exchange capacity based on optical-fibre channel, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～tetra-, 1 test macro based on optical-fibre channel of the present embodiment, also comprise PCI-Express interface, PCI-Express interface connects PCI-Express processor.
Those skilled in the art can freely select the type of PCI-Express interface according to the actual requirements.
Embodiment six:
In order to improve the application extension ability of the test macro based on optical-fibre channel, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～five, the test macro based on optical-fibre channel of the present embodiment, also comprise interface chip MAX1482, RS485 interface, RS422 interface, RS485 interface, RS422 interface are all connected with interface chip MAX1482, and interface chip MAX1482 connects FPGA field programmable gate array.
Those skilled in the art are the model of free option interface chip according to the actual requirements.
Embodiment seven:
In order to improve the comprehensive configurable ability of test macro based on optical-fibre channel, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～six, and the FPGA field programmable gate array of the present embodiment is Xilinx XC5VLX110T.
Those skilled in the art can freely select the model of FPGA field programmable gate array according to the actual requirements.
Embodiment eight:
In order to improve the system management ability of the test macro based on optical-fibre channel, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～seven, and the central processing unit of the present embodiment is Cortex-M3 core ARM microprocessor LPC1769.
Those skilled in the art can freely select the model of central processing unit according to the actual requirements.
Embodiment nine:
In order to improve data-signal conversion and the transmitting-receiving ability of the test macro based on optical-fibre channel, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～eight, and the model of the optical transceiver of the present embodiment is FTRJ-8519-1-2.5.
Those skilled in the art are the model of free selective light transceiver according to the actual requirements.
Just can realize this utility model as mentioned above.
Claims (9)
1. the test macro based on optical-fibre channel, comprise the first reference clock chip, the second reference clock chip, it is characterized in that: also comprise central processing unit, optical transceiver, FPGA field programmable gate array, FLASH memory, JTAG debugger, described the first reference clock chip, the second reference clock chip, FLASH memory, JTAG debugger are all connected with central processing unit, described JTAG debugger connects FLASH memory, and described central processing unit, optical transceiver are all connected with FPGA field programmable gate array.
2. the test macro based on optical-fibre channel according to claim 1, it is characterized in that: described FPGA field programmable gate array comprises FC data processor, data buffer storage, PCI-Express processor, operating state register group, described FC data processor, data buffer storage and PCI-Express processor are all connected with operating state register group, described FC data processor connection data buffer memory, described data buffer storage connects PCI-Express processor.
3. the test macro based on optical-fibre channel according to claim 2, it is characterized in that: described data buffer storage comprises reception buffer memory and sends buffer memory, described FC data processor connects reception buffer memory, described reception buffer memory connects PCI-Express processor, described PCI-Express processor connects transmission buffer memory, and described transmission buffer memory connects FC data processor.
4. the test macro based on optical-fibre channel according to claim 1, is characterized in that: also comprise data cache device SRAM, described data cache device SRAM connects FPGA field programmable gate array.
5. the test macro based on optical-fibre channel according to claim 1, is characterized in that: also comprise PCI-Express interface, described PCI-Express interface connects PCI-Express processor.
6. the test macro based on optical-fibre channel according to claim 1, it is characterized in that: also comprise interface chip MAX1482, RS485 interface, RS422 interface, described RS485 interface, RS422 interface are all connected with interface chip MAX1482, and described interface chip MAX1482 connects FPGA field programmable gate array.
7. the test macro based on optical-fibre channel according to claim 1, is characterized in that: described FPGA field programmable gate array is Xilinx XC5VLX110T.
8. the test macro based on optical-fibre channel according to claim 1, is characterized in that: described central processing unit is Cortex-M3 core ARM microprocessor LPC1769.
9. the test macro based on optical-fibre channel according to claim 1, is characterized in that: the model of described optical transceiver is FTRJ-8519-1-2.5.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103472388A (en) * | 2013-09-12 | 2013-12-25 | 成都成电光信科技有限责任公司 | Testing system of optical fiber network |
| CN105515673A (en) * | 2015-11-27 | 2016-04-20 | 中国航空工业集团公司沈阳飞机设计研究所 | Optical fiber channel node card |
| CN106841973A (en) * | 2015-12-04 | 2017-06-13 | 深圳市盛德金科技有限公司 | Logic testing device and method |
| CN109460374A (en) * | 2017-09-06 | 2019-03-12 | 上海赛治信息技术有限公司 | A kind of PiP encapsulation chip based on programmable logic |
| CN112306773A (en) * | 2020-11-05 | 2021-02-02 | 中国航空工业集团公司西安航空计算技术研究所 | Fault detection platform of FC node machine with standard serial host interface |
| CN112486877A (en) * | 2020-11-05 | 2021-03-12 | 中国航空工业集团公司西安航空计算技术研究所 | Outfield guarantee and test platform of universal FC conversion interface module |
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2013
- 2013-09-12 CN CN201320565039.9U patent/CN203537390U/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103472388A (en) * | 2013-09-12 | 2013-12-25 | 成都成电光信科技有限责任公司 | Testing system of optical fiber network |
| CN105515673A (en) * | 2015-11-27 | 2016-04-20 | 中国航空工业集团公司沈阳飞机设计研究所 | Optical fiber channel node card |
| CN105515673B (en) * | 2015-11-27 | 2018-11-13 | 中国航空工业集团公司沈阳飞机设计研究所 | A kind of optical-fibre channel node card |
| CN106841973A (en) * | 2015-12-04 | 2017-06-13 | 深圳市盛德金科技有限公司 | Logic testing device and method |
| CN106841973B (en) * | 2015-12-04 | 2023-12-15 | 深圳市盛德金科技有限公司 | Logic testing device and method |
| CN109460374A (en) * | 2017-09-06 | 2019-03-12 | 上海赛治信息技术有限公司 | A kind of PiP encapsulation chip based on programmable logic |
| CN112306773A (en) * | 2020-11-05 | 2021-02-02 | 中国航空工业集团公司西安航空计算技术研究所 | Fault detection platform of FC node machine with standard serial host interface |
| CN112486877A (en) * | 2020-11-05 | 2021-03-12 | 中国航空工业集团公司西安航空计算技术研究所 | Outfield guarantee and test platform of universal FC conversion interface module |
| CN112486877B (en) * | 2020-11-05 | 2024-05-28 | 中国航空工业集团公司西安航空计算技术研究所 | Outfield guarantee and test platform of generalized FC conversion interface module |
| CN112306773B (en) * | 2020-11-05 | 2024-06-18 | 中国航空工业集团公司西安航空计算技术研究所 | Fault detection platform of FC node machine with standard serial host interface |
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Address after: High tech Zone Tianchen road Chengdu City, Sichuan province 610000 No. 88 Patentee after: CHENGDU UESTC OPTICAL COMMUNICATION CO.,LTD. Address before: High tech Zone Tianchen road Chengdu City, Sichuan province 610000 No. 88 Patentee before: CHENGDU CHENGDIAN GUANGXIN TECHNOLOGY Co.,Ltd. |
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