CN103472388A - Testing system of optical fiber network - Google Patents
Testing system of optical fiber network Download PDFInfo
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- CN103472388A CN103472388A CN2013104139555A CN201310413955A CN103472388A CN 103472388 A CN103472388 A CN 103472388A CN 2013104139555 A CN2013104139555 A CN 2013104139555A CN 201310413955 A CN201310413955 A CN 201310413955A CN 103472388 A CN103472388 A CN 103472388A
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Abstract
The invention discloses a testing system of an optical fiber network, and belongs to the technical field of optical fiber communication transmission. The testing system comprises a first reference clock chip and a second reference clock chip, and further comprises a central processing unit, an optical transceiver, an FPGA, an EPROM and a JTAG debugger, wherein the first reference clock chip and the second reference clock chip are both connected with the central processing unit, the central processing unit, the EPROM, the JTAG debugger and the optical transceiver are all connected with the FPGA, and the JTAG debugger is connected with the EPROM. By means of the testing system, each module of the FPGA can be tested, configuration programs can be directly written in the EPROM, the engineering period is short, and the development can be conveniently and flexibly realized.
Description
Technical field
The present invention relates to the fiber-optic communications traffic technical field, is a kind of optical fiber communication measurement, control or signal transmission system specifically.
Background technology
Optical fiber communication, be to utilize the fiber optic transmission signal, with a kind of communication mode of realizing that information is transmitted.A pair of single mode optical fibre can be opened 35000 phones simultaneously, with telecommunication, compare there is transmission frequency bandwidth, loss is low, loss evenly and not is subject to the impact of temperature, antijamming capability is strong, fidelity is high, the signal security degree is high, reliable operation degree high, the host-host protocol of the high speed serialization ability that it adopts, have high reliability, high bandwidth, characteristics that real-time is high.Along with the development of the all-wave window optical fiber of the progress of optical fiber technology, particularly anhydrous peak, in the wide optical frequency scope from 1280nm to 1625nm, can realize low-loss, low dispersion transmission, transmission capacity is hundred times, several thousand times of even growths of up to ten thousand times.That simultaneously optical fiber communication adopts is point-to-point, star, chain, loop network topological structure, and intermediate equipment is few, does not need to carry out complicated protocol conversion.Just so, optical fiber telecommunications system becomes the major flow communication system gradually.
Optical fiber telecommunications system not only comprises basic hardware system; also comprise monitoring management system; its major function is that the various connection devices to forming optical fiber telecommunications system carry out the monitoring of performance and duty; can auto-alarming while breaking down and processed, the protection exchanging system is carried out automatically and controlled.It can also realize real-time demonstration and the storage to data simultaneously, and the data of storage are carried out to the instant analysis processing.Monitoring management system not only can receive the optical-fibre channel data that optical transmitter and receiver sends, can also be directly and another Optical Network Terminal interconnected.
The operation of optical fiber telecommunications system and monitoring function are mainly to realize by the optical-fibre channel data interface card.The systemic-function of optical-fibre channel data interface card and circuit logic more complicated, need more configurable logic block.This configurability is mainly realized by field programmable gate array (FPGA), the design engineer utilizes the resource on FPGA many systemic-functions to be configured on the logical circuit of device, circuit quantity on the reduction system circuit board, the design engineer can also utilize the configurable characteristic of FPGA to change logic to increase or remove function, fix-up logic leak or improve performance.
The programmable gate array (FPGA) that the optical-fibre channel data interface card adopts comprises bus control module, the optical-fibre channel data storage card duty register group that optical-fibre channel data processing module, data buffer storage and computing machine are connected.The bus control module that wherein design engineer can be connected with computing machine the optical-fibre channel data processing module is configured, realize logic by configuration adjustment, make modules in best duty, increase harmony and the stability of each module work of FPGA, and then improve the overall performance of FPGA.Also, by configuration optical-fibre channel data interface card, adapt to the light channel network at place, eliminate the problem of finding in practical application, thereby farthest meet operation and the monitoring requirements of fiber optic network.
The configurator of FPGA is arranged in EPROM, and when the optical-fibre channel data interface card powers up, fpga chip reads in data in EPROM in sheet in the RAM that programmes, and after having configured, FPGA enters duty.With a slice FPGA, different programming datas, can produce different circuit functions, and FPGA is used very flexible.
During the FPGA design, first by the jtag test instrument, the FPGA internal node is tested, concrete mode is that a plurality of devices that will test are cascaded by jtag interface, forms a JTAG chain, can realize each device is tested respectively.After having tested, then by JTAG, all parts on FPGA and FPGA integral body are programmed, programming writes EPROM by programming after finishing.
Usually first with JTAG, EPROM is carried out to pre-programmed at present, then EPROM is installed to FPGA above, then start FPGA, FPGA and Qi Ge parts are tested, according to test result, adjust the configuration programming, write EPROM, then tested, until test passes.This method, need to repeatedly take off, install EPROM, this process easily causes EPROM hardware damage to occur, find misprogrammed, while needing to adjust, can only, after all having tested, could complete by writing new configurator, this method is unfavorable for finding the Optimum Points of configurator, and construction period is longer simultaneously.
Summary of the invention
In order to overcome prior art when by JTAG, FPGA being tested and writing configurator, adopt JTAG to carry out pre-programmed to EPROM, be installed to again on FPGA, then by JTAG, FPGA system or each parts are carried out to integrated testability, this scheme is long at construction period, configurator be can't adjust in time and the optimization work point of FPGA all parts and relevant configurator found, the process of whole test is loaded down with trivial details, the technological deficiency that test period is long, the invention provides a kind of test macro of fiber optic network.
For solving above-mentioned technical matters, the present invention by the following technical solutions:
The test macro of fiber optic network, comprise the first reference clock chip, the second reference clock chip, central processing unit, optical transceiver, FPGA field programmable gate array, FLASH storer, JTAG debugger, the first reference clock chip, the second reference clock chip, FLASH storer, JTAG debugger all are connected with central processing unit, the JTAG debugger connects the FLASH storer, and central processing unit, optical transceiver all are connected with the FPGA field programmable gate array.
When the present invention is come into operation, the first step checks, commissioning device: check between each module of test macro of fiber optic network, whether optical transceiver be connected normally with fiber optic network hardware, if there is extremely, corrected.Second step adds electric test equipment: start power supply, confirm that whether test macro and the connection device duty of fiber optic network be normal, just come into operation after equipment is normal, the 3rd step, carry out the debugging test assignment, first with the JTAG debugger, test the modules of FPGA field programmable gate array, modules and FPGA field programmable gate array are programmed, the configurator write is write to the FLASH storer, allow the FPGA field programmable gate array read in the configurator of FLASH storer, operation FPGA field programmable gate array, be in operation PGA field programmable gate array and each functional module thereof are tested, by test result, adjust or rewrite configurator, start again test, until the configuration of FPGA field programmable gate array meets monitoring and the operation task of connected fiber optic network fully.
The principle of work of common jtag test programming: by each logical device apportion, adopt eprom memory to carry out the stored configuration program, adopt the jtag test device to carry out scanning logic, a plurality of logical devices that it first will be tested are cascaded by jtag interface, form a JTAG chain, each chain has the test access port of oneself.At first data are sent to the jtag test device, activate the scanning logic of jtag test device, then the JTAG chain is scanned, read the logical message of each logical device, again the jtag test device is connected with the FPGA field programmable gate array, the jtag test device sends scan test signal to the FPGA field programmable gate array, and the jtag test device is read the configured in one piece logic of FPGA field programmable gate array.After having tested, then by the jtag test device, all parts on the FPGA field programmable gate array and FPGA field programmable gate array integral body are programmed, programming writes eprom memory by programming after finishing.
Principle of work of the present invention: adopt the central processing unit of integrated jtag test interface to set up test link, adopt the FLASH storer to carry out the stored configuration program, adopt the FPGA field programmable gate array to inherit each functional module, adopt the jtag test device to test each functional module of FPGA field programmable gate array and FPGA field programmable gate array oneself.FPGA field programmable gate array, FLASH storer, jtag test device all are connected with central processing unit, and the FLASH storer connects the jtag test device.During work, the jtag test interface of jtag test device by central processing unit use central processing unit and FPGA field programmable gate array with and the test link set up of each module carry out the test of integral body or individual module.After having tested, the jtag test device is programmed to all parts on the FPGA field programmable gate array and FPGA field programmable gate array integral body by central processing unit, and programming writes the FLASH storer by programming after finishing.
With prior art, the FPGA field programmable gate array is being carried out to test program, adopt function logic module and FPGA field programmable gate array separately to carry out, carry out again each module and the programming of FPGA field programmable gate array, after programming finishes, the technical scheme that programming is write to eprom memory is compared, logic testing link and programming link that the present invention adopts central processing unit to set up, use the jtag test device directly FPGA field programmable gate array modules and integral body are tested and programmed, test link is stable, efficiently, test result is comprehensive, the testing engineering cycle is short.Good test result, guaranteed quality and the operational efficiency of the configurator write later.After the configurator of FPG field programmable gate array and modules thereof has been write, the FLASH storer writes direct.Simultaneously, next time is while starting the FPGA field programmable gate array, directly read in the configurator of FLASH storer, realize the functional configuration of FPGA field programmable gate array, the JTAG debugger can be debugged on the basis of new test procedure, until configurator meets the requirement of the fiber optic network of connection.The FLASH storer had than the better erasable performance of eprom memory, larger memory capacity, safer, reliable, stable and longer serviceable life.
For further optimization, improve the adaptive faculty of FPGA field programmable gate array to fiber optic network, as preferentially, the FPGA field programmable gate array comprises FC data processor, data buffer storage, PCI-Express processor, duty register group, FC data processor, data buffer storage and PCI-Express processor all are connected with duty register group, FC data processor connection data buffer memory, data buffer storage connects the PCI-Express processor.
For the FPGA field programmable gate array of monitoring and operation fiber optic network, light signal and electric signal need to be changed mutually, realize the seamless link of fiber optic network and telecommunication network, this work completes by the FC data processor usually; It also needs to carry out with computing machine the administration module of the PCI-Express exchanges data link of high-speed data clearing house need, i.e. PCI-Express processor; The message transmission rate difference of FC data processor and PCI-Express processor is very large, so need to realize the message transmission rate adjustment, this realizes by data buffer storage; It also needs one for storing work order, hardware resource, and can manage it the storer of arithmetic and logic operation, is duty register group.
It is more than the further improvement to the system structure optimization ability of the test macro of fiber optic network.Adopt the FPGA field programmable gate array of above structure can adapt to monitoring and the operation of high speed fibre network fully, and can realize and computing machine carries out high-speed communication.
Those skilled in the art can freely select according to real work border and design requirement the parameter of assembly.
For further optimization, the bidirectional data transfers ability of the data transmission of the test macro of raising fiber optic network, as preferentially, data buffer storage comprises the reception buffer memory and sends buffer memory, the PC data processor connects the reception buffer memory, receive buffer memory and connect the PCI-Express processor, the PCI-Express processor connects the transmission buffer memory, sends buffer memory and connects the PC data processor.
It is more than the further improvement to the data transmission capabilities of the test macro of fiber optic network.Bidirectional data transfers is exactly adopt to send line and acceptance line method independently separately between two data unit, makes data carry out transfer operation on both direction simultaneously.Data buffer storage is divided into receiving buffer memory and sending buffer memory and is configured in respectively transmission line and acceptance line, adopt this fifo queue of FIFO to realize DMA buffer memory parts, thereby can greatly improve forward efficiency, reduce Forwarding Delay, realized that pipeline system forwards the FC frame, more can solve the FC data processor data rate problem different from PCI Express data rate.
Those skilled in the art can freely select according to the actual requirements the reception buffer memory of data buffer storage and send the ratio of buffer memory.
For further optimization, improve FPGA field programmable gate array data-handling capacity, as preferentially, the test macro of fiber optic network, also comprise data cache device SRAM, described data cache device SRAM connects the FPGA field programmable gate array.
It is more than the further improvement to the data reading capability of the test macro of fiber optic network.Data cache device SRAM has the function of static storage, does not need refresh circuit just can preserve the data of its storage inside, therefore has higher performance, and speed is fast, and read-write sequence is simple, working stability.Adopt data cache device SRAM to provide data cache for FPGA, be conducive to improve the ability of the test macro deal with data of fiber optic network, adapting to more at a high speed, more jumbo data transmission load.
Those skilled in the art can freely select the model of data cache device SRAM according to the actual requirements.
For further optimization, improve the test macro of fiber optic network and the communication capacity of computing machine, the optical-fibre channel data processing module also comprises the PCI-EXPRESS interface, the PCI-EXPRESS interface connects the FPGA field programmable gate array.
It is more than the further improvement to test macro and the computer data exchange capacity of fiber optic network.PCI Express bus is point-to-point high-speed serial bus, and each PCI Express equipment has oneself independently data connection, has guaranteed the monopoly of passage, avoids the interference of other equipment.PCI Express bus is supported the transmitted in both directions pattern, PCI Express bus every to data transfer bandwidth up to 4GB/s, the bidirectional data transfers bandwidth has more than 8GB/s.
Those skilled in the art can freely select the model of PCI-EXPRESS interface according to the actual requirements.
For further optimization, improve the peripheral applications extended capability of the test macro of fiber optic network, as preferably, the test macro of fiber optic network, also comprise interface chip MAX1482, RS485 interface, RS422 interface, RS485 interface, RS422 interface all are connected with interface chip MAX1482, and interface chip MAX1482 connects the FPGA field programmable gate array.
It is more than the further improvement to the application extension ability of the test macro of fiber optic network.Computing machine and and smart machine be generally to communicate with data processing equipment by RS485 interface and RS422 interface, realize demonstration, the storage of data, thus the monitoring and operation function.The MAX1482 interface chip is lower powered full duplex interface chip, and it can realize communicating with RS485 interface, RS422 interface of low EMI and low reflection, and RS485 interface and RS422 interface are all full duplex communication interface.The system of this employing interface chip has abundant peripheral control interface and communication interface.
Those skilled in the art are the model of free option interface chip according to the actual requirements.
For further optimization, improve the circuit logic allocative abilities of the test macro of fiber optic network, realize better systemic-function and circuit logic, as preferentially, the FPGA field programmable gate array is Xilinx XC5VLX110T.
The FPGA field programmable gate array, performance and the function of owned input-output unit able to programme, configurable logic block, digital dock administration module, embedded block RAM, interconnection resource, the embedded functional unit of bottom, embedded special-purpose each module of stone directly depend on its acp chip.。
It is more than the further improvement to the comprehensive configurable ability of test macro of fiber optic network.Xilinx is the technology enterprise in advance of FPGA field programmable gate array industry, the Virtex-5 family chip is first 65nm FPGA product of the whole world that Xilinx company releases, use 1.0V tri-gate oxidation layer process, the ExpressFabric framework of exploitation of innovation is also realized ultimate Integrated.XC5VLX110T belongs to the LXT platform that the high performance logic to low-power consumption serial i/O is optimized.
For further optimization, improve the managerial ability of the test macro of fiber optic network to each module of system, as preferably, central processing unit is Cortex-M3 core ARM microprocessor LPC1769.
It is more than the further improvement to the system management ability of the test macro of fiber optic network.Duty and the buffer queue scheduling of central processing unit for controlling fpga chip, manage the FLASH configuring chip.Cortex-M3 core ARM microprocessor LPC1769, be that it has the JTAG interface towards the chip of the low-power consumption in the embedded market of industry, supports the JTAG debugging, and special instruction tracing unit is provided.
Those skilled in the art can freely select the model of central processing unit according to the actual requirements.
For further optimization, improve the light signal conversion of test macro of fiber optic network and transmitting-receiving ability as preferentially, the model of optical transceiver is FTRJ-8519-1-2.5.
More than to the data-signal conversion of the test macro of fiber optic network and the further improvement of transmitting-receiving ability.Adopt the FTRJ-8519-1-2.5 of Finisar company optical transceiver, it adopts the 850nm laser instrument, and the 2.125Gbps transfer rate is provided, and has good shake and EMI characteristic.
Those skilled in the art are the model of free selective light transceiver according to the actual requirements.
Compared with prior art, the invention has the beneficial effects as follows:
1. with prior art, the FPGA field programmable gate array is being carried out to test program, adopt function logic module and FPGA field programmable gate array separately to carry out, carry out again each module and the programming of FPGA field programmable gate array, the technical scheme that programming is write to eprom memory is compared, logic testing link and programming link that the present invention adopts central processing unit to set up, use the jtag test device directly FPGA field programmable gate array modules and integral body are tested and programmed, test link is stable, efficient, test result is comprehensive, and the testing engineering cycle is short.After the configurator of FPG field programmable gate array and modules thereof has been write, the FLASH storer writes direct.Simultaneously, next time is while starting the FPGA field programmable gate array, directly read in the configurator of FLASH storer, realize the functional configuration of FPGA field programmable gate array, the JTAG debugger can be debugged on the basis of new test procedure, until configurator meets the requirement of the fiber optic network of connection.The FLASH storer had than the better erasable performance of eprom memory, larger capacity, safer, reliable and longer life-span.
2. the present invention adopts and comprises the FC data processor, data buffer storage, the PCI-Express processor, duty register group, the FPGA field programmable gate array of FC data processor, it can realize the transmission demand configuration FPGA field programmable gate array according to fiber optic network, farthest meet monitoring and the operation business of fiber optic network, its construction period is short, flexible configuration, the customization cost is low, adopt Gbps level high-speed serial communication pattern PCI-Express interface can easily realize carrying out large capacity between computing machine and fiber data card, the exchanges data of high load capacity.
3. the present invention adopts interface chip MAX1482, RS485 interface, RS422 interface, can realize the access of more smart machine, realizes demonstration, the storage of data, thereby realizes monitoring and operation function to fiber optic network.
The invention solves the FPGA field programmable gate array is carried out to test program, adopt function logic module and FPGA field programmable gate array separately to carry out test program, programming is write to eprom memory, formality is loaded down with trivial details, construction period is long, the technical matters that effect is undesirable, test link of the present invention is stable, efficiently, test result is comprehensive, the testing engineering cycle is short, when it can also realize that start the FPGA field programmable gate array next time, directly read in the configurator of FLASH storer, realize the functional configuration of FPGA field programmable gate array, the JTAG debugger can be debugged on the basis of new test procedure, until configurator meets the requirement of the fiber optic network of connection.It has good industrial value.。
The accompanying drawing explanation
In order to be illustrated more clearly in embodiments of the invention, below will be briefly described describing the required accompanying drawing of using in the embodiment of the present invention.Apparent, the accompanying drawing in the following describes is only some embodiment that put down in writing in the present invention, for a person skilled in the art, in the situation that do not pay creative work, can also, according to following accompanying drawing, obtain other accompanying drawing.
Fig. 1 is structural representation of the present invention.
Embodiment
In order to make those skilled in the art understand better the present invention, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out to clear, complete description.Apparent, embodiment described below is only the part in the embodiment of the present invention, rather than all.Embodiment based on the present invention record, those skilled in the art are not in the situation that pay other all embodiment that creative work obtains, all in the scope of protection of the invention.
Embodiment mono-:
As shown in Figure 1, the present invention, comprise the first reference clock chip, the second reference clock chip, also comprise central processing unit, optical transceiver, FPGA field programmable gate array, FLASH storer, JTAG debugger, the first reference clock chip, the second reference clock chip, FLASH storer, JTAG debugger all are connected with central processing unit, the JTAG debugger connects the FLASH storer, and central processing unit, optical transceiver all are connected with the FPGA field programmable gate array.
Those skilled in the art can freely select according to the requirement of practice of construction environment and workpiece the parameter of assembly.
Embodiment bis-:
System structure optimization ability for the test macro that improves fiber optic network, the present embodiment improves further on the basis of embodiment mono-, the FPGA field programmable gate array of the present embodiment comprises FC data processor, data buffer storage, PCI-Express processor, duty register group, FC data processor, data buffer storage and PCI-Express processor all are connected with duty register group, FC data processor connection data buffer memory, data buffer storage connects the PCI-Express processor.
Those skilled in the art can freely select according to real work border and design requirement the parameter of assembly.
Embodiment tri-:
Data transmission capabilities for the test macro that improves fiber optic network, the present embodiment improves further on the basis of embodiment bis-, the data buffer storage of the present embodiment comprises the reception buffer memory and sends buffer memory, the PC data processor connects the reception buffer memory, receive buffer memory and connect the PCI-Express processor, the PCI-Express processor connects the transmission buffer memory, sends buffer memory and connects the PC data processor.
Those skilled in the art can freely select according to the actual requirements the reception buffer memory of data buffer storage and send the ratio of buffer memory.
Embodiment tetra-:
Data reading capability for the test macro that improves fiber optic network, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～tri-, the test macro of the fiber optic network of the present embodiment, also comprise data cache device SRAM, data cache device SRAM connects the FPGA field programmable gate array.
Those skilled in the art can freely select the model of data cache device SRAM according to the actual requirements.
Embodiment five:
For test macro and the computer data exchange capacity that improves fiber optic network, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～tetra-, the test macro of 1 fiber optic network of the present embodiment, also comprise the PCI-Express interface, the PCI-Express interface connects the PCI-Express processor.
Those skilled in the art can freely select the type of PCI-Express interface according to the actual requirements.
Embodiment six:
Application extension ability for the test macro that improves fiber optic network, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～five, the test macro of the fiber optic network of the present embodiment, also comprise interface chip MAX1482, RS485 interface, RS422 interface, RS485 interface, RS422 interface all are connected with interface chip MAX1482, and interface chip MAX1482 connects the FPGA field programmable gate array.
Those skilled in the art are the model of free option interface chip according to the actual requirements.
Embodiment seven:
For the comprehensive configurable ability of the test macro that improves fiber optic network, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～six, and the FPGA field programmable gate array of the present embodiment is Xilinx XC5VLX110T.
Those skilled in the art can freely select the model of FPGA field programmable gate array according to the actual requirements.
Embodiment eight:
For the system management ability of the test macro that improves fiber optic network, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～seven, and the central processing unit of the present embodiment is Cortex-M3 core ARM microprocessor LPC1769.
Those skilled in the art can freely select the model of central processing unit according to the actual requirements.
Embodiment nine:
For data-signal conversion and the transmitting-receiving ability of the test macro that improves fiber optic network, the present embodiment improves further on the basis of any one embodiment of embodiment mono-～eight, and the model of the optical transceiver of the present embodiment is FTRJ-8519-1-2.5.
Those skilled in the art are the model of free selective light transceiver according to the actual requirements.
Just can realize this invention as mentioned above.
Claims (9)
1. the test macro of fiber optic network, comprise the first reference clock chip, the second reference clock chip, it is characterized in that: also comprise central processing unit, optical transceiver, FPGA field programmable gate array, FLASH storer, JTAG debugger, described the first reference clock chip, the second reference clock chip, FLASH storer, JTAG debugger all are connected with central processing unit, described JTAG debugger connects the FLASH storer, and described central processing unit, optical transceiver all are connected with the FPGA field programmable gate array.
2. the test macro of fiber optic network according to claim 1, it is characterized in that: described FPGA field programmable gate array comprises FC data processor, data buffer storage, PCI-Express processor, duty register group, described FC data processor, data buffer storage and PCI-Express processor all are connected with duty register group, described FC data processor connection data buffer memory, described data buffer storage connects the PCI-Express processor.
3. the test macro of fiber optic network according to claim 3, it is characterized in that: described data buffer storage comprises the reception buffer memory and sends buffer memory, described PC data processor connects the reception buffer memory, described reception buffer memory connects the PCI-Express processor, described PCI-Express processor connects the transmission buffer memory, and described transmission buffer memory connects the PC data processor.
4. the test macro of fiber optic network according to claim 1, is characterized in that: also comprise data cache device SRAM, described data cache device SRAM connection FPGA field programmable gate array.
5. the test macro of fiber optic network according to claim 1, is characterized in that: also comprise the PCI-Express interface, described PCI-Express interface connection PCI-Express processor.
6. the test macro of fiber optic network according to claim 1, it is characterized in that: also comprise interface chip MAX1482, RS485 interface, RS422 interface, described RS485 interface, RS422 interface all are connected with interface chip MAX1482, and described interface chip MAX1482 connects the FPGA field programmable gate array.
7. the test macro of fiber optic network according to claim 1, it is characterized in that: described FPGA field programmable gate array is Xilinx XC5VLX110T.
8. the test macro of fiber optic network according to claim 1, it is characterized in that: described central processing unit is Cortex-M3 core ARM microprocessor LPC1769.
9. the test macro of fiber optic network according to claim 1, it is characterized in that: the model of described optical transceiver is FTRJ-8519-1-2.5.
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| CN110417503A (en) * | 2019-07-31 | 2019-11-05 | 锐捷网络股份有限公司 | A kind of method and digital communication equipment for test clock network delay |
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