CN101388741B - Highly precised time synchronization device, system and method for computer network - Google Patents

Abstract

The invention provides a high-precision time synchronization device, method and system that can be used for computer network performance test, monitoring system and network simulation. Including: using the hardware circuit to realize the time stamp generation circuit, moving the time stamp recording location to the physical link layer, eliminating the impact of cache delay and interrupt response time delay in common software time stamps; and through the prediction-based time synchronization algorithm ( Prediction-based Clock Synchronization (PCS) realizes precise clock synchronization of each measuring node; the present invention improves the accuracy of the time stamp, and can ensure that the synchronization time stamp error of each measuring node does not exceed 100 ns, achieving a precision equivalent to that of GPS synchronization, but realizing Simple and inexpensive.

Description

A high-precision time synchronization device, system and method for computer network

technical field

The present invention relates to the technical field of computer network applications, and more specifically, the present invention relates to a high-precision time synchronization device, system and method for computer networks. the

Background technique

Applications such as distributed network systems, computer network performance measurement and test systems, and network simulations all require high-precision time synchronization. For example, when sending and receiving data packets in computer network performance measurement, accurate time stamp marks are the basis for network parameter measurement such as delay, bandwidth, and jitter. In a multi-node computer network measurement system, the clocks of each node need to maintain high synchronization accuracy in addition to their own high precision. Otherwise, network performance such as delay and jitter calculated by comparing the timestamp difference between nodes parameters will be inaccurate. the

The commonly used time synchronization method is generally a software clock synchronization method, usually based on the Network Time Protocol (NTP). The node uses the NTP protocol to synchronize with the time server on the network, and calculates the deviation between the node clock and the time server clock by estimating the round-trip delay of the data packet on the network, thereby completing the synchronization of the node clock and the time server clock. NTP can obtain 1ms synchronization accuracy in LAN environment and 28.7ms synchronization accuracy in WAN environment. One way to improve clock synchronization accuracy based on NTP protocol is to apply Time Stamp Counter (Time Stamp Counter, TSC). Mainstream CPUs provide TSC registers, which record the number of clock cycles since the host is powered on. The accuracy is related to the CPU frequency, 1GHz The TSC accuracy of the CPU is 1ns. NTP synchronization combined with TSC counters can improve accuracy down to the microsecond level. However, this software method is difficult to achieve higher precision due to the uncertain cache delay and interrupt response time. the

SynUTC, an Ethernet-based hardware clock synchronization technology, uses hardware circuits to generate time stamps, and the synchronization error can reach 100ns. However, SynUTC needs to modify the underlying structure of Ethernet, and the existing switch hardware must be modified to support SynUTC, which is difficult to promote and apply on a large scale. the

There is also a time synchronization method based on the IEEE 1588 Precision Time Protocol (Precision Time Protocol, PTP). The PTP protocol is a time synchronization standard for network measurement and control systems. According to the accuracy requirements of the application, software synchronization and hardware synchronization are used. The PTP synchronization accuracy realized by hardware can reach 233ns, but the synchronization result is unstable due to the uncertain processing delay of the synchronization data packet in the switch or router. the

Using the external clock source of the Global Position System (GPS), nanosecond-level synchronization accuracy can be achieved. However, the GPS system is expensive, and the installation of the GPS antenna is inconvenient, which limits the deployment location of the measurement nodes. the

Contents of the invention

In order to overcome the defects of poor universality and low precision of time synchronization in existing computer network applications, the present invention proposes a high-precision time synchronization device, system and method for computer networks. the

According to one aspect of the present invention, a kind of time synchronization equipment for network system is proposed, including, GTP transceiver, media access controller, sending and receiving data packet buffer queue and PCIe endpoint controller, it is characterized in that the time synchronization The device also includes one or more time stamp insertion modules and one or more time synchronization algorithm PCS time stamp generators based on prediction;

Wherein, the PCS timestamp generator is used to receive and send a synchronous clock signal to generate a timestamp; the timestamp insertion module is connected to the PCS timestamp generator, the media access controller and the sending and receiving packet buffer queue respectively, The time stamp is inserted into the physical link layer of the data packet; the time stamp insertion module is to insert the time stamp before the data packet received from the media access controller is output to the receiving data packet buffer queue; the sending data packet is buffered Packets in the queue are time stamped before being sent to the media access controller. the

Wherein, the PCS time stamp generator outputs a time stamp according to a preset frequency control word and crystal oscillator clock signal. the

Wherein, the PCS time stamp generator receives a synchronous clock input signal and a crystal oscillator clock signal, generates a time stamp according to a preset frequency control word, and provides it to the time stamp inserting module. the

Wherein, the PCS timestamp generator includes:

A direct frequency synthesizer for generating a clock frequency based on a reference clock signal and a frequency control word;

The time stamp high register, the time stamp low register and the time stamp low counter are used to receive the clock frequency generated by the direct frequency synthesizer, output the time stamp to the time stamp insertion module or provide the time stamp for the main clock. the

According to another aspect of the present invention, a time synchronization system for a network system is proposed, including a plurality of time synchronization devices, wherein one of the plurality of time synchronization devices acts as a master device, and the rest of the time synchronization devices The synchronous device acts as a slave device, the master device generates a synchronous clock output signal, and other slave devices receive the synchronous clock output signal to realize time synchronization of the system. the

Wherein, the PCS time stamp generator of the master device outputs a time stamp to the time stamp insertion module of the master device and the slave device according to a preset frequency control word and a crystal oscillator clock signal. the

Wherein, the PCS time stamp generator of the slave device receives the synchronous clock output signal and the crystal oscillator clock signal, generates a time stamp according to a preset frequency control word and provides it to the time stamp insertion module of the slave device. the

According to yet another aspect of the present invention, a kind of time synchronization method using the above-mentioned time synchronization system is proposed, comprising:

Step 10), the slave device receives the synchronous clock output signal of the master device, and reads the current time of the slave device;

Step 20), obtaining the third reading and the second reading and the time difference Δt ₂ and Δt ₁ between the second reading and the first reading;

其中，N为频率控制字位数， 

为初始频率控制字，更新所述频率控制字， 

其中m为时间戳精度；  Step 30), obtaining the frequency signal of the reference clock,

Among them, N is the number of frequency control words,

is the initial frequency control word, updating the frequency control word,

Where m is the timestamp precision;

调整从设备的时钟频率，并计算更新的频率控制字 

使用所述频率控制字 

调整从设备时钟频率，实现系统的同步。  Step 40), through the frequency control word

Adjust the clock frequency of the slave device and calculate the updated frequency control word

Using the frequency control word

Adjust the clock frequency of the slave device to achieve system synchronization.

Wherein, the method also includes:

e¹(i)＝2^m-Δt_i，计算频率控制字 

通过 

调整从设备的时钟频率。  Step 50), calculate the time difference Δt _i =T _i -T _i-1 between two consecutive readings of the master device from the device; obtain the errors e ⁰ (i) and e ¹ (i) in the two readings,

e ¹ (i)＝2 ^m -Δt _i , calculate the frequency control word

pass

Adjust the clock frequency of the slave device.

The present invention utilizes hardware circuits to implement time stamps, and moves the time stamp record position to the physical link layer, eliminating the impact of cache delays and interrupt response time delays in common software time stamps; through the prediction-based time synchronization algorithm (Prediction- based Clock Synchronization (PCS) realizes accurate clock synchronization of each measurement node; the invention improves the accuracy of the time stamp, can ensure that the time stamp error of each measurement node does not exceed 100ns, and achieves an accuracy equivalent to that of GPS synchronization. the

Description of drawings

Fig. 1 is a schematic diagram of a high-precision time synchronization scheme according to an embodiment of the present invention;

Figure 2 is a schematic diagram of the position where a time stamp can be added in a traditional receiving scenario;

Figure 3 is a schematic diagram of the time stamp deviation of the two cards when the PCS synchronization algorithm is not used;

Figure 4 is a schematic diagram of the time stamp interval of adjacent sampling data packets of each card in Figure 3;

Fig. 5 is a schematic structural diagram of a time synchronization system according to an embodiment of the present invention;

Fig. 6 is a schematic diagram of a hardware time stamp generation circuit according to an embodiment of the present invention;

Fig. 7 is a schematic diagram of a time stamp insertion circuit according to an embodiment of the present invention;

Fig. 8 is the time sequence diagram based on the time synchronization algorithm PCS of prediction of the present invention;

Fig. 9 is the time synchronization algorithm PCS flowchart based on prediction of the present invention;

Fig. 10 is a schematic diagram of a verification environment according to an embodiment of the present invention;

Figure 11 is a two-hour result diagram of the time stamp deviation of the two cards using the PCS synchronization algorithm;

Figure 12 is a 12-hour result diagram of the time stamp deviation of the two cards using the PCS synchronization algorithm;

Fig. 13 is a schematic diagram of the prediction error of the PCS algorithm. the

Detailed ways

A high-precision time synchronization device, system and method for computer networks provided by the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. the

Fig. 1 shows the overall scheme of high-precision time synchronization according to an embodiment of the present invention, as shown in Fig. 1, first utilize hardware circuit (such as FPGA, PLA etc. similar structure) to realize time stamp generation circuit, generate time synchronization equipment, time The location of the stamp record is moved to the physical link layer to eliminate the impact of cache delay and interrupt response time delay in the common software method time stamp; connect each synchronization device to each other, set a master synchronization device, and connect all the devices that need to be synchronized A time synchronization system is formed, in which a prediction-based clock synchronization algorithm (Prediction-based Clock Synchronization, PCS) is applied to realize precise clock synchronization of each node device. In this embodiment, the time stamp generation circuit is constructed by FPGA. Similarly, based on the following schematic description of the time stamp generation circuit, the time stamp generation circuit can also be implemented using PLA, ASIC or other integrated circuits. In this embodiment, RS422 is used to connect the synchronization device when the time synchronization system is constructed by using the time stamp generation circuit. Similarly, the present invention can also use other known connection technologies such as RS484, RS232 or USB, PCI, etc. In the constructed time synchronization system, the PCS time synchronization method is applied to realize high-precision synchronization of connected devices. the

Figure 2 is a schematic diagram of the position where the time stamp is added in the network data packet receiving scenario. In the traditional network interface card data packet receiving scenario, the data packet in the user space domain arrives at the network interface card based on the specific application program, and the network interface card sends the data packet according to the network The protocol (such as TCP/IP) is forwarded to the host memory, and the driver is notified by an interrupt to process the received data packet. The host responds to the interrupt, and copies the received data packet to the upper layer protocol stack for processing, and the processed data packet finally reaches the application program. As shown in Figure 2, during this process, timestamps can be added at multiple locations: Media Access Control (MAC) layer, driver layer, and application layer. Adding timestamps at different locations is affected by cache delay and interrupt response time delay, and the deviation between timestamps and the real time of data packet arrival is also different. Among them, the media access control layer is least affected, the driver layer, and the application layer Most affected; the difference is on the order of milliseconds. In the embodiment of the present invention, this deviation is defined as an additional time stamp error. the

Figure 3 is a schematic diagram of the time stamp deviation generated by crystal oscillators with the same nominal frequency. The clock that generates the time stamp is affected by the jitter and drift of the crystal oscillator and its rate is unstable. Therefore, the generated time stamp will also deviate over time. the

FIG. 4 is a schematic diagram of time stamp intervals between adjacent sampled data packets in FIG. 3 , both of which are time stamp deviations generated by crystal oscillators with the same nominal value. Therefore, in the present invention, the deviation caused by the instability of the crystal oscillator is defined as the error of the time stamp itself. Therefore, the time stamp error defined in the embodiment of the present invention is composed of the time stamp itself error and the time stamp additional error. To improve the time synchronization accuracy, it is necessary to reduce the time stamp itself error and the additional error. the

In the embodiment of the present invention, the time stamp recording location is moved to the physical link layer, and the time stamp is added to the application system by a hardware circuit. FIG. 5 is a structural diagram of a time stamp synchronization device according to a specific embodiment of the present invention. Since the time stamp is added after the data packet leaves the MAC, various software delay factors in the time stamp additional error can be eliminated, and the time stamp accuracy can be improved to the nanosecond level. the

In this embodiment, the device circuit structure is realized based on FPGA, and the circuit structure can be applied to a network card or other network measurement devices. the

As shown in Figure 5, the time synchronization device includes a GTP (General Packet Radio Service Tunneling Protocol) transceiver, a media access controller, a sending and receiving data packet buffer queue (a receiving data packet queue and a sending data packet queue in the figure) and a PCIe (PCI Express) endpoint controller. The input and output of the synchronous clock in the existing equipment are directly connected to the media access controller through the sending and receiving data packet buffer queue, and the synchronization is realized through software control. In this embodiment, the time synchronization system device further includes one or more time stamp insertion modules and one or more PCS time stamp generators, wherein, the PCS time stamp generator receives and sends the synchronous clock, and receives the packet processor's The control signal is connected with the timestamp insertion module to control the timestamp insertion module, and the timestamp insertion module is respectively connected with the PCS timestamp generator, the media access controller, the packet processor and the sending and receiving data packet buffer queue, and the timestamp Inserted into the physical link layer of network data. In this embodiment, two time stamp insertion modules are shown in the figure, and one time stamp insertion module may be used in the present invention. the

Each part that needs to be synchronized is interconnected through the synchronous clock input and output shown in Figure 5 (it can be any form of serial input or other known connection mode on the physical connection), and the clock signal generated by the PCS time stamp generator is input to the time Stamp insertion module (for example, the content of the data transmission is 64-bit time stamp information), in which the clock signal is inserted into the received or sent network data packet. the

Fig. 6 shows the detailed circuit of the PCS time stamp generator shown in Fig. 5. As shown in Fig. 6, the core of the generator is a direct frequency synthesizer, and the generated clock frequency is adjusted by adjusting the frequency control word. In this embodiment, the timestamp register has a total of 64 bits, the high 32-bit value represents the number of seconds from 0:00 on January 1, 1970, and the low 32-bit value represents the fraction of a second. The highest resolution that this representation can achieve is ^2-32 s, that is, 233ps, and by setting the low 32-mbit to 0, a clock with a resolution of 2 ^-m s can be obtained. The initial value of the high 32bit second count of the timestamp register is written by the host through the driver during initialization, so the host time is required to have second-level precision, which can be easily realized through the NTP protocol; the low 32bit second fraction is generated by the internal counter, and the counter is directly The frequency synthesizer outputs the clock frequency f _syn and counts down, and generates a carry signal after the count is full, and adds 1 to the high 32bit count value.

As shown in Figure 6, the components are connected through data lines, where the reference clock is the clock input by the external crystal oscillator shown in Figure 5, and the frequency control word is the preset frequency adjustment parameter; the output value of the direct frequency synthesizer is stored in the time stamp In the low counter; the carry signal of the timestamp low counter is input into the timestamp high register. When the node is the master node, the carry signal will also generate an output pulse signal to the slave node; the timestamp high register and the timestamp low register The value is sent to the timestamp insertion module; when the node is a slave node, the input pulse provided by the master node is used to generate an interrupt signal and notify the driver to read the value of the current timestamp register. the

Fig. 7 shows the detailed circuit of the time stamp insertion module shown in Fig. 5, as shown in Fig. 7, the data packet that receives is deposited in the register earlier, inserts current clock information ( The current clock value is generated by the hardware timestamp generation circuit shown in Figure 6); the data in the sending data packet queue is also stored in the register before sending, and sent to the MAC after inserting the current clock; wherein, the data clock information is inserted into the data physical link layer. the

In another embodiment of the present invention, the present invention proposes a time synchronization system, including a plurality of time synchronization devices described above, wherein one of the time synchronization devices acts as a master device to generate a synchronous clock output signal, and the The rest of the time synchronization devices, as slave devices, receive the synchronous clock output signal sent by the master device, and realize the time synchronization of the system through the corresponding processing of the time stamp generator and time stamp insertion module of the device. All slave devices are interconnected or respectively connected with the master synchronization device to form a time synchronization system. The connection methods include but are not limited to RS484, RS232, RS422 and USB. The PCS time stamp generator of the master device outputs a time stamp to the time stamp insertion module of the master device and the slave device according to the preset frequency control word and crystal oscillator clock signal. The PCS time stamp generator of the slave device receives the synchronous clock output signal and the crystal oscillator clock signal, generates a time stamp according to the preset frequency control word, and provides it to the time stamp insertion module of the device. the

The present invention also proposes a prediction-based clock synchronization algorithm (Prediction-based Clock Synchronization, PCS) to complete the clock synchronization between multiple nodes through the above-mentioned system. When multiple nodes are synchronized, it is necessary to designate a master node to send a reference clock, and the master node Node synchronization nodes are called slave nodes. The designation of the master-slave nodes depends on the application requirements without any additional restrictions. The master-slave nodes are interconnected through an asynchronous serial bus. During synchronization, the master node outputs a pulse to each slave node every 1s. After the slave node receives the pulse, it reads the time stamp register, measures the result of the previous second, and adjusts the DDS frequency control word to expect the smallest synchronization deviation in the next second. The timing diagram of the present invention is shown in FIG. 8 , and the present invention is divided into two stages of startup and synchronization. the

Startup phase:

In step 0, the slave node starts. When the slave node PCS timestamp generator receives the second pulse output by the master node, it reads the current time T ₀ from the timestamp counter, and at the same time generates an interrupt signal to notify the driver to read the value;

Step 1, when the slave node PCS time stamp generator receives the second pulse output by the master node again, it reads the current time T ₁ from the time stamp counter, and at the same time generates an interrupt signal to notify the driver to read the value, and the driver uses the 0th Calculate the time difference between the 0th step and the 1st step Δt ₁ =T ₁ -T ₀ from the time value read in step 1 and step 1;

其中N为频率控制字位数，本实施例中值为32； 

为初始频率控制字，本实施例中值为0xABCC7712；驱动利用下面的公式计算新的频率控制字  Step 2, when the slave node PCS timestamp generator receives the second pulse output by the master node for the third time, it reads the current time T ₂ from the timestamp counter, and at the same time generates an interrupt signal to notify the driver to read the value, and the driver uses Calculate the time difference Δt ₂ =T ₂ -T ₁ between step 1 and step 2 from the time values read in step 1 and step 2, and use the following formula to calculate the actual frequency of the reference clock (crystal oscillator output);

Wherein N is the number of digits of the frequency control word, and the value in this embodiment is 32;

is the initial frequency control word, the value in this embodiment is 0xABCC7712; the driver uses the following formula to calculate the new frequency control word

其中m为时间戳精度，本实施例中值为24； 

Where m is the timestamp precision, and the value in this embodiment is 24;

Step 3, when the slave node PCS timestamp generator receives the second pulse output by the master node for the fourth time, it reads the current time T ₃ from the timestamp counter, and at the same time generates an interrupt signal to notify the driver to read the value, and the driver uses Calculate the time difference between the second step and the third step Δt ₃ =T ₃ -T ₂ from the time values read in the second step and the third step. Apply the frequency control word calculated in step 2 from the node PCS timestamp generator Adjust the clock frequency, and the driver uses the following formula to calculate the new frequency control word

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="K\; dds"\; filenames="DEST\_PATH\_HSB00000450438700011.png,H2008102248913E00042.png"\; state="\{\{state\}\}">K</figure-callout></span><figure-callout\; id="2"\; label="K\; dds"\; filenames="DEST\_PATH\_HSB00000450438700011.png,H2008102248913E00042.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">dds</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="K\; dds"\; filenames="H2008102248913E00021.png,H2008102248913E00062.png"\; state="\{\{state\}\}">K</figure-callout></span><figure-callout\; id="0"\; label="K\; dds"\; filenames="H2008102248913E00021.png,H2008102248913E00062.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">dds</span>}}}{{\mathrm{<span\; class="notranslate">\; \&Delta;<figure-callout\; id="3"\; label="t"\; filenames="H2008102248913E00021.png"\; state="\{\{state\}\}">t</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}$

调整时钟频率，并由驱动利用上面第3步的公式计算新的频率控制字 至此，启动阶段结束。  Step 4, when the slave node PCS timestamp generator receives the second pulse output by the master node for the fifth time, it reads the current time T ₄ from the timestamp counter, and at the same time generates an interrupt signal to notify the driver to read the value, and the slave node The PCS timestamp generator applies the frequency control word calculated in step 3

Adjust the clock frequency, and the driver uses the formula in step 3 above to calculate the new frequency control word At this point, the start-up phase is over.

B. Synchronization phase:

After the 4-step adjustment in the startup phase, the clock of the slave node and the clock of the master node have been synchronized, but considering the instability of the clock crystal oscillator, the slave node needs to continuously correct the frequency control word, so as to maintain long-term synchronization with the master node;

1. When the slave node PCS time stamp generator receives the second pulse output by the master node, it reads the current time T _i from the time stamp counter, and at the same time generates an interrupt signal to inform the driver to read the value, and the driver calculates the time of two consecutive interruptions Time difference Δt _i =T _i -T _i-1 ;

2. Drive the calculation of the first two steps of prediction errors e ⁰ (i) and e ¹ (i):

${\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; \&Delta;t</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; dds</span>}}^{\mathrm{<span\; class="notranslate">\; i</span>}}}{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; dds</span>}}^{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}$

e ¹ (i)=2 ^m -Δt _i , the calculation of the prediction error is not limited to the calculation formula provided in this embodiment, and the meanings of the variables in the formula are the same as those mentioned above;

驱动计算下一步频率控制字 

3. Apply the frequency control word calculated in the last cycle from the node PCS timestamp generator

The drive calculates the next frequency control word

${\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; dds</span>}}^{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; \&Delta;t</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; dds</span>}}^{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ,</span>$

Different frequency control words will make the clock frequency synthesized by the direct frequency synthesizer in Figure 6 be different. If the time of the slave node is found to be faster within the interval between the two pulses of the master node, then the frequency control word of the slave node needs to be adjusted down. Conversely, turn it up. Through continuous adjustment, it can be ensured that the clock of the slave node is consistent with the clock of the master node. the

When performing the synchronization and synchronization test of specific devices, the devices that need to be synchronized are interconnected by using asynchronous serial connection lines (for example, RS422) as shown in FIG. 10 . Fig. 10 is in order to verify the experimental environment of the performance of the present invention, the network tester adopts TestCenter of Spirent Company, utilizes its gigabit module to send out the test data packet, divides one road traffic into two roads same traffics by optical splitter, connects to Two test nodes, the time when the data packet arrives at the two test nodes is the same. The two test nodes are respectively installed on high-performance servers. Install two network cards with the synchronization device, start the synchronous driving method, and use RS422 to connect the two network cards to perform synchronization or testing. the

Figure 11 is the two-hour result of the time stamp deviation of the two cards using the PCS synchronization algorithm, where the abscissa is the measurement time point, and the ordinate is the time stamp deviation of the two cards (in nanoseconds). From the results, it can be seen that the time stamp deviation Between -50ns and 180ns. Figure 12 shows the 12-hour statistical results of the time stamp deviation of two cards using the PCS synchronization algorithm, where the abscissa is the time stamp deviation, and the ordinate is the frequency of the deviation. From the results, it can be seen that the PCS algorithm adjusts the frequency control word very quickly The synchronization of the two devices is well completed, and most of the time stamp deviations are controlled within 0-100ns. Figure 13 shows the prediction error of the PCS algorithm, where the abscissa is the measurement time point, and the ordinate is the time stamp deviation between the two cards (in nanoseconds). From the results, it can be seen that the prediction error is mainly distributed within -50ns to 50ns. the

Finally, it should be noted that the above embodiments are only used to describe the technical solutions of the present invention rather than limit the technical methods of the present invention. The present invention can be extended to other modifications, changes, applications and embodiments in application, and therefore it is considered that all such Modifications, changes, applications, and embodiments are all within the spirit and teaching scope of the present invention. the

Claims (9)

1. time synchronism equipment that is used for network system; Comprise; General packet radio service tunnel agreement (GTP) transceiver, MAC controller, the formation of reception packet buffering, transmission packet buffering formation and peripheral element high speed expansion interface (PCIe) endpoint controller; It is characterized in that said time synchronism equipment also comprises one or more timestamp insert module and one or more time synchronized algorithm PCS time stamp generator based on prediction;

Wherein, said PCS time stamp generator is used for generation time and stabs; Said timestamp insert module is connected with PCS time stamp generator, MAC controller, the formation of reception packet buffering and the formation of transmission packet buffering respectively, said timestamp is inserted into the physical link layer of packet; Said timestamp insert module is before the packet that receives from said MAC controller outputs to the formation of reception packet buffering, to insert timestamp; The packet that sends in the packet buffering formation inserted timestamp before sending to said MAC controller.

2. the time synchronism equipment of claim 1, said PCS time stamp generator is according to frequency preset control word and crystal oscillator clock signal, and output time stabs to the timestamp insert module.

3. the time synchronism equipment of claim 1, said PCS time stamp generator receive synchronised clock output signal and crystal oscillator clock signal, and according to the frequency preset control word, generation time stabs and offers said timestamp insert module.

4. the time synchronism equipment of claim 1, said PCS time stamp generator comprises:

Direct synthesizer is used for producing clock frequency according to reference clock signal and frequency control word;

The high bit register of timestamp, the low bit register of timestamp and timestamp low counter are used to receive the clock frequency that said direct synthesizer produces, and output time stabs the timestamp insert module or is provided for the master clock timestamp.

5. clock synchronization system that is used for network system; Comprise any described time synchronism equipment of a plurality of claims 1 to 4, wherein, one of them of said a plurality of time synchronism equipments is as main equipment; Remaining time synchronism equipment is as slave unit; Said main equipment produces synchronised clock output signal, and remaining slave unit receives said synchronised clock output signal, realizes the time synchronized of system.

6. the clock synchronization system of claim 5, wherein, the PCS time stamp generator of said main equipment is according to frequency preset control word and crystal oscillator clock signal, and output time stabs the timestamp insert module to said main equipment.

7. the clock synchronization system of claim 5, wherein, said slave unit PCS time stamp generator receives said synchronised clock output signal and crystal oscillator clock signal, and according to the frequency preset control word, generation time stabs the timestamp insert module that offers slave unit.

8. method for synchronizing time that is used in the described clock synchronization system of claim 5 comprises:

Step 10), slave unit receive the synchronised clock output signal of main equipment, the current time of reading this slave unit;

Step 20), obtain time difference Δ t between reading for the third time and read for the second time and read for the second time and reading for the first time ₂With Δ t ₁

Step 30), obtain the frequency signal of reference clock,

Wherein, N is the FREQUENCY CONTROL word bit number,

Be the original frequency control word, upgrade said frequency control word, $K_{\mathrm{Dds}}^1=\left(\frac{4\&times;2^m-({\mathrm{\&Delta;\; t}}_1+{2\mathrm{\&Delta;\; t}}_2)}{{\mathrm{\&Delta;\; t}}_2}\right)\&times;K_{\mathrm{Dds}}^0,$ Wherein m is the timestamp precision;

Step 40), adjust the clock frequency of slave unit through frequency control word

; And calculate the frequency control word

that upgrades and use said frequency control word

adjustment slave unit clock frequency, realize the synchronous of system.

9. the method for claim 8, wherein, said method also comprises:

Step 50), calculate the double time difference Δ t that slave unit reads main equipment _i=T _i-T _I-1Obtain the error e in reading for twice ⁰(i) and e ¹(i),

e ¹(i)=2 ^m-Δ t _i, the calculated rate control word

Through

The clock frequency of adjustment slave unit.

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