CN106708168B - multiprocessor system and clock synchronization method - Google Patents
multiprocessor system and clock synchronization method Download PDFInfo
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- CN106708168B CN106708168B CN201510778794.9A CN201510778794A CN106708168B CN 106708168 B CN106708168 B CN 106708168B CN 201510778794 A CN201510778794 A CN 201510778794A CN 106708168 B CN106708168 B CN 106708168B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
Abstract
the embodiment of the invention relates to a multiprocessor system and a clock synchronization method, wherein the method comprises the following steps: when the master processor detects the slave processors with hot insertion, if the high level of the TSC synchronous pins is effective, the TSC synchronous pins of all the processors are enabled, and an indication signal is sent to the first programmable logic device, wherein the indication signal is used for indicating the first programmable logic device to generate a high pulse which is started from the low level and is longer than a preset time length on the falling edge of the first number of bus clocks; after the master processor and each slave processor detect that the high pulse reaches a self TSC synchronous pin, sampling the count value of the TSC counter through the rising edge of an internal synchronous clock; and synchronizing the TSC clocks of the slave processors and the master processor according to the count value of the TSC counter sampled by each slave processor and the count value of the TSC counter sampled by the master processor. Therefore, in the embodiment of the invention, the main processor is matched with the programmable logic device, so that the success rate of TSC clock synchronization can be improved.
Description
Technical Field
The present invention relates to the field of computers, and more particularly, to a multiprocessor system and a clock synchronization method.
Background
Currently, multiprocessor systems are widespread, and clocks are required between cores of each processor in the multiprocessor system for time synchronization between threads, and currently, X86 servers compare the prevailing core clocks to two types: a timestamp Timer (TSC) clock and a high precision timer (HPET) clock. The difference between them is that the TSC clock is based on a 64-bit hardware counter inside the Central Processing Unit (CPU), while the HPET clock counter needs to be read from the memory. When the system works in the HPET clock, when the performance test is applied to the actual TPC-C database, a great deal of CPU time loss is found in the operation of processing and reading the data in the memory clock. Through practical TPC-C tests, in a 4p (intel ivb) system, the performance of the system when operating in the HPET clock is found to be 49% of the performance when operating in the TSC clock. In larger systems, this criterion is worsened by the increased memory access latency, which necessarily requires that the system be operated in the TSC clock state.
the server based on the X86 platform advances towards the direction of a small machine, and can support the construction of a 32P system after the expansion of a Node Connection (NC) chip; in an X86 based system, TSC clock synchronization can occur in two states: (1) a power-on process; (2) and (5) hot plug process of the CPU. The TSC synchronization condition in the power-on process includes two conditions: (1) processing _ PG (power supply power-on completion indication signal) of all processors of a system needs to be valid within 10 ns; (2) the clocks are synchronized. TSC synchronization conditions occurring in the CPU hot plug process are three: (1) the system in operation uses a TSC clock; (2) the PROCESS _ PG of the hot-plug CPU needs to be effective after 864BCLKs (corresponding to the CPU model IVB-EX) or 384BCLKs (corresponding to the CPU model HSW-EX) integral-multiple delay of the PROCESS _ PG signal of the original system, and the error cannot exceed one BCLK, wherein the BCLK is an input reference clock of the CPU, which can also be called a bus clock, and one BCLK is generally 10 ns; (3) the BIOS of the system needs to actively initiate a TSC synchronization request.
In the hardware field, the conditions (1) and (2) in the power-on synchronization process are solved by the scheme; the condition (1) in the hot plug synchronous process is ensured by the power-on synchronous process, the condition (2) in the hot plug process is solved by a relevant scheme, but the condition (3) in the hot plug process has some challenges in the field of large systems.
The current complete machine system uses 1P as a unit, QPI (a high-speed link for interconnection between CPUs) of 8 CPU boards are interconnected through a passive signal backplane to form an 8P system, 4 8P frames are interconnected through an NI link (a high-speed link on an NC chip) to form a 32P system, and the existing scheme is to directly interconnect TSC synchronization pins (TSC _ SYNC pins) of 32 CPUs of one system with an external stray board through a 3m long cable, thereby realizing the TSC synchronization process.
the clock synchronization method in the prior art is formed based on a current multiprocessor system, for TSC synchronization pins with effective high level, when TSC synchronization is actually carried out, a Basic Input Output System (BIOS) pulls up TSC synchronization pins of each CPU one by one, after the TSC synchronization pin of the last CPU is pulled up, the whole TSC bus becomes high level according to the result of line matching, and the system uses the rising edge of an internal synchronization clock (internal sync clock) to sample the current TSC counter (counter) value for synchronization in a high level window of the TSC;
Due to the fact that device delay, cable delay and delay generated by rising edge conversion caused by the fact that the output type of a CPU is Open Drain (OD) output, the time difference of the rising edge of the TSC waveform reaching each CPU can exceed the index of 500ns given by Intel, although the edge difference of the TSC _ SYNC signal is 1us through actual verification, the TSC _ SYNC signal can be synchronized successfully, the margin is too small, and potential safety hazards exist in stability.
disclosure of Invention
The embodiment of the invention provides a multiprocessor system and a clock synchronization method, which can improve the success rate and stability of clock synchronization.
In a first aspect, a clock synchronization method for a multiprocessor system is provided, the multiprocessor system including a master processor and at least one slave processor, a TSC synchronization pin connecting the master processor and the slave processor via a TSC bus, the TSC bus having a first programmable logic device connected thereto, the method including:
When the master processor detects that the slave processors with hot insertion exist, if the TSC synchronous pins are high-level effective, the TSC synchronous pins of all the processors are enabled, and an indication signal is sent to the first programmable logic device, wherein the indication signal is used for indicating the first programmable logic device to generate a high pulse which is started from low level and is longer than a preset time length on the falling edge of a first number of bus clocks;
after each slave processor in the master processor and the at least one slave processor detects that the high pulse reaches a TSC synchronous pin of the slave processor, sampling the count value of the TSC counter through the rising edge of an internal synchronous clock;
and according to the count value of the TSC counter sampled by each slave processor in the at least one slave processor and the count value of the TSC counter sampled by the master processor, enabling the count values of the TSC counters of the at least one slave processor and the master processor to be equal, and carrying out TSC clock synchronization.
With reference to the first aspect, in a first possible implementation manner of the first aspect, after the TSC synchronization pins of all processors are enabled, the method further includes:
And after the enabling state of the TSC synchronous pins of all the processors is kept for a certain time, pulling down the TSC synchronous pins of all the processors to restore the TSC synchronous pins of all the processors to the initial state.
with reference to the first aspect, in a second possible implementation manner of the first aspect, the method further includes:
When the master processor detects that a slave processor which is hot-plugged exists, if the TSC synchronous pin is effective in low level, an indication signal is sent to the first programmable logic device, and the indication signal is used for indicating the first programmable logic device to generate a low pulse which starts from high level and is longer than a preset time length on the falling edge of a second number of bus clocks;
After each slave processor in the master processor and the at least one slave processor detects that the low pulse reaches a TSC synchronous pin of the slave processor, sampling the count value of the TSC counter through the rising edge of an internal synchronous clock;
And according to the count value of the TSC counter sampled by each slave processor in the at least one slave processor and the count value of the TSC counter sampled by the master processor, enabling the count values of the TSC counters of the at least one slave processor and the master processor to be equal, and carrying out TSC clock synchronization.
With reference to the first aspect or the first or second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the sending an indication signal to the first programmable logic device includes:
a General Purpose Input/Output (GPIO) pin of a Platform Controller Hub (PCH) is at a low level, and an indication signal is sent to the first programmable logic device through the low level Output by the GPIO pin.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, a second programmable logic device is connected to the TSC bus; the sending an indication signal to the first programmable logic device includes:
And operating the GPIO pin of the PCH to be at a low level, controlling the second programmable logic device to output the low level through the low level output by the GPIO pin, and sending an indication signal to the first programmable logic device through the low level output by the second programmable logic device.
In a second aspect, a multiprocessor system is provided, which comprises a master processor and at least one slave processor, wherein TSC synchronous pins of the master processor and the slave processor are connected through a TSC bus, and a first programmable logic device is connected to the TSC bus;
the master processor is used for enabling TSC synchronous pins of all processors and sending an indication signal to the first programmable logic device when the master processor detects that a slave processor with hot insertion exists, wherein the high level of the TSC synchronous pins is effective, and the indication signal is used for indicating the first programmable logic device to generate a high pulse which is started from a low level and is longer than a preset time length on the falling edge of a first number of bus clocks;
the master processor and each slave processor in the at least one slave processor are used for sampling the count value of the TSC counter through the rising edge of an internal synchronous clock after detecting that the high pulse reaches the TSC synchronous pin of the master processor and each slave processor in the at least one slave processor;
And each slave processor in the at least one slave processor is used for enabling the count value of the TSC counter of the slave processor and the count value of the TSC counter of the master processor to be equal according to the count value of the TSC counter sampled by the slave processor and the count value of the TSC counter sampled by the master processor, and carrying out TSC clock synchronization.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the main processor is further configured to, after the enabling of the TSC synchronization pins of all the processors and maintaining the enabled states of the TSC synchronization pins of all the processors for a certain time, pull down the TSC synchronization pins of all the processors to restore the TSC synchronization pins of all the processors to the initial state.
With reference to the second aspect, in a second possible implementation manner of the second aspect, the master processor is further configured to send an indication signal to the first programmable logic device if the TSC synchronization pin is active low when the master processor detects that there is a slave processor that has a hot plug, where the indication signal is used to instruct the first programmable logic device to generate a low pulse that is greater than a preset time length from a high level on a falling edge of a second number of bus clocks;
the master processor and each slave processor in the at least one slave processor are further used for sampling the count value of the TSC counter through the rising edge of an internal synchronous clock after detecting that the low pulse reaches the TSC synchronous pin of the master processor and each slave processor in the at least one slave processor;
each slave processor in the at least one slave processor is further configured to make the count value of the TSC counter of the slave processor and the count value of the TSC counter of the master processor equal to each other according to the count value of the TSC counter sampled by the slave processor and the count value of the TSC counter sampled by the master processor, and perform TSC clock synchronization.
With reference to the second aspect or the first or second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the main processor is specifically configured to operate a GPIO pin of the PCH to be a low level, and send an indication signal to the first programmable logic device through the low level output by the GPIO pin.
With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, a second programmable logic device is connected to the TSC bus; the main processor is specifically configured to operate a GPIO pin of the PCH to be a low level, control the second programmable logic device to output the low level through the low level output by the GPIO pin, and send an indication signal to the first programmable logic device through the low level output by the second programmable logic device.
The embodiment of the invention provides a clock synchronization method, which is characterized in that a programmable logic device is introduced into a multiprocessor system to divide a TSC bus into a plurality of domains, a main processor sends out a synchronization signal to control the programmable logic device to synchronize signals on the TSC bus, wherein the programmable logic device also has the function of enhancing driving, so that the time difference that the rising edge of the waveform of the TSC reaches each CPU can be reduced, the system after hot plugging works under the TSC clock, and the stability is good.
Drawings
FIG. 1 is a TSC clock synchronization timing diagram during hot-plug process;
FIG. 2 is a schematic diagram of a TSC _ SYNC pin type;
FIG. 3 is a block diagram of a multiprocessor system with TSC _ SYNC direct connection;
FIG. 4 is a diagram illustrating a multiprocessor system according to an embodiment of the present invention;
FIG. 5 is a signal flow diagram of a clock synchronization method according to an embodiment of the present invention;
FIG. 6 is a TSC synchronization waveform of an embodiment of the present invention;
Fig. 7 is a signal flow diagram of a clock synchronization method according to another embodiment of the present invention.
Detailed Description
the technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described below in conjunction with the drawings in the embodiments of the present invention.
the invention provides a solution to the problems of low TSC clock synchronization success rate and poor stability caused by too long TSC _ SYNC direct link in the existing multiprocessor system.
In a specific embodiment of the present invention, the GPIO pin of the PCH (south bridge chip in the X86 platform) is controlled by the main processor to perform synchronization or delay, and the driving is enhanced by the logic device. Since the reliability of the TSC synchronization signal direct interconnection of the current 8P or 4P server has been verified, the 32P system with higher signal integrity risk is decomposed into the 4P or 8P system with lower risk by the programmable logic device.
In the embodiment of the present invention, the number of processors included in the multiprocessor system is not specifically limited, and for convenience of description, only the 32P system is taken as an example for explanation.
Fig. 1 is a TSC clock synchronization timing diagram during hot plug, and referring to fig. 1, a time when a power supply power-on completion indication signal (PWRGOOD) of a CPU reaches a hot-plugged CPU needs to have a specific relationship in a time domain with the signal of an original CPU: 864BCLKs (corresponding to CPU model IVB-EX) or 384BCLKs (corresponding to CPU model HSW-EX); the time difference of the TSC _ SYNC effective edge reaching all the CPU pins cannot exceed 500 ns; on the current platform, the TSC _ SYNC in IVB-EX is effective at high level, and the TSC _ SYNC in HSW-EX is effective at low level.
Fig. 2 is a schematic diagram showing types of TSC _ SYNC pins, and referring to fig. 2, for a hot plug clock synchronization process, a BIOS of a system is required to actively initiate a TSC synchronization request, the current processing mode is that the BIOS controls the TSC _ SYNC pin of a CPU by writing a PCODE register of the CPU, an IO type of the signal at the CPU is I/OD, the pins of all CPUs are required to be connected by hardware at a board level, and the board level is pulled up.
In order to compare with the multiprocessor system structure provided by the embodiment of the present invention, the embodiment of the present invention provides a multiprocessor system structure under the TSC _ SYNC direct connection condition, referring to fig. 3, the whole system is an 8P system formed by interconnection of QPI (a high-speed link for interconnection between CPUs) of 8 CPU boards through a passive signal backplane, 4 8P frames form a 32P system through an NI link (a high-speed link on an NC chip), and TSC _ SYNC pins of 32 CPUs of one system are directly interconnected with external strays through a 3m long cable, so as to implement the TSC synchronization process. All level conversion devices on the bus device are bidirectional and OD output type devices, the translator is a converter without bus driving capability, and the driving capability of the bus is adjusted through an external pull-up resistor.
The TSC pins of the X86 platform are I/OD type interfaces inside the CPU, the high level is effective, when TSC synchronization is actually carried out, the BIOS raises the TSC one by one, the whole TSC bus becomes the high level due to the wire-AND result after the last CPU pin is raised, and the system uses the rising edge of the Internal Sync Clock to sample the current TSC Counter value in the high level window of the TSC for synchronization.
The multiprocessor system provided by the embodiment of the present invention is improved based on fig. 3, and as shown in fig. 4, is a large system TSC _ SYNC pin interconnection scheme according to an embodiment of this patent scheme, and the system is a 32P XNC system, wherein the XNC system is a system that interconnects CPUs using an NC chip, the system includes 4 frame 8P sub-server systems, each 8P sub-server system uses a middle backplane, two management boards (PBI boards) and 8 BPN boards, each BPN board includes a CPU, the spurious board is used for interconnection of system spurious signals, and the high-speed links are interconnected by NI links from the NC chip.
Referring to fig. 4, two hardware channels for synchronization signals are reserved in the system. One hardware channel is a 1-drive-8 hardware channel, as shown by a hardware connecting line between two PBI boards in the figure; the other is a 1-drive-4 hardware channel, which is crossed on the signal backplane, as shown by the dotted line between the two PBI board logic devices in the figure.
The 4 CPUs or 8 CPUs are connected through analog switches, and are connected to a logic device after passing through a switch (switch), the switch of the present scheme may use LSF0108 or GTL2003, and the logic device includes but is not limited to a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA); the logic device in the stray board replaces the original analog switch, and can play the roles of enhancing the driving and time synchronization. The logic devices in the PBI board serve two primary functions: (1) receiving a TSC _ SYNC signal sent by a stray board; (2) a pair of crosswires (shown in dashed lines) is used as the reserved 1-drive 4-channel.
Stray signals between the PBI board and the stray board are set to be LVCMOS output for the stray board, wherein the LVCMOS output is of a level type, the driving is stronger compared with a drain open circuit output level type, the time delay can be reduced, the GPIO of the PCH is set to be output, signals output by the GPIO pins are connected with the logic device of the stray board through logic devices, and the signals are set to be input compared with the stray board.
In the process of hot insertion of the CPU, the BIOS code synchronizes the hot-inserted CPU with the TSC clock domain of the CPU which normally works, and calibrates the values of the TSC counters of all the slave CPUs in the system with the value of the counter of the master CPU, and the detailed steps of TSC synchronization realization are as follows, because of the difference of IVB-EX and HSW-EX in synchronous signal processing, which are respectively described as follows:
Fig. 5 is a signal flow diagram of a clock synchronization method according to an embodiment of the present invention, in an IVB-EX synchronization scheme of the embodiment, for a case that TSC _ SYNC defaults to a low level and synchronization is performed when TSC _ SYNC is a high level, the following clock synchronization method is adopted:
step 501, after the slave CPU is hot plugged, the BIOS of the master CPU runs to the TSC synchronization stage.
the method can be used as a program to be mounted under a main CPU, and one main CPU is appointed in a plurality of CPUs contained in the multiprocessor system.
at step 502, BIOS enables the TSC _ SYNC pin from CPU0 to CPU31 via the PCODE command.
At this time, all logic device output low levels keep the whole TSC bus low, and as the TSC output pin of the CPU is OpenDrain output and is used as an open-circuit output IO type, the output of all IO lines can be realized, and as long as one IO in the bus keeps a low level, the whole bus network can keep the low level.
In step 503, the GPIO of the PCH operated by the BIOS is low.
at step 504, the GPIO indicates that the TSC pins of all CPUs of the spur logic device have no longer been pulled to GND.
In step 505, the strake board logic device pulls the entire 16P/32P/64P TSC bus out a >10us high pulse on the 864BCLKs count clock falling edge of the strake board.
the value of the time length of the high pulse requires that the pulse length is greater than 1 clock cycle of the CPU lnalsync, and since the time length of 864BCLKs in condition 2 is 8.64us, 10us is selected here; after the CPU is pulled up, a TSC synchronization module in the CPU is enabled, and the PCODE code of the CPU carries out TSC synchronization at the moment.
In step 506, the CPU samples and stores the Snapshot value of the TSC Counter through the rising edge of the Internal Sync Clock after the TSC _ SYNC is valid.
in step 507, after the BIOS code delays the enabling state for 100ms, the TSC pins of all CPUs are pulled down, and the TSC pins of all CPUs are restored to the initial state.
In step 508, the BIOS reads the register values of all CPUs (including the main CPU) Snapshot (the instantaneous values of TSC COUNTER of all CPUs on the rising edge of Internal Sync CLOCK), calculates the Offset (Offset) values between all CPUs and the main CPU, and keeps the TSC COUNTER count value of the CPU operating with PCODE command consistent with the main CPU.
Fig. 6 is a schematic diagram of TSC synchronization waveforms according to an embodiment of the present invention, and referring to fig. 6, from a macroscopic point of view, the scheme is actually that a controllable high pulse is cut out from an original TSC _ SYNC synchronization waveform through BIOS control, and due to the addition of a device for enhancing driving, the high pulse has better signal integrity, i.e., more optimal delay and satisfactory signal edges and signal levels when transmitted in a large system.
Fig. 7 is a signal flow diagram of a clock synchronization method according to an embodiment of the present invention, in an HSW-EX synchronization scheme of the embodiment, TSC _ SYNC defaults to a high level, and synchronization is performed when TSC _ SYNC is a low level, where the method includes:
Step 701, after the slave CPU is hot plugged, the BIOS of the master CPU runs to the TSC synchronization stage.
Step 702, during TSC synchronization by the BIOS, the GPIO for PCH is operated at low level.
at step 703, the GPIO instructs the spur logic device system to initiate a TSC synchronization process.
at step 704, the CPLD triggers the entire 32P TSC bus to pull a 100us low pulse (HSW) using the falling edge of the 384BCLKs count clock.
This process is implemented in the stray board, and then the low pulse is sent to the logic devices of each PBI board of the system, and passed to all CPUs.
Step 705, the PCODE of the CPU automatically captures the value of TSC COUNT to the Snapshot register on the rising edge of the Internal Sync Clock.
in step 706, the BIOS reads the register values of all CPUs (including the main CPU) Snapshot (the instantaneous value of TSC COUNTER of all CPUs on the rising edge of Internal Sync CLOCK), calculates the Offset value between all CPUs and the main CPU, and uses the PCODE command to operate the TSC COUNTER value of the CPU to keep the TSC COUNTER value consistent with the main CPU.
Compared with the scheme of IVB-EX, the actual TSC _ SYNC waveform of the scheme has no temporal correlation compared with the original scheme.
By using the scheme to interconnect the TSC pins, the system after hot plug can work under the TSC clock, and the performance of the original system cannot be seriously reduced.
for all spurious signals encountered in large system design and requiring interconnection of all processors, which have a risk of signal integrity during the implementation process, the method can be implemented by using the thinking mode of the patent: the risky signal is divided into multiple domains while synchronization is performed using the synchronization signal.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It will be understood by those of ordinary skill in the art that all or part of the steps in the method for implementing the above embodiments may be implemented by a program which may be stored in a computer-readable storage medium, wherein the storage medium is a non-transitory (non-transitory) medium, such as a random access memory, a read only memory, a flash memory, a hard disk, a solid state drive, a magnetic tape (magnetic tape), a floppy disk (floppy disk), an optical disk (optical disk) and any combination thereof.
the above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for clock synchronization in a multiprocessor system, the multiprocessor system including a master processor and at least one slave processor, a TSC synchronization pin connecting the master processor and the slave processor via a TSC bus, the TSC bus having a first programmable logic device connected thereto, the method comprising:
when the master processor detects that the slave processors with hot insertion exist, if the TSC synchronous pins are high-level effective, the TSC synchronous pins of all the processors are enabled, and an indication signal is sent to the first programmable logic device, wherein the indication signal is used for indicating the first programmable logic device to generate a high pulse which is started from low level and is longer than a first preset time length on the falling edge of a first number of bus clocks; the first preset time length is more than 1 clock cycle of internal synchronization of the CPU;
after each slave processor in the master processor and the at least one slave processor detects that the high pulse reaches a TSC synchronous pin of the slave processor, sampling the count value of the TSC counter through the rising edge of an internal synchronous clock;
And according to the count value of the TSC counter sampled by each slave processor in the at least one slave processor and the count value of the TSC counter sampled by the master processor, enabling the count values of the TSC counters of the at least one slave processor and the master processor to be equal, and carrying out TSC clock synchronization.
2. The method of claim 1, wherein after the enabling TSC synchronization pins of all processors, the method further comprises:
and after the enabling state of the TSC synchronous pins of all the processors is kept for a certain time, pulling down the TSC synchronous pins of all the processors to restore the TSC synchronous pins of all the processors to the initial state.
3. the method of claim 1, wherein the method further comprises:
When the master processor detects that a slave processor which is hot-plugged exists, if the TSC synchronous pin is effective in low level, an indication signal is sent to the first programmable logic device, and the indication signal is used for indicating the first programmable logic device to generate a low pulse which is started from high level and is longer than a second preset time length on the falling edge of a second number of bus clocks; the second preset time length is 100 us;
After each slave processor in the master processor and the at least one slave processor detects that the low pulse reaches a TSC synchronous pin of the slave processor, sampling the count value of the TSC counter through the rising edge of an internal synchronous clock;
And according to the count value of the TSC counter sampled by each slave processor in the at least one slave processor and the count value of the TSC counter sampled by the master processor, enabling the count values of the TSC counters of the at least one slave processor and the master processor to be equal, and carrying out TSC clock synchronization.
4. The method of claim 1, 2 or 3, wherein said sending an indication signal to the first programmable logic device comprises:
and the general purpose input/output GPIO pin of the operation platform control hub PCH is in low level, and an indication signal is sent to the first programmable logic device through the low level output by the GPIO pin.
5. The method of claim 4, wherein a second programmable logic device is connected to the TSC bus; the sending an indication signal to the first programmable logic device includes:
and the general purpose input and output GPIO pin of the operation platform control hub PCH is in low level, the low level output by the GPIO pin is used for controlling the second programmable logic device to output low level, and the low level output by the second programmable logic device is used for sending an indication signal to the first programmable logic device.
6. A multiprocessor system, comprising a master processor and at least one slave processor, wherein TSC synchronization pins of the master processor and the slave processor are connected by a timestamp timer TSC bus, and wherein a first programmable logic device is connected to the TSC bus;
The master processor is used for enabling TSC synchronous pins of all processors and sending an indication signal to the first programmable logic device when the master processor detects that a slave processor with hot insertion exists, wherein the high level of the TSC synchronous pins is effective, and the indication signal is used for indicating the first programmable logic device to generate a high pulse which is started from low level and is longer than a first preset time length on the falling edge of a first number of bus clocks; the first preset time length is more than 1 clock cycle of internal synchronization of the CPU;
The master processor and each slave processor in the at least one slave processor are used for sampling the count value of the TSC counter through the rising edge of an internal synchronous clock after detecting that the high pulse reaches the TSC synchronous pin of the master processor and each slave processor in the at least one slave processor;
And each slave processor in the at least one slave processor is used for enabling the count value of the TSC counter of the slave processor and the count value of the TSC counter of the master processor to be equal according to the count value of the TSC counter sampled by the slave processor and the count value of the TSC counter sampled by the master processor, and carrying out TSC clock synchronization.
7. the system of claim 6, wherein the main processor is further configured to pull down the TSC sync pins of all processors to restore the TSC sync pins of all processors to an initial state after the enabling of the TSC sync pins of all processors has been maintained for a certain time.
8. The system of claim 6, wherein:
the master processor is further used for sending an indication signal to the first programmable logic device when the master processor detects that a slave processor with hot insertion exists, and if the TSC synchronization pin is effective in low level, the indication signal is used for indicating the first programmable logic device to generate a low pulse which starts from high level and is longer than a second preset time length on the falling edge of a second number of bus clocks; the second preset time length is 100 us;
the master processor and each slave processor in the at least one slave processor are further used for sampling the count value of the TSC counter through the rising edge of an internal synchronous clock after detecting that the low pulse reaches the TSC synchronous pin of the master processor and each slave processor in the at least one slave processor;
Each slave processor in the at least one slave processor is further configured to make the count value of the TSC counter of the slave processor and the count value of the TSC counter of the master processor equal to each other according to the count value of the TSC counter sampled by the slave processor and the count value of the TSC counter sampled by the master processor, and perform TSC clock synchronization.
9. The system of claim 6, 7 or 8, wherein the main processor, in particular a general purpose input output, GPIO, pin for operating a platform control hub, PCH, is low, and wherein an indication signal is sent to the first programmable logic device via the low output from the GPIO pin.
10. The system of claim 9, wherein a second programmable logic device is connected to the TSC bus; the main processor is specifically configured to operate a general purpose input/output GPIO pin of the platform control hub PCH to a low level, control the second programmable logic device to output the low level through the low level output by the GPIO pin, and send an indication signal to the first programmable logic device through the low level output by the second programmable logic device.
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| US10877919B2 (en) * | 2017-07-21 | 2020-12-29 | Integrated Device Technology, Inc. | Method to synchronize integrated circuits fulfilling functional safety requirements |
| CN109977069B (en) * | 2017-12-28 | 2021-04-20 | 华为技术有限公司 | A device |
| CN110308934B (en) * | 2018-03-22 | 2022-03-29 | 龙芯中科(成都)技术有限公司 | HPET driving method and device, readable storage medium and electronic equipment |
| CN109367569B (en) * | 2018-09-10 | 2021-03-12 | 广州大铁锐威科技有限公司 | Detection data synchronous acquisition system and method for measuring geometrical parameters of track |
| CN111158867B (en) * | 2018-11-07 | 2023-05-16 | 阿里巴巴集团控股有限公司 | Time synchronization processing method, thread scheduling method, device and electronic equipment |
| JP7439474B2 (en) * | 2019-11-25 | 2024-02-28 | 富士電機株式会社 | Programmable controller systems and modules |
| US11137794B2 (en) * | 2020-01-06 | 2021-10-05 | Woodward, Inc. | Systems and methods for synchronization of multiple processors |
| CN111258371B (en) * | 2020-01-08 | 2022-06-10 | 深圳市源拓光电技术有限公司 | Device, system and method for synchronizing counters among multiple FPGA chips |
| TWI782316B (en) * | 2020-08-24 | 2022-11-01 | 達明機器人股份有限公司 | Method for synchronizing process |
| CN112769518B (en) * | 2021-01-22 | 2022-09-13 | 上海宽域工业网络设备有限公司 | Serial port time sending system and method with second punctual edge |
| CN113204516A (en) * | 2021-04-26 | 2021-08-03 | 北京京东乾石科技有限公司 | Method and device for time synchronization of processors |
| CN113381831A (en) * | 2021-05-12 | 2021-09-10 | 聚融医疗科技(杭州)有限公司 | Multi-chip FPGA (field programmable Gate array) receiving and transmitting synchronization method and system and ultrasonic control equipment |
| CN113721703B (en) * | 2021-08-19 | 2024-02-13 | 飞腾信息技术有限公司 | Clock synchronization control device, system and control method in multi-path CPU system |
| CN113821469A (en) * | 2021-09-23 | 2021-12-21 | 深圳市元征科技股份有限公司 | Multiprocessor synchronization method, device, terminal equipment and storage medium |
| CN113835467B (en) * | 2021-09-26 | 2024-03-29 | 深圳市杰普特光电股份有限公司 | Clock synchronization system, method, electronic equipment and storage medium |
| CN117908354A (en) * | 2022-10-11 | 2024-04-19 | 比亚迪股份有限公司 | Time synchronization system, domain controller and vehicle |
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