CN101388741A - Highly precised time synchronization device, system and method for computer network - Google Patents

Abstract

The invention provides a high-accuracy time synchronizing apparatus, a method and a system for testing the computer network performance, monitoring system and network simulation, which comprises the following steps: utilizing a hardware circuit to realize a timestamp generating circuit, moving a timestamp recording position to a physical chain circuit layer, removing impact of the cache delay in the timestamp of a common software and impact caused by interrupting the response time delay, and realizing the accurate clock synchronization of each measuring node through the prediction-based time synchronous algorithm (Prediction-based Clock Synchronization,PCS). The apparatus improves the accuracy of the timestamp, can guarantee the error of the synchronous timestamp of each measured node not to exceed 100ns, and can reach the accuracy which is equal to adopting GPS synchronization, and the realization is simple and the cost is low.

Description

A kind of high-accuracy time synchronizing apparatus, system and method that is used for computer network

Technical field

The present invention relates to applications of computer network technical field, more specifically, the present invention relates to a kind of high-accuracy time synchronizing apparatus, system and method that is used for computer network.

Background technology

All the have relatively high expectations time synchronized of precision of distributed network system (DNS), computer network performance measurement and application such as test macro and network simulation.For example, when the transmission of packet in the computer network performance measurement, reception, it is network parameter based measurement such as time delay, bandwidth, shake that precise time stabs mark.In a multinode computer network measuring system, each nodal clock will have the degree of precision except self, also need the very high synchronization accuracy that keeps, otherwise network performance parameters such as the time-delay of calculating by time tolerance between comparison node, shake are with inaccurate.

Method for synchronizing time commonly used generally is the software clock method for synchronous, and common time protocol Network Based (Network Time Protocol, NTP).Node utilizes on Network Time Protocol and the network time server synchronous, wraps in round-trip delay on the network by the estimated data, computing node clock and time server clock jitter, thereby finish nodal clock and time server clock synchronously.NTP can obtain the 1ms synchronization accuracy under LAN environment, can obtain the 28.7ms synchronization accuracy under wan environment.Raising is to use Time Stamp Counter (Time Stamp Counter based on a way of Network Time Protocol clock synchronization accuracy, TSC), main flow CPU provides the TSC register, clock periodicity since its record main frame powers on, this precision is relevant with cpu frequency, and the TSC precision of the CPU of 1GHz is 1ns.NTP in conjunction with the TSC counter can bring up to precision the microsecond level synchronously.But this software approach is subjected to buffer delay uncertain and interrupt response time is uncertain influences, and is difficult to the precision that reaches higher.

Hardware clock simultaneous techniques SynUTC based on Ethernet utilizes hardware circuit to come generation time to stab, and synchronous error can reach 100ns.But SynUTC need revise the Ethernet fabric, and existing switch hardware must be made certain modification could support SynUTC, is difficult to apply on a large scale.

Also exist based on IEEE1588 chronometer time agreement (Precision Time Protocol, PTP) method for synchronizing time, the PTP agreement is the time synchronized standard of network measure and control system, according to the required precision of using, adopts software synchronization and two kinds of implementations of hardware synchronization.Hard-wired PTP synchronization accuracy can reach 233ns, but since synchrodata to wrap in switch or the router processing delay uncertain, cause the synchronized result instability.

(Global Position System, external clock reference GPS) can reach the synchronization accuracy of nanosecond to utilize global positioning system.But gps system costs an arm and a leg, and the gps antenna installation is inconvenient, causes the measured node deployed position limited.

Summary of the invention

The defective poor for the universality that overcomes time synchronized in the active computer network application, that precision is low, the present invention proposes a kind of high-accuracy time synchronizing apparatus, system and method that is used for computer network.

According to an aspect of the present invention, a kind of time synchronism equipment that is used for network system has been proposed, comprise, GTP transceiver, MAC controller, transceive data bag buffer queue and PCIe endpoint controller, it is characterized in that described time synchronism equipment also comprises one or more timestamp insert module and one or more PCS time stamp generator;

Wherein, described PCS time stamp generator is used for receiving and sending synchronizing clock signals, produces synchronized timestamp; Described timestamp insert module is connected with PCS time stamp generator, MAC controller and transceive data bag buffer queue respectively, described synchronized timestamp is inserted into the physical link layer of packet.

Wherein, described PCS time stamp generator is according to frequency preset control word and crystal oscillator clock signal, and output time stabs signal.

Wherein, described PCS time stamp generator receives synchronised clock input signal and crystal oscillator clock signal, and according to the frequency preset control word, generation time stabs signal and offers described timestamp insert module.

Wherein, described PCS time stamp generator comprises:

Direct synthesizer is used for stabbing signal according to reference clock signal and frequency control word generation time;

Time Stamp Counter comprises low counter and high-positioned counter, is used to receive described time stamp signal and described synchronizing clock signals or control signal, and output time stabs the timestamp insert module or is provided for the master clock timestamp.

Wherein, described timestamp insert module was inserted timestamp information before the packet that receives from described MAC controller outputs to the reception data packet queue; Data in the data packet queue were inserted timestamp information before sending to described MAC controller; Wherein, described timestamp information inserts the physical link layer of described packet.

According to a further aspect in the invention, a kind of clock synchronization system that is used for network system has been proposed, comprise a plurality of described time synchronism equipments, wherein, one of them of described a plurality of time synchronism equipments be as main equipment, described remaining time synchronism equipment as slave unit, described main equipment produces the synchronised clock output signal, described slave unit receives described synchronised clock output signal, realizes the time synchronized of system.

Wherein, the PCS time stamp generator of described main equipment is according to frequency preset control word and crystal oscillator clock signal, and output time stabs timestamp insert module and the described slave unit that signal is given described main equipment.

Wherein, described slave unit PCS time stamp generator receives described synchronised clock output signal and crystal oscillator clock signal, and according to the frequency preset control word, generation time stabs the timestamp insert module that signal offers slave unit.

According to another aspect of the invention, proposed a kind of method for synchronizing time that uses above-mentioned clock synchronization system, having comprised:

Step 10), slave unit receive the time synchronizing signal of main equipment, the current time of reading this slave unit;

Step 20), obtain time difference Δ t between reading for the third time and read for the second time and read for the second time and reading for the first time ₂With Δ t ₁

Step 30), obtain the frequency signal of reference clock, $f_{\mathrm{ref}}=\frac{f_{\mathrm{syn}}{2}^N}{K_{\mathrm{dds}}}=\frac{\mathrm{\&Delta;}{\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">t</figure-callout>}}_2\&times;2^{\mathrm{<figure-callout\; id="0"\; label="N\; K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">N</figure-callout>}}}{K_{\mathrm{dds}}^{}}$ , wherein, N is the FREQUENCY CONTROL word bit number,

Be the original frequency control word, upgrade described frequency control word, ${\mathrm{<figure-callout\; id="1"\; label="K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00162.png"\; state="\{\{state\}\}">K</figure-callout>}}_{\mathrm{dds}}^{}=\left(\frac{4\&times;2^m-(\mathrm{\&Delta;}{\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="A200810224891E00161.png,A200810224891E00162.png"\; state="\{\{state\}\}">t</figure-callout>}}_1+2\mathrm{\&Delta;}{t}_2)}{\mathrm{\&Delta;}{t}_2}\right)\&times;{\mathrm{<figure-callout\; id="0"\; label="K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">K</figure-callout>}}_{\mathrm{dds}}^{}$ , wherein m is the timestamp precision;

Step 40), pass through frequency control word

Adjust the clock frequency of slave unit, and calculate the frequency control word that upgrades

${\mathrm{<figure-callout\; id="2"\; label="K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">K</figure-callout>}}_{\mathrm{dds}}^{}=\frac{2^m\&times;{\mathrm{<figure-callout\; id="0"\; label="K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">K</figure-callout>}}_{\mathrm{dds}}^{}}{\mathrm{\&Delta;}{\mathrm{<figure-callout\; id="3"\; label="t"\; filenames="A200810224891E00182.png"\; state="\{\{state\}\}">t</figure-callout>}}_3}$ , use described frequency control word

Adjust the slave unit clock frequency, realize the synchronous of system.

Wherein, described method also comprises:

Step 50), calculate the double time difference Δ t that slave unit reads main equipment _i=T _i-T _I-1Obtain the error e in reading for twice ⁰(i) and e ¹(i), $e^0\left(i\right)=2^m-\frac{\mathrm{\&Delta;}{t}_i\&times;K_{\mathrm{dds}}^i}{K_{\mathrm{dss}}^{i-1}},$ e ¹(i)=2 ^m-Δ t _i, the calculated rate control word

$K_{\mathrm{dds}}^{i+1}=\frac{2^m+e^0\left(i\right)+e^1\left(i\right)}{\mathrm{\&Delta;}{t}_i}\&times;K_{\mathrm{dds}}^{i-1},$ By

Adjust the clock frequency of slave unit.

The present invention utilizes hardware circuit to realize timestamp being write down timestamp the position move on to physical link layer, has eliminated buffer delay in the common software timestamp and interrupt response time and has postponed the influence that brings; (Prediction-based Clock Synchronization PCS) has realized that the precision clock of each measured node is synchronous by the time synchronized algorithm based on prediction; The present invention has improved the timestamp precision, can guarantee that each measured node synchronized timestamp error is no more than 100ns, reaches and the precision that adopts the GPS locking phase to work as.

Description of drawings

Fig. 1 is split-second precision synchronization scenario schematic diagram according to an embodiment of the invention;

Fig. 2 receives the schematic diagram that can add the timestamp position in the scene for tradition;

Fig. 3 is two card timestamp deviation schematic diagrames when not adopting the PCS synchronized algorithm;

Fig. 4 is every card neighbouring sample packet interval of timestamps schematic diagram among Fig. 3;

Fig. 5 is clock synchronization system structural representation according to an embodiment of the invention;

Fig. 6 produces circuit diagram for hardware timestamping according to an embodiment of the invention;

Fig. 7 inserts circuit diagram for timestamp according to an embodiment of the invention;

Fig. 8 is the time synchronized algorithm PCS sequential chart based on prediction of the present invention;

Fig. 9 is the time synchronized algorithm PCS flow chart based on prediction of the present invention;

Figure 10 is verification environment schematic diagram according to an embodiment of the invention;

Figure 11 is two hours of two card timestamp deviations adopting PCS synchronized algorithm figure as a result;

Figure 12 is 12 hours of two card timestamp deviations adopting PCS synchronized algorithm figure as a result;

Figure 13 is a PCS algorithm predicts error schematic diagram.

Embodiment

Below in conjunction with the drawings and specific embodiments a kind of high-accuracy time synchronizing apparatus, system and method that is used for computer network provided by the invention is described in detail.

Fig. 1 illustrates the synchronous overall plan of split-second precision according to an embodiment of the invention, as shown in Figure 1, at first utilize hardware circuit (such as similar structures such as FPGA, PLA) to realize the timestamp generative circuit, the rise time synchronizer, timestamp is write down the position move on to physical link layer, eliminate buffer delay in the common software approach timestamp and interrupt response time and postpone the influence that brings; Each synchronizer is connected to each other, set a main synchronizer, need synchronous equipment to be connected to form clock synchronization system all, (Prediction-based ClockSynchronization PCS) realizes the clock precise synchronization of each node device to use time synchronized algorithm based on prediction in this clock synchronization system.In the present embodiment, make up the timestamp generative circuit by FPGA, similarly, describe based on following principle to the timestamp generative circuit, the timestamp generative circuit also can use PLA, ASIC or other integrated circuits to realize.In the present embodiment, when using timestamp generative circuit structure clock synchronization system, utilize RS422 to connect synchronizer, similarly, the present invention also can use known such as other interconnection techniques such as RS484, RS232 or USB, PCI.In the time synchronized system that makes up, use described PCS method for synchronizing time, realize the high-precise synchronization of institute's connection device.

Fig. 2 receives the position view that adds timestamp in the scene for network packet, receive in the scene at legacy network interface card packet, packet in the user's space territory arrives network interface unit based on concrete application program, network interface unit is transferred to host memory with packet according to procotol (such as TCP/IP), by the packet that interrupts notifying driver handles to receive.Response of host interrupts, and copies the packet of receiving to the upper-layer protocol stack and handles, and the packet after the processing finally arrives application program.As shown in Figure 2, in this process, timestamp can add in a plurality of positions: media interviews control (Media Access Control, MAC) layer, Drive Layer and application layer.It is different that the diverse location joining day is stabbed the influence that postponed by buffer delay and interrupt response time, it is also different that timestamp and packet arrive the deviation of actual time, wherein, take second place in the influenced minimum of MAC layer, Drive Layer, application layer is suffered has the greatest impact; Difference is at Millisecond.This deviation of definition is the timestamp additive error in the embodiments of the invention.

Fig. 3 is the timestamp deviation schematic diagram that crystal oscillator produced with same nominal frequency, and the clock that generation time stabs is subjected to crystal oscillator shake and drift to influence its speed instability, thereby the timestamp of generation also can have deviation in time.

Fig. 4 is a neighbouring sample packet interval of timestamps schematic diagram among Fig. 3, and the two is to stab deviation by same nominal value crystal oscillator institute generation time.Thus, the deviation that definition is caused by the crystal oscillator instability among the present invention is the error of timestamp own.So the timestamp error that defines in the embodiments of the invention is made up of error of timestamp own and timestamp additive error, improves timing tracking accuracy and need set about from reducing error of timestamp own and additive error.

In the embodiments of the invention, timestamp is write down the position move on to physical link layer, by hardware circuit timestamp is joined in the application system, Fig. 5 is the timestamp synchronizer structure chart of the specific embodiment according to the present invention.Owing to stab with regard to the joining day after packet leaves MAC, the feasible influencing factor that can get rid of various software delays in the timestamp additive error is brought up to nanosecond with the timestamp precision.

In the present embodiment, this circuitry structure realizes based on FPGA, this circuit structure can be applied in the network interface card or in other network measure equipment.

As shown in Figure 5, this time synchronism equipment comprises GTP transceiver, MAC controller, transceive data bag buffer queue (reception data packet queue among the figure and transmission data packet queue) and PCIe endpoint controller.The synchronised clock input and output directly link to each other with MAC controller by transceive data bag buffer queue in the existing equipment, control by software approach and realize synchronously.In the present embodiment, this time synchronized system, device also comprises one or more timestamp insert module and one or more PCS time stamp generator, wherein, the PCS time stamp generator receives and sends synchronised clock, receive the control signal of packet handler, be connected with the timestamp insert module, control time is stabbed insert module, the timestamp insert module is connected with PCS time stamp generator, MAC controller, packet handler and transceive data bag buffer queue respectively, timestamp is inserted into the physical link layer of network data.In the present embodiment, two timestamp insert modules shown in the figure, the present invention can use a timestamp insert module.

Need each synchronous parts by the input of the synchronised clock shown in Fig. 5, output interconnection (can be any type of serial input or other known connected mode on the physical connection), the clock signal that the PCS time stamp generator produces (for example is input to the timestamp insert module, the content of transfer of data is the timestamp information of 64 bits), in the timestamp insert module, clock signal is inserted in the network packet that receives or send.

Fig. 6 illustrates the detailed circuit of the PCS time stamp generator shown in Fig. 5, and as shown in Figure 6, the core of described generator is a direct synthesizer, and the control word adjustment generates clock frequency by adjusting frequency.In the present embodiment, the timestamp register is 64bit altogether, and high 32bit value representative is hanged down the 32bit value representation mark of second since 0 second number in morning on January 1st, 1970.The highest resolution that this expression mode can reach is 2 ^-32S, i.e. 233ps, and, by with low ^32-mBit is set to 0, can obtain resolution to be ^2-mThe clock of s.The high 32bit of timestamp register counts initial value second and is write by main frame when the initialization by driver, therefore requires the main frame time to have a second class precision, and this can conveniently realize by Network Time Protocol; Low 32bit fractional part second is produced by internal counter, and counter is counted under direct synthesizer output clock frequency fsyn, and the full back of meter produces carry signal, and high 32bit count value adds 1.

As shown in Figure 6, each parts links to each other by data wire, and wherein reference clock is the clock that external crystal-controlled oscillation shown in Figure 5 is imported, and frequency control word is that frequency preset is regulated parameter; The output valve of direct synthesizer is deposited in the timestamp low counter; The carry signal of timestamp low counter is input in the high bit register of timestamp, and when node is host node, this carry signal also will produce output pulse signal and offer from node; The value of the low bit register of high bit register of timestamp and timestamp is sent to the timestamp insert module; When node is during from node, the input pulse that utilizes host node to provide produces interrupt signal, and notice drives and reads the value that the current time stabs register.

Fig. 7 illustrates the detailed circuit of timestamp insert module shown in Figure 5, as shown in Figure 7, the packet that receives is deposited earlier in the register, inserts present clock information (the present clock value is produced by hardware timestamping generative circuit shown in Figure 6) then before this packet outputs to the reception data packet queue; The data that send in the data packet queue were also deposited earlier in the register before sending, and sent to MAC behind the insertion present clock; Wherein, data clock information is inserted the physical link layer of data.

In another embodiment of the present invention, the present invention proposes a kind of clock synchronization system, comprise a plurality of above-mentioned time synchronism equipments, wherein, one of them of a plurality of time synchronism equipments produces the synchronised clock output signal as main equipment, described remaining time synchronism equipment as slave unit, receive the synchronised clock output signal that main equipment sends,, realize the time synchronized of system through the time stamp generator of this equipment and the respective handling of timestamp insert module.All slave units are interconnected with this main synchronizer or link to each other respectively, constitute clock synchronization system, and described connected mode includes but not limited to RS484, RS232, RS422 and USB.The PCS time stamp generator of main equipment is according to frequency preset control word and crystal oscillator clock signal, and output time stabs timestamp insert module and the described slave unit that signal is given described main equipment.Slave unit PCS time stamp generator receives described synchronised clock output signal and crystal oscillator clock signal, and according to the frequency preset control word, generation time stabs the timestamp insert module that signal offers this equipment.

A kind of clock synchronization algorithm (Prediction-based ClockSynchronization based on prediction has also been proposed among the present invention, PCS) finish a plurality of internodal clock synchronizations by said system, need specify a host node to send reference clock when multinode is synchronous, the node synchronous with host node is called from node, the appointment of main and subordinate node is decided according to application demand, without any added limitations, interconnect by asynchronous serial bus between main and subordinate node.In the time of synchronously host node every pulse of 1s output to respectively from node, receive pulse from node after, time for reading is stabbed register, measures one second result, adjusts the DDS frequency control word and expects next second synchronism deviation minimum.Sequential schematic diagram of the present invention as shown in Figure 8, the present invention is divided into and starts and synchronous two stages.

The startup stage:

The 0th step started from node, after the pulse per second (PPS) that receives host node output from node PCS time stamp generator, read current time T from Time Stamp Counter ₀, produce the driving of interrupt signal notice simultaneously and read this value;

In the 1st step, after the pulse per second (PPS) that receives host node output from node PCS time stamp generator once more, from Time Stamp Counter, read current time T ₁, produce interrupt signal notice simultaneously and drive and read this value, drive the time value of utilizing the 0th step and the 1st step to read and calculate the 0th and go on foot and the 1st time difference Δ t between going on foot ₁=T ₁-T ₀

In the 2nd step, after the pulse per second (PPS) that receives host node output from node PCS time stamp generator for the 3rd time, from Time Stamp Counter, read current time T ₂, produce interrupt signal notice simultaneously and drive and read this value, drive the time value of utilizing the 1st step and the 2nd step to read and calculate the 1st and go on foot and the 2nd time difference Δ t between going on foot ₂=T ₂-T ₁, and the formula below utilizing calculates the actual frequency of reference clock (crystal oscillator output);

$f_{\mathrm{ref}}=\frac{f_{\mathrm{syn}}{2}^N}{K_{\mathrm{dds}}}=\frac{\mathrm{\&Delta;}{\mathrm{<figure-callout\; id="2"\; label="t"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">t</figure-callout>}}_2\&times;2^{\mathrm{<figure-callout\; id="0"\; label="N\; K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">N</figure-callout>}}}{K_{\mathrm{dds}}^{}}$ , wherein N is the FREQUENCY CONTROL word bit number, the present embodiment intermediate value is 32;

Be the original frequency control word, the present embodiment intermediate value is 0xABCC7712; The formula that drives below utilizing calculates new frequency control word

${\mathrm{<figure-callout\; id="1"\; label="K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00162.png"\; state="\{\{state\}\}">K</figure-callout>}}_{\mathrm{dds}}^{}=\left(\frac{4\&times;2^m-(\mathrm{\&Delta;}{\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="A200810224891E00161.png,A200810224891E00162.png"\; state="\{\{state\}\}">t</figure-callout>}}_1+2\mathrm{\&Delta;}{t}_2)}{\mathrm{\&Delta;}{t}_2}\right)\&times;{\mathrm{<figure-callout\; id="0"\; label="K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">K</figure-callout>}}_{\mathrm{dds}}^{}$ , wherein m is the timestamp precision, the present embodiment intermediate value is 24;

In the 3rd step, after the pulse per second (PPS) that receives host node output from node PCS time stamp generator the 4th, from Time Stamp Counter, read current time T ₃, produce interrupt signal notice simultaneously and drive and read this value, drive the time value of utilizing the 2nd step and the 3rd step to read and calculate the 2nd and go on foot and the 3rd time difference Δ t between going on foot ₃=T ₃-T ₂Use the frequency control word that calculates the 2nd step from node PCS time stamp generator Adjust clock frequency, and calculate new frequency control word by the formula that drives below utilizing

${\mathrm{<figure-callout\; id="2"\; label="K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">K</figure-callout>}}_{\mathrm{dds}}^{}=\frac{2^m\&times;{\mathrm{<figure-callout\; id="0"\; label="K\; dds"\; filenames="A200810224891E00161.png,A200810224891E00182.png"\; state="\{\{state\}\}">K</figure-callout>}}_{\mathrm{dds}}^{}}{\mathrm{\&Delta;}{\mathrm{<figure-callout\; id="3"\; label="t"\; filenames="A200810224891E00182.png"\; state="\{\{state\}\}">t</figure-callout>}}_3}$

In the 4th step, after the pulse per second (PPS) that receives host node output from node PCS time stamp generator the 5th, from Time Stamp Counter, read current time T ₄, produce the driving of interrupt signal notice simultaneously and read this value, use the frequency control word that calculates the 3rd step from node PCS time stamp generator

Adjust clock frequency, and calculate new frequency control word by driving the formula that utilizes top the 3rd step

So far, finish the startup stage.

B. synchronous phase:

Through the startup stage 4 steps whole after, synchronous from nodal clock and host node clock, but consider the unsteadiness of clock crystal oscillator, need continuous frequency of amendment control word from node, thereby keep long-term synchronous with host node;

1. after the pulse per second (PPS) that receives host node output from node PCS time stamp generator, from Time Stamp Counter, read current time T _i, produce the driving of interrupt signal notice simultaneously and read this value, drive and calculate the time difference Δ t that interrupts continuously for twice _i=T _i-T _I-1

2. drive and calculate first two steps predicated error e ⁰(i) and e ¹(i):

$e^0\left(i\right)=2^m-\frac{\mathrm{\&Delta;}{t}_i\&times;K_{\mathrm{dds}}^i}{K_{\mathrm{dss}}^{i-1}}$

e ¹(i)=2 ^m-Δ t _i, the computing formula that is not limited to provide in the present embodiment when calculating predicated error, the variable implication is ditto described in the formula; 3. use the frequency control word that last cycle calculations goes out from node PCS time stamp generator

, drive and calculate next step frequency control word

$K_{\mathrm{dds}}^{i+1}=\frac{2^m+e^0\left(i\right)+e^1\left(i\right)}{\mathrm{\&Delta;}{t}_i}\&times;K_{\mathrm{dds}}^{i-1},$

Different frequency control words can make the clock frequency difference that direct synthesizer is synthesized among Fig. 6, if find from node host node in twice pulse spacing the time walked soon, need so the frequency control word from node is turned down, otherwise, transfer big.By continuous adjustment, can guarantee to reach unanimity from nodal clock and host node clock.

When carrying out the synchronous and synchronism detection of concrete equipment, the equipment that needs are synchronous utilizes asynchronous serial connecting line interconnection (for example RS422) according to shown in Figure 10.Figure 10 is in order to verify the experimental situation of performance of the present invention, network tester adopts Spirent company's T estCenter, utilize its gigabit module to send test packet, by optical splitter one road flow is divided into the two-way same traffic, be connected to two test nodes through isometric optical patchcord, it is constantly identical that packet arrives two test nodes.Two test nodes are installed on the high-performance server respectively.Mounting strap has two network interface cards of described synchronizer, starts the driven in synchronism method, and utilizes RS422 to connect two network interface cards and can carry out synchronously or test.

Figure 11 is two hours results of two card timestamp deviations adopting the PCS synchronized algorithm, and wherein abscissa is the Measuring Time point, and ordinate is two card timestamp deviations (unit is nanosecond), and from the result as seen, the timestamp deviation is between-50ns～180ns.Figure 12 is for adopting two 12 hours statisticses of blocking the timestamp deviations of PCS synchronized algorithm, wherein abscissa is the timestamp deviation, the frequency that ordinate occurs for this deviation, from the result as seen, the PCS algorithm has been finished the synchronous of two equipment well by the control word of adjusting frequency, and the most of the time is stabbed Deviation Control within 0～100ns.Figure 13 has shown the predicated error of PCS algorithm, and wherein abscissa is the Measuring Time point, ordinate be two the card timestamp deviations (unit is nanosecond), from the visible predicated error of result mainly be distributed in-50ns～50ns within.

It should be noted that at last, above embodiment is only in order to describe technical scheme of the present invention rather than the present technique method is limited, the present invention can extend to other modification, variation, application and embodiment on using, and therefore thinks that all such modifications, variation, application, embodiment are in spirit of the present invention and teachings.

Claims (10)

1, a kind of time synchronism equipment that is used for network system, comprise, GTP transceiver, MAC controller, transceive data bag buffer queue and PCIe endpoint controller, it is characterized in that described time synchronism equipment also comprises one or more timestamp insert module and one or more PCS time stamp generator;

Wherein, described PCS time stamp generator is used to produce synchronized timestamp; Described timestamp insert module is connected with PCS time stamp generator, MAC controller and transceive data bag buffer queue respectively, described synchronized timestamp is inserted into the physical link layer of packet.

2, the time synchronism equipment of claim 1, described PCS time stamp generator are used for receiving and sending synchronizing clock signals according to frequency preset control word and crystal oscillator clock signal, and wherein, described synchronizing clock signals comprises time stamp signal.

3, the time synchronism equipment of claim 1, described PCS time stamp generator receives synchronised clock input signal and crystal oscillator clock signal, and according to the frequency preset control word, generation time stabs signal and offers described timestamp insert module.

4, the time synchronism equipment of claim 1, described PCS time stamp generator comprises:

Direct synthesizer is used for stabbing signal according to reference clock signal and frequency control word generation time;

Time Stamp Counter comprises low counter and high-positioned counter, is used to receive described time stamp signal and described synchronizing clock signals or control signal, and output time stabs the timestamp insert module or is provided for the master clock timestamp.

5, the time synchronism equipment of claim 1, described timestamp insert module was inserted timestamp information before the packet that receives from described MAC controller outputs to the reception data packet queue; Data in the data packet queue were inserted timestamp information before sending to described MAC controller; Wherein, described timestamp information inserts the physical link layer of described packet.

6, a kind of clock synchronization system that is used for network system, any one the described time synchronism equipment that comprises a plurality of claims 1 to 5, wherein, one of them of described a plurality of time synchronism equipments is as main equipment, described remaining time synchronism equipment is as slave unit, described main equipment produces the synchronised clock output signal, and described remaining slave unit receives described synchronised clock output signal, realizes the time synchronized of system.

7, the clock synchronization system of claim 6, wherein, the PCS time stamp generator of described main equipment is according to frequency preset control word and crystal oscillator clock signal, and output time stabs timestamp insert module and the described slave unit that signal is given described main equipment.

8, the clock synchronization system of claim 6, wherein, described slave unit PCS time stamp generator receives described synchronised clock output signal and crystal oscillator clock signal, and according to the frequency preset control word, generation time stabs the timestamp insert module that signal offers slave unit.

9, a kind of method for synchronizing time that is used in the described clock synchronization system of claim 6 comprises:

Step 10), slave unit receive the time synchronizing signal of main equipment, the current time of reading this slave unit;

Step 20), obtain time difference Δ t between reading for the third time and read for the second time and read for the second time and reading for the first time ₂With Δ t ₁

Step 30), obtain the frequency signal of reference clock, $f_{\mathrm{ref}}=\frac{f_{\mathrm{syn}}{2}^N}{K_{\mathrm{dds}}}=\frac{{\mathrm{\&Delta;t}}_2\&times;2^N}{K_{\mathrm{dds}}^0},$ Wherein, N is the FREQUENCY CONTROL word bit number,

Be the original frequency control word, upgrade described frequency control word, $K_{\mathrm{dds}}^1=\left(\frac{4\&times;2^m-({\mathrm{\&Delta;t}}_1+{2\mathrm{\&Delta;t}}_2)}{{\mathrm{\&Delta;t}}_2}\right)\&times;K_{\mathrm{dds}}^0,$ Wherein m is the timestamp precision;

Step 40), pass through frequency control word

Adjust the clock frequency of slave unit, and calculate the frequency control word that upgrades

$K_{\mathrm{dds}}^2=\frac{2^m\&times;K_{\mathrm{dds}}^0}{{\mathrm{\&Delta;t}}_3},$ Use described frequency control word Adjust the slave unit clock frequency, realize the synchronous of system.

10, the method for claim 9, wherein, described method also comprises:

Step 50), calculate the double time difference Δ t that slave unit reads main equipment _i=T _i-T _I-1Obtain the error e in reading for twice ⁰(i) and e ¹(i), $e^0\left(i\right)=2^m-\frac{{\mathrm{\&Delta;t}}_i\&times;K_{\mathrm{dds}}^i}{K_{\mathrm{dds}}^{i-1}},$ e ¹(i)=2 ^m-Δ t ₁, the calculated rate control word $K_{\mathrm{dds}}^{i+1}=\frac{2^m+e^0\left(i\right)+e^1\left(i\right)}{{\mathrm{\&Delta;t}}_i}\&times;K_{\mathrm{dds}}^{i-1},$ By

Adjust the clock frequency of slave unit.

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