CN109150355A - System for realizing PTP network card under FPGA - Google Patents
System for realizing PTP network card under FPGA Download PDFInfo
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- CN109150355A CN109150355A CN201810923439.XA CN201810923439A CN109150355A CN 109150355 A CN109150355 A CN 109150355A CN 201810923439 A CN201810923439 A CN 201810923439A CN 109150355 A CN109150355 A CN 109150355A
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- 238000012545 processing Methods 0.000 claims abstract description 20
- 108700009949 PTP protocol Proteins 0.000 claims abstract description 7
- 230000000630 rising effect Effects 0.000 claims description 4
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 5
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 230000006870 function Effects 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000306 recurrent effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 235000007926 Craterellus fallax Nutrition 0.000 description 1
- 240000007175 Datura inoxia Species 0.000 description 1
- 101100126329 Mus musculus Islr2 gene Proteins 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention provides a system for realizing PTP network card under FPGA, comprising: an input module for receiving an ethernet data stream; the processing module is used for processing Ethernet data flow PCIe data flow and IEEE1588 protocol message; and the output module is used for providing the Ethernet data stream, the timestamp of IEEE1588 and a related control register to a user through a PCIe bus, and the user realizes network card drive, TCP/IP and PTP protocol stack in an operating system. The invention designs the multifunctional board card integrating data transmission, time synchronization and frequency synchronization, and can meet various time synchronization application scenes and services; the PCIe network card is realized through the FPGA chip, and a special network card chip is expected to be partially replaced, so that the cost is reduced.
Description
Technical field
The present invention relates to the systems that PTP network interface card is realized under network communicating system field more particularly to a kind of FPGA.
Background technique
The full name of IEEEl588 is " the precision interval clock synchronous protocol standard of network measure and control system ", abbreviation PTP
(Precision Time Protoc01).The typical field of application of PTP is measurement and control system, industrial automation, power train
System and Distributed Motion Control System.Time unification is distributed across the equipment of different location and the basis of system synergistic working.
Network Time Protocol clock synchronization precision synchronous with SNTP agreement can only reach tens milliseconds and be even lower than tens milliseconds, it is remote
Far from the needs for meeting present network, therefore need the higher standard of hunting time precision just to solve the problems, such as this.
The formulation of IEEE1588 standard is the time synchronization problem in order to solve some equipment in industrial circle, which has performance
More excellent synchronization accuracy.
The present invention is realized using the design method that the IP kernel of Xilinx IEEE1588, Ethernet and PCIE interface combine
PCIE time synchronization PTP network interface card, the function of horn of plenty board and professional, also support 1PPS output and input, recurrent pulses
It outputs and inputs, the application scenarios for clock synchronization performance test and Frequency Synchronization.
Summary of the invention
For the defects in the prior art and upper demand is applied, the technical problem to be solved in the present invention is embodied in following several
Point: PTP time synchronization board is utilized, provides the high-precision clock synchronization of Microsecond grade error for user；PTP time synchronization board props up simultaneously
Hold transmission services data and PTP time adjustment function；PTP synchronization board provides recurrent pulses for Frequency Synchronization and outputs and inputs function
Energy.
The present invention is realized according to following technical scheme:
The system for realizing PTP network interface card using FPGA characterized by comprising
Input module, for receiving ethernet data stream；
Processing module, for Ethernet data circulation PCIe data stream and the processing of IEEE1588 protocol massages；
Output module, by PCIe bus by the timestamp and associated control registers of ethernet data stream and IEEE1588
It is supplied to user, user realizes trawl performance, TCP/IP and PTP protocol stack in operating system.
In above-mentioned technical proposal, the input module includes that RJ45 interface and physical interface transceiver (PHY) support 10/
100/1000Mb traffic rate intervenes controller (MAC) IP kernel with the Ethernet media of FPGA by Media Independent Interface and is connected,
For receiving and dispatching the physical link of message.
In above-mentioned technical proposal, the processing module includes:
Business data processing module, by the data flow cache of Media Independent Interface or gigabit ethernet interface into circulation team
Tail portion is arranged, PCIe is deposited into PCIe data space, CPU read data transfer upper-layer protocol stack from queue head access evidence；
IEEE1588 clock synchronization module generates for PTP packet check function and hardware timestamping and the time adjusts, wherein
PTP packet check is scanning and correct identification IEEE1588 from the data flow of Media Independent Interface or gigabit ethernet interface
Message, be submitted to upper layer PTP protocol stack processing；The hardware timestamping, which refers to, to be added between MAC layer and PHY to PTP message
Timestamp field effectively eliminates the delay and jitter of protocol stack, reflects the IEEE1588 message practical time sent and received；When
Between adjustment to be current network interface card update the local time according to the time deviation of link Round-Trip delay and PTP server.
Frequency clock synchronization module, the precise time generated using IEEE1588 clock synchronization module is come the input of control wave
And output, the 32 bit nanosecond count values that PTP network interface card is exported according to hardware timestamping export control command to choosing by comparator
Select device, thus export pulse per second (PPS) (1PPS) signal, cyclic pulse signal (Period [1:0]) and trigger signal (Triger [1:
0]).External input 1PPS pulse and event signal (Event [1:0]) are triggered by the rising edge of level to interrupt, then will be in this
The MSI interrupt processing of the IP kernel of PCIe is passed in stealpass.
By adopting the above-described technical solution, compared with prior art, the present invention have it is following the utility model has the advantages that
The present invention designs the multi-functional board of collective data transmission, time synchronization and Frequency Synchronization, can satisfy a variety of
Time synchronization application scenarios and business；The present invention realizes PCIe network interface card by fpga chip, is expected to part and substitutes professional network interface card core
Piece reduces cost.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the system architecture block diagram that PTP network interface card is realized under a kind of FPGA of the invention.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
Such as Fig. 1, the invention proposes the system for realizing PTP network interface card under a kind of FPGA, PTP report in selective analysis this programme
The principle of literary detection module and hardware timestamping module beats timestamp at the gmii interface between MAC and PHY and eliminates agreement
The delay and jitter of stack, greatly improves synchronization accuracy；The resolution ratio of the hardware timestamping is 10ns, therefore using the present invention
Design scheme the synchronization accuracy of nanosecond may be implemented.Its system includes:
Input module, for receiving ethernet data stream；
Processing module, for Ethernet data circulation PCIe data stream and the processing of IEEE1588 protocol massages；
Output module, by PCIe bus by the timestamp and associated control registers of ethernet data stream and IEEE1588
It is supplied to user, user realizes trawl performance, TCP/IP and PTP protocol stack in operating system.
The input module includes RJ45 interface and the PHY chip of 10/100/1000Mb, is independently connect by media
Mouth (MII interface) or gigabit ethernet interface (gmii interface) are connected with the MAC layer IP kernel of FPGA, for receiving and dispatching the object of message
Manage link.
In specific embodiments of the present invention, the processing module includes:
Business data processing module, by the data flow cache of Media Independent Interface or gigabit ethernet interface into circulation team
Tail portion is arranged, PCIe is deposited into PCIe data space, CPU read data transfer upper-layer protocol stack from queue head access evidence；
IEEE1588 clock synchronization module generates for PTP packet check function and hardware timestamping and the time adjusts, wherein
PTP packet check is scanning and correct identification IEEE1588 from the data flow of Media Independent Interface or gigabit ethernet interface
Message, be submitted to upper layer PTP protocol stack processing；The hardware timestamping, which refers to, to be added between MAC layer and PHY to PTP message
Timestamp field effectively eliminates the delay and jitter of protocol stack, reflects the IEEE1588 message practical time sent and received；
Frequency clock synchronization module, the precise time generated using IEEE1588 clock synchronization module come the input of control wave and
Output, the 32 bit nanosecond count values that PTP network interface card export according to timestamp pass through comparator and export control command to selector, from
And pulse per second (PPS) (1PPS) signal, cyclic pulse signal (Period [1:0]) and trigger signal (Triger [1:0]) are exported, outside
Portion inputs 1PPS pulse and event signal (Event [1:0]) and triggers interruption by the rising edge of level, then transmits the interruption
To the MSI interrupt processing of the IP kernel of PCIe.
Furthermore the counter works frequency of network interface card timestamp module is higher, and the resolution ratio of network interface card timestamp is higher, still
In practical projects, this frequency is limited by the performance of FPGA device itself and local crystal oscillator, it is impossible to unconfined raising,
Otherwise net synchronization capability cannot be not only improved, or even this frequency can also be not achieved because of system and cisco unity malfunction.The present invention
Clock signal of the 100Mhz as network interface card time counter is multiplied to using DCM of the 50Mhz crystal oscillator access FPGA inside.?
The rising edge of each clock is cumulative, and each accumulated value is 10ns, that is, the resolution ratio of network interface card timestamp is 10ns.It starts power up
When, timestamp module needs initial time, the write time time stamp deposit that is issued renewal time order by CPU and will be updated
Device, counter start to update the network interface card time, then start to add up on this basis.When CPU issues adjustment local zone time order,
Timestamp module is by the read access time deviation adjusting network interface card time with synchronous master clock.
The present invention uses hardware description language (VHDL) complete design, under the ISE10.1 software development environment of xi linx
Compiling, it is comprehensive using Synplify Pro, it writes test stimulus file and completes emulation, Zhi Hou in Modesim se 6.2
It is tested on KC705 development board, writes and load PCIe trawl performance and protocol stack on Linux host platform, completed whole
The verifying and test of a functional module.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (3)
1. realizing the system of PTP network interface card under a kind of FPGA characterized by comprising
Input module, for receiving ethernet data stream；
Processing module, for Ethernet data circulation PCIe data stream and the processing of IEEE1588 protocol massages；
Output module is provided the timestamp and associated control registers of ethernet data stream and IEEE1588 by PCIe bus
To user, user realizes trawl performance, TCP/IP and PTP protocol stack in operating system.
2. according to the system for realizing PTP network interface card under a kind of FPGA described in claim 1, which is characterized in that the input module packet
Include RJ45 interface and the PHY chip of 10/100/1000Mb, by Media Independent Interface or gigabit ethernet interface with
The MAC layer IP kernel of FPGA is connected, for receiving and dispatching the physical link of message.
3. realizing the system of PTP network interface card under a kind of FPGA according to claim 1, which is characterized in that the processing module
Include:
Business data processing module, by the data flow cache of Media Independent Interface or gigabit ethernet interface into round-robin queue's tail
Portion, PCIe are deposited into PCIe data space, CPU read data transfer upper-layer protocol stack from queue head access evidence；
IEEE1588 clock synchronization module generates for PTP packet check function and hardware timestamping and the time adjusts, wherein PTP
Packet check is scanning and correct identification IEEE1588 from the data flow of Media Independent Interface or gigabit ethernet interface
Message is submitted to the processing of upper layer PTP protocol stack；When the hardware timestamping refers between MAC layer and PHY to the addition of PTP message
Between stab field, the delay and jitter of cancellation protocol stack reflects the IEEE1588 message practical time sent and received；Time adjustment
It is that current PTP network interface card updates the local time according to the time deviation of link Round-Trip delay and PTP server；
Frequency clock synchronization module, using the precise time that IEEE1588 clock synchronization module generates come the input of control wave and defeated
Out, the 32 bit nanosecond count values that PTP network interface card is exported according to hardware timestamping export control command to selector by comparator,
To export second pulse signal, cyclic pulse signal and trigger signal；External input pulse per second (PPS) and event signal pass through level
Rising edge trigger interrupt, then the interruption is passed to the IP kernel of PCIe MSI interrupt processing.
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| CN201810923439.XA CN109150355B (en) | 2018-08-14 | 2018-08-14 | System for realizing PTP network card under FPGA |
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| CN201810923439.XA CN109150355B (en) | 2018-08-14 | 2018-08-14 | System for realizing PTP network card under FPGA |
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Cited By (5)
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| CN112436948A (en) * | 2020-11-12 | 2021-03-02 | 中国铁道科学研究院集团有限公司 | Train Ethernet card based on TSN and data receiving and transmitting method |
| CN112904932A (en) * | 2021-05-08 | 2021-06-04 | 鹏城实验室 | Clock synchronization method, board card, computer storage medium and terminal equipment |
| CN112994818A (en) * | 2019-12-18 | 2021-06-18 | 海信视像科技股份有限公司 | Time synchronization method and display device |
| CN114968893A (en) * | 2022-07-27 | 2022-08-30 | 井芯微电子技术(天津)有限公司 | PCIe message queue scheduling method, system and device based on timestamp |
| CN116028426A (en) * | 2023-03-28 | 2023-04-28 | 无锡沐创集成电路设计有限公司 | Multi-PCIe access network card and single-port network card driving method for uploading messages |
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| CN114968893A (en) * | 2022-07-27 | 2022-08-30 | 井芯微电子技术(天津)有限公司 | PCIe message queue scheduling method, system and device based on timestamp |
| CN114968893B (en) * | 2022-07-27 | 2022-09-30 | 井芯微电子技术(天津)有限公司 | PCIe message queue scheduling method, system and device based on timestamp |
| CN116028426A (en) * | 2023-03-28 | 2023-04-28 | 无锡沐创集成电路设计有限公司 | Multi-PCIe access network card and single-port network card driving method for uploading messages |
| CN116028426B (en) * | 2023-03-28 | 2023-08-15 | 无锡沐创集成电路设计有限公司 | Multi-PCIe access network card and single-port network card driving method for uploading messages |
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