CN109407752A - The synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication - Google Patents
The synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication Download PDFInfo
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- CN109407752A CN109407752A CN201811564713.5A CN201811564713A CN109407752A CN 109407752 A CN109407752 A CN 109407752A CN 201811564713 A CN201811564713 A CN 201811564713A CN 109407752 A CN109407752 A CN 109407752A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
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Abstract
The present invention provides realize the synchronous GIS breaker on-line monitoring system of clock in a kind of RS485 communication, including host and slave, the switching signal amount of host supervision GIS breaker, the current signal of slave monitoring GIS breaker, it is connected between host and slave by RS485 interface, the connecting line of RS485 interface serves not only as the communication wire between host and slave, simultaneously, as the clock sync signal line between host and slave, clock synchronization command control is carried out to slave for host, and, the synchronously control when configuration of communication baud rate when as RS485 communication wire is to as RS485 clock sync signal line does not have an impact.Present system not only realizes communication function only by RS485 all the way, also realizes clock sync signal function, and system clock synchronous effect is enabled to reach set requirement.
Description
Technical field
The present invention relates to communication technique fields, more particularly to a kind of based on realization clock synchronization in RS485 communication
GIS breaker mechanic property on-line monitoring system.
Background technique
GIS killer switch mechanical property on-line monitoring system, You Yitai host and 3 monitor compositions.Host supervision
Switching signal amount, the opening and closing time including signal, and three monitors detect the electric current letter of A, B, C threephase switch respectively
Number, current signal includes switching current and separating brake electric current.The parameter of monitoring includes the size of electric current and the time of current lead-through.It opens
The time that OFF signal and current signal occur is different, and the temporal correlation of the two signals is very close.The time of current signal
It is combined together with the time of switching signal, just forms a complete parameter value.So in practical applications, host and monitoring
The synchronization of the respective time of device just becomes critically important.
Existing GIS breaker mechanic property on-line monitoring system, in addition to communication between host and three detectors
Except RS485 signal wire, RS485 signal all the way is also added in addition, for realizing the time synchronization of host and three monitors.
Such two-way RS485 signal wire, other than the increased costs of cable, there are also construction volume increases, and mostly all the way
Signal instability will increase, maintenance can increase accordingly.
Summary of the invention
For above-mentioned defect existing in the prior art, the object of the present invention is to provide one kind based on real in RS485 communication
The synchronous GIS breaker mechanic property on-line monitoring system of current clock, the precision clock of host and slave processors is synchronous in realization system.
In order to achieve the above objectives, the technical solution adopted in the present invention is as follows:
Realize the synchronous GIS breaker mechanic property on-line monitoring system of clock in a kind of RS485 communication, including host and
Slave, the switching signal amount of host supervision GIS breaker, slave monitors the current signal of GIS breaker, between host and slave
It being connected by RS485 interface, the RS485 interface connecting line serves not only as the communication wire between host and slave, meanwhile,
As the clock sync signal line between host and slave, clock synchronization command control is carried out to slave for host, and, as
The synchronously control when configuration of communication baud rate when RS485 communication wire is to as RS485 clock sync signal line does not produce
It is raw to influence.
Specifically include that steps are as follows:
Step 1: host sends warning order
When needing to carry out clock synchronization, the synchronous warning order of host elder generation tranmitting data register, transmission order aft engine will be done must
The preparation wanted, including allow external interrupt, interrupt identification is reset；
Step 2: slave receives warning order
After slave receives warning order, necessary preparation is done, including allow external interrupt, interrupt identification is reset；
Step 3: host sends synch command
After synch command is sent, host can generate external interrupt, can generate interrupt identification, record in external interrupt
Master clock when generating and preservation are interrupted, and external interrupt is forbidden to generate again, until sending new synch command again；
Step 4: slave receives synch command
After slave receives synch command, also produce external interrupt, in external interrupt record interrupt generate when from
Clock value simultaneously saves, and external interrupt is forbidden to generate again, until receiving the new synch command of host transmission again；
Step 5: host sends master clock；
Step 6: slave receives master clock；
Step 7: slave corrects the slave clock of oneself
After slave receives the master clock value of host, the slave clock of oneself is modified.
The data transmission line of host connects its external interrupt pin, after host sends synch command to each slave, host
A data are sent, the start bit of the data is interrupted as clock sync signal to trigger host external interrupt pin；
The data receiver line of slave connects its external interrupt pin, after the synch command that slave receives host sending, waits to be received
The data that host is sent, the start bit of the data is as clock sync signal to trigger in the generation of slave external interrupt pin
It is disconnected.
The external interrupt priority of cpu controller in host is configured to the highest priority in its all interruption；Slave
In the external interrupt priority of cpu controller be configured to the highest priority in its all interruption.
The triggering of the interrupt signal in external interrupt pin in host is configured to trigger interruption from high to low；In slave
The triggering of interrupt signal in external interrupt pin is configured to trigger interruption from high to low.
Synch command is the data of a byte or multiple bytes.
Clock includes the value of clock counter and the value of timer, wherein the value of timer is recorded to the essence of system clock
Degree setting position, is interrupted, the value of timer resets and reloads, and the value of clock counter adds 1 until overflowing.
The master clock when interruption being recorded in external interrupt generates is known as synchronous master clock, is saved in master counter
In M_Int_Time_Counter and master timer M_Int_Timer；Be recorded in external interrupt interruption generate when from when
Clock value is saved in from clock counter S_Int_Time_Counter and from timer S_Int_Timer；Slave receives master
After the master clock value of machine, when being modified to the slave clock of oneself, slave first reads from oneself current slave clock counter S_
Time_Counter and value from timer S_Timer calculate separately the two values and interrupt corresponding two saved when generating
The deviation of a value is then written to S_Time_Counter and S_ deviation plus the master clock value saved when interrupting and generating
It in Timer, hereafter starts counting from the value in timer from S_Timer, is interrupted until overflowing, after interruption, S_Time_
Counter value do plus 1 adjustment.
It is revised also to exist between clock and current master clock after slave clock of the slave to oneself is modified
Certain synchronous error, the time difference of the time difference, interrupt processing including signal transmission and master clock and from the respective clock of clock
The time difference caused by source is different, the time difference of signal transmission refers to host and slave generates the time difference between interrupting, interrupt processing
The time difference has in host and slave, indicates to the time difference read between respective clock after interrupting generation, wherein by leading
Clock with from the respective clock source of clock it is different caused by the time difference assignment of timer can be calibrated again by slave.Or
Person reduces the synchronization of time intenals between host and slave to reduce time deviation.
Host is one, and the switching signal amount for monitoring includes the signal closing time and separating brake of A, B, C threephase switch
Time；Slave is 3, for monitoring the current signal of A, B, C threephase switch, including switching current and separating brake electric current respectively.
Compared with prior art, the present invention have it is following the utility model has the advantages that
It is disclosed by the invention to be based on the GIS breaker mechanic property on-line monitoring for realizing that clock synchronizes in RS485 communication
System by original communication RS485 and synchronous RS485 two paths of signals line with realizing identical function all the way, and improves performance.It is former
What is transmitted on synchronous RS485 signal wire is communication command.When needing clock synchronous, host first reads master clock value, by same
RS485 signal wire hair master clock is walked to slave, slave is again corrected respective clock after receiving master clock.It is sent out from host
It is sent to slave and receives master clock value, then to the clock information of slave parsing host, this can occupy the regular hour in the process,
After clock of the slave to oneself is proofreaded, from clock, there are deviations with master clock.And this patent is using same
One signal is as clock sync signal, and host and slave processors receive after this signal simultaneously while reading respective clock value, institute
With after the clock correction on C machine, the system clock deviation of whole system is with regard to very little.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the system structure diagram of one embodiment of the invention；
Fig. 2 is hardware principle structural block diagram of the invention；
Fig. 3 is Clock Synchronization Procedure schematic diagram of the present invention；
Fig. 4 is host timer interrupt service flow chart of the present invention；
Fig. 5 is host external interrupt service flow diagram of the present invention；
Fig. 6 is host main program flow chart of the present invention；
Fig. 7 is slave main program flow chart of the present invention；
Fig. 8 is system testing schematic diagram of the invention；
Synchronization signal time error schematic diagram when Fig. 9 is synchronous；
Figure 10 is the clock difference schematic diagram of host and slave after clock is one second synchronous.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
Shown in Fig. 1, the present invention provides a kind of based on the GIS breaker mechanic property for realizing that clock synchronizes in RS485 communication
On-line monitoring system.Including a host and 3 slaves.In the course of work, after host and 3 slave clock synchronizations, have identical
One system clock.After if slave 1 monitors A phase switching current signal, at the beginning of slave 1 records the electric current and the time
Length, and measure the size of electric current.Wherein refer to system clock when electric current starts at the beginning of electric current；Hereafter, host meeting
Receive the variation of A phase switching signal.At the beginning of the variation of host record A phase switching signal and the end time, that is, believe
Number variation when system clock.After switching signal, host can read the data of slave 1, opening for the switching current of slave 1
The end time for the switching signal that time beginning arrives to Host Detection, as entire closing time, this parameter has reacted the reality of switch
Border actuation time.
Since host and slave 1 all record the time with system clock, so the accuracy of system clock clock synchronization is had
The embodiment of body.
The synchronous principle of present system clock:
Host and slave have timer on single-chip microcontroller all using single-chip microcontroller as control unit, have external interrupt pin and
UART interface.Wherein UART connection RS485 chip, the communication bus as system use.
Master clock and production principle from clock:
Single-chip microcontroller on host is known as host CPU, and the single-chip microcontroller on slave is known as from CPU.Single-chip microcontroller on host and slave
It is all after using external crystal-controlled oscillation frequency multiplication as work clock.Master and slave CPU each has the work clock and timer of oneself, work
Clock source of the clock after frequency dividing as timer, clock source can be set as generating in timing by certain time interval
Disconnected, the number of interruption is recorded rear shape and forms master clock and from clock.Time interval is arranged according to actual needs, can be 1 second,
1 millisecond etc..
The synchronous of hardware signal is realized:
It realizes that clock is synchronous, is realized on hardware by signal wire.The hardware connection structure figure of host and slave is such as
Shown in Fig. 2.Host and slave are communicated by RS485 in system, and the interface that RS485 chip is connected with CPU is UART interface.It is logical
During news, the signal that the transmission data line TXD_M of host CPU and the reception data line RXD_S from CPU are generated is identical and same
Step, can use this signal wire as synchronous signal line.
The accurate reading of time:
UART, which sends data, to be sent according to position, is sent one 8 data and generally to be sent 10 positions, wherein there is starting
Position and stop position.It is high level in no transmissions data that UART, which sends signal, and start bit when sending data is low level,
This start bit in communication process can be used as synchronization signal.According to this synchronization signal, host CPU and same from CPU is needed
When grab respective clock.
Signal is grabbed simultaneously to realize by interrupting.There is external interrupt pin in CPU, in host CPU, TXD_Mx
It is signally attached to an interrupt pin.From CPU, RXD_S is signally attached to an interrupt pin.The external interrupt of CPU
The jump from height to ground level is both configured to trigger.Clock is read in the external interrupt of CPU, CPU master and slave in this way can be same
When read respective clock.
The amendment of slave clock:
After obtaining respective clock, master clock is sent to slave by host, after slave receives the clock value of host, main
The clock value when clock of machine and oneself interruption is compared, and is corrected the clock of oneself, is achieved that same with host clock
Step.
It is further described in detail below by way of a specific embodiment come the concrete methods of realizing synchronous to clock.
The configuration of timer and Interruption processing:
Host CPU uses STM32F103VCT6 chip, system clock frequency: 72MHz clock, using timer Timer4, when
The pre- divider ratio of clock is 720, then a clock cycle is 0.01mS, i.e. 10uS.The automatic reloading register period of timer
Value be set as 50000, then the Interruption primary time be 50000x 0.01mS=500mS.Master timer is named as M_
Timer。
STM32F103C8T6 chip is used from CPU, the configuration of system frequency and timer is identical with host CPU, from timer
It is named as S_Timer.
The timer of CPU is 16, and with postponing opening timing device, timer counts plus one every 10uS, etc. count values reach
Count value is reset when to 50000, and generates Interruption, twice Interruption time interval 500mS.Defined variable record interrupts
Number, so that it may be converted into clock.The timer interruption number counting variable of host is named as host clock counter, variable
Name: M_Time_Counter, the entitled slave clock counter of the timer interruption number counting variable of slave, variable name: S_
Time_Counter。
In host Interruption, M_Time_Counter counter adds 1；In slave Interruption, M_Time_Counter
Counter adds 1.
The configuration of UART interface:
UART is communicated for connecting RS485 chip.Host CPU meets RS485 using UART1, configures baud rate 115200,
8 data bit, 1 stop position, no parity.UART3 connection RS485 chip is used from CPU, configures baud rate 115200,8
Position data bit, 1 stop position, no parity.
The configuration and interrupt processing of external interrupt:
Host CPU external interrupt uses PC0 pin, connects the transmission signal wire TX of UART.Failing edge triggering is configured to interrupt.
PA2 pin is used from CPU external interrupt, connects the reception signal wire RX of UART.Failing edge triggering is configured to interrupt.Master and slave CPU
External interrupt can be carried out the setting forbidden and allowed, that is, forbid interrupt generate and allow interrupt generate.
The time count value that timer is read in interruption, saves.
The processing of host CPU external interrupt: reading the value of clock counter M_Time_Counter and timer M_Timer, and
It is saved in M_Int_Time_Counter and M_Int_Timer, interrupt identification is set, external interrupt is forbidden；
From the processing of CPU external interrupt: the value of clock counter S_Time_Counter and timer S_Timer are read, and
It is saved in S_Int_Time_Counter and S_Int_Timer, interrupt identification is set, external interrupt is forbidden；
Clock Synchronization Procedure, as shown in Figure 3:
Slave and the clock of host synchronize include the following steps realization: host sends warning order；Slave, which receives, prepares life
It enables；Host sends synch command；Slave receives synch command；Host sends master clock；Slave receives master clock and corrects oneself
Slave clock, as shown in Figure 2.
Detailed process includes the following:
Host sends warning order: when needing to carry out clock synchronization, the synchronous warning order of host elder generation tranmitting data register.It sends
Order aft engine will do necessary preparation, and specially permission external interrupt, interrupt identification are reset.
After slave receives warning order, same preparation is done, allows external interrupt, interrupt identification is reset.
Host sends synch command: after synch command is sent, host can generate external interrupt, can generate interruption mark
Will, and the master clock interrupted when generating has also been recorded in external interrupt, master clock value is stored in M_Int_Time_
In Counter and M_Int_Timer.The clock-unit of value in M_Int_Time_Counter is 0.5S, i.e. 500mS；M_
The clock-unit of value in Int_Timer is 0.01mS, i.e. 10uS.
After slave receives synch command, external interrupt is also produced, this can sentence according to interrupt identification
It is disconnected.Slave clock value when generating is interrupted to be stored in S_Int_Time_Counter and S_Int_Timer.S_Int_Time_
The clock-unit of value in Counter is 0.5S, i.e. 500mS；The clock-unit of value in S_Int_Timer is 0.01mS, i.e.,
10uS.After slave receives synch command, the master clock value of receiving host is waited.
Host send master clock: host send synch command after, send master clock value, i.e. M_Int_Time_Counter and
Data in M_Int_Timer are to slave.
After slave receives the clock value of host, by calculating, the clock of oneself is modified.
Host sends clock synchronization order, 16 binary data packets: " 55 AA, 31 54 49 4D, 45 0D 0A "
Host sends clock synchronization data packet, 16 binary data packets: " 55 AA 32 "
Host sends host time, 16 binary data packets: " 55 AA, 33 xx xx xx xx yy yy "
Parameter definition:
The timing of host clock second: M_Time_Counter, unit 0.5 second
When host clock microsecond meter: M_Timer, unit 10 are delicate or 0.01 millisecond
Slave clock second timing: S_Time_Counter, unit 0.5 second
When slave clock microsecond meter: S_Timer, unit 10 are delicate or 0.01 millisecond.
The calculating and amendment of slave clock:
After slave receives the clock data of host, the clock of oneself is modified.Read current clock counter
The value of S_Time_Counter and timer S_Timer calculate separately the two values and interrupt corresponding two values when generating
Deviation, deviation add master clock value, be then written in S_Time_Counter and S_Timer.Hereafter in timer
Value started counting from S_Timer, until overflow interrupt, after interruption, S_Time_Counter value do plus 1 adjustment.
Software flow:
Host timer interrupt service program, as shown in Figure 4:
Host timer interrupt service program handles host clock and updates, and main function is to carry out second increase by 1 to count.Meter
Number often adds 1, indicates that master clock increases by 0.5 second.Increase a test signal in the interrupt service program simultaneously, test signal is one
A low pulse signal, with oscilloscope measurement it can be seen that, every one low pulse signal of output in 0.5 second.
Slave timer interrupt service program:
The timer interrupt routine of slave is identical with host and each 0.5 second count value adds 1, and also export one it is low
Pulse signal.
Host external interrupt service routine, as shown in Figure 5:
The generation of host external interrupt is caused by clock synchronization command, and master clock is read in interruption and is saved, and
External interrupt is forbidden to generate.This clock is known as synchronous master clock, is saved in M_Int_Time_Counter and M_Int_
In Timer, clock when Host Interrupt is indicated.
Interrupt service routine outside slave:
The generation of slave external interrupt is also to be caused by clock synchronization command, and processing mode is identical with host, reading when
Clock value is saved in S_Int_Time_Counter and S_Int_Timer, indicates clock when slave interrupts.
Host main program flow, as shown in Figure 6:
Host main program flow is that host is held in Clock Synchronization Procedure from the initiation clock synchronization program that clock synchronization terminates to the end
Row process.
Slave main program flow, as shown in Figure 7:
Slave main program flow be slave in the process of running, from receive clock synchronization warning order to clock synchronization processing complete
Program execution flow.
Clock synchronism detection result and analysis, shown in Fig. 8.
Influence the factor of clock synchronous error:
Influencing the clock synchronous time difference includes the time difference of signal transmission and the clock difference of interrupt processing.Signal transmission refers to
It is the time difference between host and slave generation interruption.By measurement, the time difference in 1.4uS or so, as shown in Figure 9.Interrupt processing
Time have in host and slave, indicate interrupt occur after to the time difference read between respective clock.Actual measurement
In, the time of interrupt processing is 3uS or so, if keeping host and the interrupt processing process of slave consistent as far as possible, when can reduce
Between deviation.
The synchronous measurement of clock:
Figure 10 is the clock after the synchronizing of actual measurement.It is the letter of host and slave output at 1 second after clock synchronizes
Number time deviation.It is less than 5uS according to the diagram time difference.By measuring for a long time, the clock jitter after having respective time to synchronize is big
In 10uS, but not more than 20uS.
If reducing the synchronous deviation of clock, the method that can be used: reducing the divider ratio of timer, can be with from 10uS
It is increased to 2uS.
After clock synchronizes, since master clock is different with from the respective clock source of clock, also can slowly it be generated in operational process
Deviation, the method that reducing this deviation can use are that slave is calibrated from the assignment of timer again；In addition be reduce host and
Synchronization of time intenals between slave, such as 10 seconds or clock synchronization of shorter time progress.
In this experiment measurement process, master clock and be 1.1uS/S from the time difference between clock, if done for 10 seconds primary
Clock it is synchronous when, deviation has reached 11uS, it is possible to which it is synchronous to make a clock using 5 seconds.
High precision clock synchronized measurement system has very big use space in energy monitoring apparatus, and test proves, this hair
The bright clock synchronization accuracy based on RS485 distributed network system (DNS) can achieve Microsecond grade.It is other from cost and precision aspect
Clock based on RS485 network system simultaneously provides reference and help.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (10)
1. realizing the synchronous GIS breaker on-line monitoring system of clock in a kind of RS485 communication, which is characterized in that including host
And slave, the switching signal amount of host supervision GIS breaker, slave monitor the current signal of GIS breaker, host and slave it
Between connected by RS485 interface, the RS485 interface connecting line serves not only as the communication wire between host and slave, together
When, as the clock sync signal line between host and slave, clock synchronization command control is carried out to slave for host, and,
The synchronously control when configuration of communication baud rate as RS485 communication wire is to as RS485 clock sync signal line is not
It has an impact.
2. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 1, it is special
Sign is, specifically includes that steps are as follows:
Step 1: host sends warning order
When needing to carry out clock synchronization, the synchronous warning order of host elder generation tranmitting data register, transmission order aft engine will do necessary
Preparation, including allow external interrupt, interrupt identification is reset；
Step 2: slave receives warning order
After slave receives warning order, necessary preparation is done, including allow external interrupt, interrupt identification is reset；
Step 3: host sends synch command
After synch command is sent, host can generate external interrupt, can generate interrupt identification, be recorded in external interrupt
Master clock when generating and preservation are interrupted, and external interrupt is forbidden to generate again, until sending new synch command again；
Step 4: slave receives synch command
After slave receives synch command, also produce external interrupt, be recorded in external interrupt interrupt generate when from
Clock value simultaneously saves, and external interrupt is forbidden to generate again, until receiving the new synch command of host transmission again；
Step 5: host sends master clock；
Step 6: slave receives master clock；
Step 7: slave corrects the slave clock of oneself
After slave receives the master clock value of host, the slave clock of oneself is modified.
3. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 2, it is special
Sign is that the data transmission line of host connects its external interrupt pin, and after host sends synch command to slave, host is sent
The start bit of one data, the data is interrupted as clock sync signal to trigger host external interrupt pin；Slave
Data receiver line connect its external interrupt pin, slave receive host sending synch command after, wait receiving host
The start bit of the data of transmission, the data is interrupted as clock sync signal to trigger slave external interrupt pin.
4. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 2, it is special
Sign is that the external interrupt priority of the cpu controller in host and slave processors is each configured to the highest priority in its all interruption.
5. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 2, it is special
Sign is that the triggering of the interrupt signal in external interrupt pin in host and slave processors is each configured to trigger interruption from high to low.
6. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 2, it is special
Sign is that synch command is the data of a byte or multiple bytes.
7. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 2, it is special
Sign is that clock includes the value of clock counter and the value of timer, wherein the minimum of the value decision systems clock of timer is single
Position is interrupted until overflowing, and the value of timer resets and reloads, and the value of clock counter adds 1.
8. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 2, it is special
Sign is that the master clock when interruption being recorded in host external interrupt generates is known as synchronous master clock, is saved in master clock meter
In number device M_Int_Time_Counter and master timer M_Int_Timer；The interruption being recorded in slave external interrupt generates
When slave clock value be saved in from clock counter S_Int_Time_Counter and from timer S_Int_Timer；Slave
After the master clock value for receiving host, when being modified to the slave clock of oneself, slave first reads from oneself current slave clock
Counter S_Time_Counter and value from timer S_Timer calculate separately what the two values and interrupting saved when generating
The deviation of corresponding two values is then written to S_Time_ deviation plus the master clock value saved when interrupting and generating
It in Counter and S_Timer, hereafter starts counting from the value in timer from S_Timer, is interrupted until overflowing, after interruption, S_
Time_Counter value do plus 1 adjustment.
9. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 2, it is special
Sign is, revised also to exist between clock and current master clock after slave clock of the slave to oneself is modified
Certain synchronous error, the time difference of the time difference, interrupt processing including signal transmission and master clock and from the respective clock of clock
The time difference caused by source is different, the time difference of signal transmission refers to host and slave generates the time difference between interrupting, interrupt processing
The time difference has in host and slave, indicates to the time difference read between respective clock after interrupting generation, wherein by leading
Clock with from the respective clock source of clock it is different caused by the time difference assignment of timer can be calibrated again by slave, or
Person reduces the synchronization of time intenals between host and slave to reduce time deviation.
10. the synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication according to claim 2, it is special
Sign is that host is one, and the switching signal amount for monitoring includes the opening and closing time of signal；Slave is 3, is used for
The current signal of A, B, C threephase switch, including switching current and separating brake electric current are monitored respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811564713.5A CN109407752B (en) | 2018-12-20 | 2018-12-20 | GIS breaker online monitoring system for realizing clock synchronization in RS485 communication |
Applications Claiming Priority (1)
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| CN112118065A (en) * | 2020-09-10 | 2020-12-22 | 国电南瑞南京控制系统有限公司 | Clock synchronization system and method for low-voltage power distribution station area |
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