CN104954096A - One-master multi-slave high-speed synchronous serial communication data transmission method - Google Patents
One-master multi-slave high-speed synchronous serial communication data transmission method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0076—Distributed coding, e.g. network coding, involving channel coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
Abstract
Provided is a one-master multi-slave high-speed synchronous serial communication data transmission method, which is suitable for the field of master-slave multi-channel high-speed transmission. Data to be transmitted and a communication clock are modulated to one signal line in a coding manner and the data are transmitted by the one-master multi-slave mode, thereby simplifying the system communication structure, reducing the number of communication lines and the communication cost and increasing the transmission speed. In addition, an excellent serial synchronous clock is obtained by the decoding method, thereby reducing the bit error rate of transmission.
Description
Technical field
The present invention relates to data transmission method, be specifically related to a kind of high-speed synchronous serial communication data transmission method of one master and multiple slaves.
Background technology
At present, large scale industry field signal acquisition node disperses, quantity is many, and manual site's collecting efficiency is low, and particularly collection point is positioned at the application scenario of high temperature, high humidity, high-noise environment, manually collection in worksite cannot be carried out, and artificial acquisition mode data are lengthy and jumbled is not easy to unified management.The serial communication of " one master and multiple slaves ", by the data acquisition to multiple collection point, transmission, and unify record management data information by main frame, substantially increase data acquisition efficiency, solve the problem of the lengthy and jumbled management inconvenience brought of data, become the major way of Solving Multichannel transfer of data.
The serial data transmission mode of " one master and multiple slaves " mainly contains two kinds: synchronous serial communication and asynchronous serial communication.Wherein, conventional asynchronous serial communication mode has RS-232, RS-485, RS-422, CAN, LIN etc., and asynchronous serial communication protocol does not generally need special synchronised clock line, only needs a data lines and a ground wire, just can carry out transfer of data by arranging corresponding baud rate, structure is simple; But asynchronous transmission communication overhead is large, and communication efficiency is low, and transmission rate is low, is not suitable for high speed data transfer.
Conventional synchronous serial communication mode has I
2s, SPI, LVDS, MLVDS etc., synchronous serial communication needs special clock line, transfer of data is carried out by clock line, data wire and ground wire, transmission speed is fast, is applicable to high speed data transfer, but its transmitting procedure needs to be no less than three lines carries out transfer of data, do not mate with general two-ways transmitting, seriously limit application, and transmission system complex structure, long-distance transmissions cost is high.
In sum, there is following problem in the data transfer mode of " one master and multiple slaves ": on the one hand based on the demand of real-time, higher to the requirement of message transmission rate; On the other hand based on low cost and the demand transmitting accuracy rate, require that data transmission system structure is simple, transmission line is few, and transmission error rates is low.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, the high-speed synchronous serial communication data transmission method of one master and multiple slaves is proposed, the method is applicable to principal and subordinate's multi-channel high-speed transmission field, the data transmitted by coded system and communication clock are modulated on a holding wire, adopt the mode of one master and multiple slaves to carry out transfer of data, thus simplify system communication structure, reduce order wire number, reduce communications cost, improve transmission rate; And obtain excellent serial synchronization clock by decoding process, reduce the error rate of transmission.
Described coded system is:
Transmit leg system provides 100MHz clock, and primary signal speed is 25MHz, and the coded system of data is: 0 à 1000,1 à 1110.
4 codings of a corresponding 100MHz of code element.When each code element starts, the 1st is " 1 ", and the 2nd and the 3rd is input signal information, and the 4th is " 0 ", so just can ensure to produce a rising edge when each code element starts.This rising edge is a very excellent synchronised clock, as long as by the active position (the 2nd of coding, 3) of rising edge aligned data, can recover original signal.
When input signal is " 1 ", export as " 1110 "; When input signal is " 0 ", export as " 1000 ".Its essence is exactly a serial code generator, according to different inputs, produces different output sequences.System clock is obtained by the PLL frequency multiplication of programmable logic device (CPLD), and coding circuit is also realized by programmable logic device (CPLD).
By above-mentioned coded system by the data that send and clock modulation in a data lines, as shown in Figure 4, many to solve transmission line in serial transmission, communication structure is complicated, and communications cost is high, is not suitable for the problem of high speed long-haul transport.
Described decoding process is (extraction of receiving terminal synchronised clock):
Decode procedure is that input signal is obtained synchronised clock by the time delay of RC delay circuit, then recovers original signal by synchronised clock.As shown in Figure 5, input signal obtains synchronised clock by RC delay circuit, and now, the active position (time range of the 2nd, 3 of coding is 10ns ~ 30ns) of the rising edge aligned data coding of synchronised clock, can recover original signal.When signal is by RC delay circuit, the width of signal may change, and using the signal by RC delay circuit as synchronised clock, be only concerned about its leading edge position, and the change of its width can not affect decode procedure.
By the mode of decoding, by the information decoding of coding out, obtain initial data and clock.
The synchronous settling time of this coded system is short, decoding circuit theory and design is all extremely simple, adopts a frame synchronization to detect data and starts, and recovers synchronised clock, and be not very high to the precision of recipient's clock and frequency requirement, easily realize in systems in practice.
The high-speed synchronous serial data transmission method of described a kind of one master and multiple slaves mode, concrete mode is as follows:
Step 1: system initialization: after system electrification, first main frame sends reset signal to from machine, and main frame is in transmission state, is in accepting state from machine; After reset completes, from machine clear buffer and correlated variables, enter into the order cycle detection stage, perform the various tasks of configuration.
Step 2: main frame sends acquisition: host computer polls respectively starts acquisition from machine configuration, and the data frame packet that main frame sends is containing six parts: Part I is hostid, is used for identifying the command frame that main frame sends; Part II, main frame read-write identifier; Part III is geocoding, deposits the geocoding from machine; Part IV is command register, deposits the operational order that main frame sends; Part V is packet, deposits the content of order; Part VI is check code, ensures communication reliability.
Step 3: from machine reception acquisition: main frame shares a data lines and a ground wire with each from machine, so respectively receive the Frame of main frame transmission from machine simultaneously.Respectively judge whether this Frame comes to main frame from machine by Frame Part I, if carry out from host, then whether the Part II geocoding contrasting geocoding and the Frame self pre-set conforms to, thus judges whether to start to communicate with main frame.
Step 4: send data from machine: confirm the acquisition of main frame from machine after, starts to transmit data, according to the connected mode of one master and multiple slaves to main frame, from the Frame that machine transmits, main frame all can receive from machine with other, therefore, needs adding one from machine identifier from machine data frame highest order.When main frame receives Frame, first by Frame judges whether this Frame comes since machine, if so, then receives this Frame; And other is when receiving this Frame from machine, judge whether this Frame comes since machine according to the upper identifier of first on Frame equally, if so, then other will not respond from machine.
Step 5: release communication link: use serial transmission protocol in data transmission procedure, for avoiding data bit generation entanglement, main frame sends reseting data frame (namely reset array) after often receiving frame data, once reset, after machine receives this Frame, clear buffer and correlated variables.
Step 6: when receiving main frame from machine and stopping acquisition or communication system to occur abnormal (when occurring multiple 0 when transmitted data bits, represent data bit entanglement), main frame sends a reset signal, makes system be in reset mode, namely return step 2, continue wait command from machine.
The advantage of the high-speed synchronous serial communication data transmission method based on one master and multiple slaves mode that the present invention realizes is:
1. devise a kind of high-speed synchronous serial communication data transmission method based on one master and multiple slaves mode, this transmission method uses synchronous serial communication transmission technology, by CPLD control logic Direct driver hardware, meet the requirement of measurement and control system high speed transfer of data, and structure is simpler, transmission line is few, and transmission error rates is low.
2. devise a kind of decoding method of high-speed synchronous serial data transmission, data and clock modulation will be transmitted on a transmission lines, have the advantage of synchronous serial transmission and asynchronous serial transmission concurrently, and avoid both shortcomings, the method is that the high-speed transfer of principal and subordinate's multi-channel data is given security.
Accompanying drawing explanation
Fig. 1 is the order data frame format that main frame sends;
Fig. 2 is the data frame format sent from machine;
Fig. 3 is principal and subordinate's multimachine data delivery topology structure chart;
Fig. 4 is cataloged procedure;
Fig. 5 is decode procedure;
Fig. 6 is that principal and subordinate's multi-channel high-speed data transmission method performs flow process;
Fig. 7 is the reseting data frame that main frame sends;
Fig. 8 is the order data frame that main frame sends;
Fig. 9 is the Frame sent from machine;
Figure 10 is master-slave communication sequential chart;
Figure 11 is transmitting terminal coded system;
Figure 12 is asynchronous communication means figure;
Figure 13 is synchronous communication mode figure.
Embodiment
In order to ensure that the high speed of complex control system and measuring system data is effectively transmitted, require that data transmission system must support higher data transmission rate, the lower error rate and higher real-time, this proposes higher requirement to the design of data transmission system.
Data delivery topology structure chart of the present invention as shown in Figure 3.As can be seen from Fig. 3, the high-speed synchronous serial data transmission method based on one master and multiple slaves mode of the present invention's design comprises host A and multiple from machine B.Host A with respectively share from machine the high-speed transfer that a ground wire and holding wire carry out data.
Described host A sends acquisition signal, this acquisition signal transmits after programmable logic device coding, accept this order from machine accordingly and respond according to Host Command, shown in the concrete high-speed synchronous serial data transmission flowchart 6 based on one master and multiple slaves mode, comprise the steps:
Step 1: system initialization.
After system electrification, first host A sends reset signal, and as shown in Figure 7, main frame is in transmission state to its form, is in accepting state from machine B; After reset completes, from machine B clear buffer and correlated variables, enter into the order cycle detection stage, perform the various tasks of configuration;
Step 2: main frame sends acquisition.
Host A poll respectively starts acquisition from machine configuration, and shown in order data frame Fig. 8 that host A sends, totally 17, the 17th is the mark of host A, and " 0 " represents host A; 16th, read-write position, is written as " 0 ", reads as " 1 "; 15th ~ 13 is address bit, and according to the number from machine B, address bit can arrange different width, can arrange at most 32 in theory from machine; 12nd ~ 9 is 4 bit registers, deposits the order that main frame sends; 8th ~ 1 is 8 bit data positions, deposits the particular content of order; 0th is parity check bit.
Step 3: receive acquisition from machine.
The 1st of the order data frame sent according to host A from machine B judges that whether this Frame is from host A, if the 1st is " 0 ", then receive this Frame from machine, then judge whether the address that the geocoding part of Frame pre-sets with oneself conforms to, if conformed to, then judge register-bit, according to host A to the order sent from machine B, make different response from machine B.
Step 4: send data from machine.
Confirm the acquisition of host A from machine B after, start to transmit data to host A, its data frame format is as shown in Figure 9, and the 17th of Frame is the identifier from machine, and " 1 " represents from machine; 16th ~ 1 is data bit; 0th is parity check bit.
Step 5: release communication link.
In order to prevent the confusion communicated, host A all will send reseting data frame after often receiving frame data, once resets, after machine B receives this Frame, from machine B clear buffer and correlated variables.
Step 6: when receiving host A from machine B and stopping acquisition or communication system to note abnormalities, host A sends a reset signal, makes system be in reset mode, namely returns step 2, continues wait command from machine.
In order to realize main frame and the high-speed synchronous serial transmission from data between machine, the present invention encodes to data at transmitting terminal programmable logic device (CPLD), by data and clock modulation on a line; Extract synchronised clock at receiving terminal by RC delay circuit, then utilize synchronised clock to the decoding data received, extract initial data and clock, thus realize transfer of data at a high speed.Concrete code encoding/decoding mode is as follows:
1) transmitting terminal coded system
Transmitting terminal system clock is 100MHz, the coded system of data as shown in figure 12: 1 à 1110,0 à 1000.
4 codings of a corresponding 100MHz of code element.The 1st of these four codings is " 1 ", and 2nd ~ 3 is the information of input symbols, and the 4th is " 0 ".By coding, the transmission rate of data is 1/4 of system clock, is 25MHz.System clock is obtained by the PLL frequency multiplication of programmable CPLD, and coding is also realized by CPLD.
As shown in Figure 4, data and serial synchronization clock signal are modulated on single line after coding.
2) receiving encoding mode
Receiving terminal system clock is 200MHz, input signal is obtained synchronised clock through RC time delay, then recovers original signal by synchronised clock, as shown in Figure 5.
Input signal obtains synchronised clock through RC delay circuit time delay 15 ~ 20ns, and the rising edge of such synchronised clock is registered to the active position of data encoding (time range of the 2nd, 3 of coding is 10 ~ 30ns), can recover original signal accurately.
The sequential chart of principal and subordinate's high-speed serial communication Code And Decode as shown in Figure 10, the sequence that transmitting terminal will send for " 10110 ", according to coding rule, under transmitting terminal 100MHz clock, " 1 " being encoded to " 1110 ", " 0 " being encoded to " 1000 ", therefore " 10110 " be encoded to " 11101000111011101000 ", the coding that receiving terminal receives also is " 11101000111011101000 ", synchronised clock clk is obtained through time delay 15 ~ 20ns, active position (2nd of the coding of the rising edge of clk at the data encoding received can be found out, the time range of 3 is 10 ~ 30ns) within, therefore the data received are easy to decoding out.
Concrete example of the present invention, experiment transmission range 20m, transmission rate is 25M/S, communicates reliable and stable.Transmission digit rate can be improved further according to actual needs.In invention, main frame and from machine communication protocol, achieves principal and subordinate's multi-computer communication and does not produce conflict; Extract the synchronised clock of serial communication by the mode of time delay, achieve the multichannel high speed serialization synchronous communication of principal and subordinate.
Claims (7)
1. a high-speed synchronous serial data transmission method for one master and multiple slaves mode, is characterized in that: comprise the steps:
Step 1, system initialization: after system electrification, first main frame sends reset signal to from machine, and main frame is in transmission state, is in accepting state from machine; After reset completes, from machine clear buffer and correlated variables, enter into the order cycle detection stage, perform the various tasks of configuration;
Step 2, main frame send acquisition: host computer polls respectively starts acquisition from machine configuration, and the data frame packet that main frame sends is containing six parts: Part I is hostid, are used for identifying the command frame that main frame sends; Part II, main frame read-write identifier; Part III is geocoding, deposits the geocoding from machine; Part IV is command register, deposits the operational order that main frame sends; Part V is packet, deposits the content of order; Part VI is check code, ensures communication reliability;
Step 3, receive acquisition from machine: main frame and respectively share a data lines and a ground wire from machine, respectively receive the Frame of main frame transmission from machine simultaneously, respectively judge whether this Frame comes to main frame from machine by Frame Part I, if carry out from host, whether the Part II geocoding then contrasting geocoding and the Frame self pre-set conforms to, thus judges whether to start to communicate with main frame;
Step 4, from machine send data: from machine confirm main frame acquisition after, start to transmit data to main frame, according to the connected mode of one master and multiple slaves, from the Frame that machine transmits, main frame all can receive from machine with other, therefore, need adding one from machine identifier from machine data frame highest order, when main frame receives Frame, first by Frame judges whether this Frame comes since machine, if so, then this Frame is received; And other is when receiving this Frame from machine, judge whether this Frame comes since machine according to the upper identifier of first on Frame equally, if so, then other will not respond from machine;
Step 5, release communication link: use serial transmission protocol in data transmission procedure, for avoiding data bit generation entanglement, main frame sends reseting data frame after often receiving frame data, once resets, after machine receives this Frame, clear buffer and correlated variables;
Step 6, when receiving main frame from machine and stopping acquisition or communication system to occur abnormal, main frame sends a reset signal, makes system be in reset mode, namely returns step 2, continues wait command from machine.
2. the high-speed synchronous serial data transmission method of a kind of one master and multiple slaves mode as claimed in claim 1, is characterized in that: the code encoding/decoding mode of described synchronous serial-data transmission is, the data of transmission and communication clock is modulated on a holding wire.
3. the high-speed synchronous serial data transmission method of a kind of one master and multiple slaves mode as claimed in claim 2, is characterized in that: described coded system is, is after the coding of 0 be 1000 before coding, is after the coding of 1 be 1110 before coding.
4. the high-speed synchronous serial data transmission method of a kind of one master and multiple slaves mode as claimed in claim 3, is characterized in that: 4 codings of the corresponding 100MHz of a described code element.
5. the 1st of these four codings is " 1 ", and 2nd ~ 3 is the information of input symbols, and the 4th is " 0 ".
6. the high-speed synchronous serial data transmission method of a kind of one master and multiple slaves mode as claimed in claim 2, is characterized in that: described coded system is that CPLD encodes to data.
7. the high-speed synchronous serial data transmission method of a kind of one master and multiple slaves mode as claimed in claim 2, it is characterized in that: described decoding process is that receiving terminal extracts synchronised clock by RC delay circuit, then utilizes synchronised clock to the decoding data received.
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| CN106201972A (en) * | 2016-07-01 | 2016-12-07 | 西安交大能源电子技术开发公司 | A kind of high speed serial communication method being applicable to low cost child node |
| CN106980301A (en) * | 2017-03-08 | 2017-07-25 | 北京数码大方科技股份有限公司 | Communication means and device |
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| CN109407752A (en) * | 2018-12-20 | 2019-03-01 | 上海欧秒电力监测设备有限公司 | The synchronous GIS breaker on-line monitoring system of clock is realized in RS485 communication |
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