CN109150355B - System for realizing PTP network card under FPGA - Google Patents
System for realizing PTP network card under FPGA Download PDFInfo
- Publication number
- CN109150355B CN109150355B CN201810923439.XA CN201810923439A CN109150355B CN 109150355 B CN109150355 B CN 109150355B CN 201810923439 A CN201810923439 A CN 201810923439A CN 109150355 B CN109150355 B CN 109150355B
- Authority
- CN
- China
- Prior art keywords
- ptp
- network card
- pcie
- ieee1588
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 claims abstract description 20
- 108700009949 PTP protocol Proteins 0.000 claims abstract description 7
- 238000001514 detection method Methods 0.000 claims description 7
- 230000000737 periodic effect Effects 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 claims description 4
- 238000013461 design Methods 0.000 abstract description 5
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 5
- 238000012360 testing method Methods 0.000 description 3
- 101100283411 Arabidopsis thaliana GMII gene Proteins 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101100126329 Mus musculus Islr2 gene Proteins 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention provides a system for realizing PTP network card under FPGA, comprising: an input module for receiving an ethernet data stream; the processing module is used for processing Ethernet data flow PCIe data flow and IEEE1588 protocol message; and the output module is used for providing the Ethernet data stream, the timestamp of IEEE1588 and a related control register to a user through a PCIe bus, and the user realizes network card drive, TCP/IP and PTP protocol stack in an operating system. The invention designs the multifunctional board card integrating data transmission, time synchronization and frequency synchronization, and can meet various time synchronization application scenes and services; the PCIe network card is realized through the FPGA chip, and a special network card chip is expected to be partially replaced, so that the cost is reduced.
Description
Technical Field
The invention relates to the field of network communication systems, in particular to a system for realizing a PTP network card under FPGA.
Background
The ieee 588 is called as "Precision clock synchronization protocol standard of network measurement and control system", PTP (Precision Time protocol 01) for short. Typical application areas for PTP are measurement and control systems, industrial automation, electrical systems and distributed motion control systems. Time unification is the basis for the cooperative work of the devices and the systems distributed at different positions. The synchronization time precision of the NTP protocol and the SNTP protocol can only reach dozens of milliseconds or even lower than dozens of milliseconds, which is far from meeting the requirement of the current network, so that the standard with higher time precision needs to be searched to solve the problem. The IEEE1588 standard is established to solve the time synchronization problem of some devices in the industrial field, and has synchronization precision with relatively good performance.
The invention adopts a design method of Xilinx IEEE1588, Ethernet and IP core combination of PCIE interfaces to realize the PCIE time synchronization PTP network card, enriches the functions and the speciality of the board card, supports 1PPS input and output and periodic pulse input and output, and is used for the application scenes of time synchronization performance test and frequency synchronization.
Disclosure of Invention
Aiming at the defects and the requirements on application in the prior art, the technical problems to be solved by the invention are embodied in the following points: a PTP time synchronization board card is utilized to provide high-precision time synchronization of microsecond-level errors for a user; the PTP time synchronization board card simultaneously supports the functions of transmitting service data and PTP time synchronization; the PTP synchronization board card provides periodic pulse input and output functions for frequency synchronization.
The invention is realized according to the following technical scheme:
utilize FPGA to realize the system of PTP network card, characterized by, including:
an input module for receiving an ethernet data stream;
the processing module is used for processing Ethernet data flow PCIe data flow and IEEE1588 protocol message;
and the output module is used for providing the Ethernet data stream, the timestamp of IEEE1588 and a related control register to a user through a PCIe bus, and the user realizes network card drive, TCP/IP and PTP protocol stack in an operating system.
In the above technical solution, the input module includes an RJ45 interface and a physical interface transceiver (PHY) supporting a 10/100/1000Mb communication rate, and is connected to an ethernet Media Access Controller (MAC) IP core of the FPGA through a media independent interface, and is used as a physical link for transmitting and receiving a packet.
In the above technical solution, the processing module includes:
the business data processing module caches data flow of the media independent interface or the gigabit Ethernet interface into the tail part of the circular queue, PCIe fetches data from the head part of the queue and stores the data into a PCIe data space, and a CPU reads the data and transmits an upper protocol stack;
the IEEE1588 time synchronization module is used for PTP message detection function, hardware timestamp generation and time adjustment, wherein PTP message detection is that IEEE1588 messages are scanned and correctly identified from data streams of a media independent interface or a gigabit Ethernet interface and are submitted to an upper PTP protocol stack for processing; the hardware timestamp refers to adding a timestamp field to the PTP message between the MAC layer and the PHY layer, so that delay and jitter of a protocol stack are effectively eliminated, and actual sending and receiving time of the IEEE1588 message is reflected; the time adjustment is the time for updating the local by the current network card according to the link round trip delay and the time offset of the PTP server.
And the frequency time setting module controls the input and output of pulse signals by using the accurate time generated by the IEEE1588 time setting module, and the PTP network card outputs a control command to the selector through the comparator according to a 32-bit nanosecond count value output by the hardware timestamp, so that a pulse per second (1PPS) signal, a periodic pulse signal (Period [1:0]) and a trigger signal (Triger [1:0]) are output. The externally input 1PPS pulse and Event signal (Event [1:0]) triggers an interrupt by the rising edge of the level, which is then passed to the MSI interrupt processing of the IP core for PCIe.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following beneficial effects:
the invention designs the multifunctional board card integrating data transmission, time synchronization and frequency synchronization, and can meet various time synchronization application scenes and services; the PCIe network card is realized through the FPGA chip, and a special network card chip is expected to be partially replaced, so that the cost is reduced.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a block diagram of a system architecture for implementing a PTP network card under an FPGA of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1, the invention provides a system for implementing a PTP network card under an FPGA, which mainly analyzes the principles of a PTP message detection module and a hardware timestamp module in the present solution, and stamps a timestamp at a GMII interface between an MAC and a PHY to eliminate delay and jitter of a protocol stack, thereby greatly improving synchronization accuracy; the resolution of the hardware timestamp is 10ns, so the design scheme of the invention can realize nanosecond synchronization precision. The system comprises:
an input module for receiving an ethernet data stream;
the processing module is used for processing Ethernet data flow PCIe data flow and IEEE1588 protocol message;
and the output module is used for providing the Ethernet data stream, the timestamp of IEEE1588 and a related control register to a user through a PCIe bus, and the user realizes network card drive, TCP/IP and PTP protocol stack in an operating system.
The input module comprises an RJ45 interface and a 10/100/1000Mb physical layer PHY chip, is connected with an MAC layer IP core of the FPGA through a media independent interface (MII interface) or a gigabit Ethernet interface (GMII interface), and is used for a physical link for receiving and transmitting messages.
In an embodiment of the present invention, the processing module includes:
the business data processing module caches data flow of the media independent interface or the gigabit Ethernet interface into the tail part of the circular queue, PCIe fetches data from the head part of the queue and stores the data into a PCIe data space, and a CPU reads the data and transmits an upper protocol stack;
the IEEE1588 time synchronization module is used for PTP message detection function, hardware timestamp generation and time adjustment, wherein PTP message detection is that IEEE1588 messages are scanned and correctly identified from data streams of a media independent interface or a gigabit Ethernet interface and are submitted to an upper PTP protocol stack for processing; the hardware timestamp refers to adding a timestamp field to the PTP message between the MAC layer and the PHY layer, so that delay and jitter of a protocol stack are effectively eliminated, and actual sending and receiving time of the IEEE1588 message is reflected;
the frequency time setting module controls input and output of pulse signals by using accurate time generated by the IEEE1588 time setting module, the PTP network card outputs a control command to the selector through the comparator according to a 32-bit nanosecond counting value output by the timestamp, so that a pulse per second (1PPS) signal, a periodic pulse signal (Period [1:0]) and a trigger signal (Triger [1:0]) are output, an externally input 1PPS pulse and an Event signal (Event [1:0]) trigger interruption through a rising edge of a level, and then the interruption is transmitted to MSI interruption processing of an IP core of PCIe.
In addition, the higher the working frequency of the counter of the network card timestamp module is, the higher the resolution of the network card timestamp is, but in practical engineering, the frequency is limited by the performance of the FPGA device and a local crystal oscillator, and cannot be increased without limit, otherwise, not only the synchronization performance cannot be increased, but also the system cannot work normally because the frequency cannot be reached. The invention adopts 50Mhz crystal oscillator to access FPGA and uses the frequency doubled to 100Mhz through internal DCM as the clock signal of the network card time counter. And accumulating at the rising edge of each clock, wherein each accumulated value is 10ns, namely the resolution of the network card time stamp is 10 ns. When the power is started, the time stamp module needs initial time, the CPU sends a time updating command and writes the time to be updated into the time stamp register, the counter starts to update the network card time, and then accumulation is started on the basis. When the CPU sends a command of adjusting the local time, the timestamp module adjusts the time of the network card by reading the time deviation so as to synchronize the master clock.
The invention adopts hardware description language (VHDL) to complete the design, compiles under the ISE10.1 software development environment of xi linx, adopts Synplify Pro synthesis, writes test excitation files to complete the simulation in Modesim se 6.2, then tests on a KC705 development board, writes and loads PCIe network card driver and protocol stack on a Linux host platform, and completes the verification and test of the whole functional module.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (2)
1. A system for realizing PTP network card under FPGA is characterized by comprising:
an input module for receiving an ethernet data stream;
the processing module is used for processing Ethernet data flow PCIe data flow and IEEE1588 protocol message;
the output module is used for providing Ethernet data stream, the timestamp of IEEE1588 and a related control register to a user through a PCIe bus, and the user realizes network card drive, TCP/IP and PTP protocol stack in an operating system;
the processing module comprises:
the business data processing module caches data flow of the media independent interface or the gigabit Ethernet interface into the tail part of the circular queue, PCIe fetches data from the head part of the queue and stores the data into a PCIe data space, and a CPU reads the data and transmits an upper protocol stack;
the IEEE1588 time synchronization module is used for PTP message detection function, hardware timestamp generation and time adjustment, wherein PTP message detection is that IEEE1588 messages are scanned and correctly identified from data streams of a media independent interface or a gigabit Ethernet interface and are submitted to an upper PTP protocol stack for processing; the hardware timestamp refers to adding a timestamp field to the PTP message between the MAC layer and the PHY layer, so that delay and jitter of a protocol stack are eliminated, and actual sending and receiving time of the IEEE1588 message is reflected; the time adjustment is that the current PTP network card updates local time according to the round trip delay of a link and the time deviation of a PTP server;
the PTP network card outputs a control command to the selector through the comparator according to a 32-bit nanosecond counting value output by the hardware timestamp, so that a pulse per second signal, a periodic pulse signal and a trigger signal are output; the external input semaphores and event signals trigger interrupts by rising edges in the level, which are then passed to the MSI interrupt processing of the IP core for PCIe.
2. The system for realizing the PTP network card under the FPGA according to claim 1, wherein the input module comprises an RJ45 interface and a 10/100/1000Mb physical layer PHY chip, and is connected with an MAC layer IP core of the FPGA through a media independent interface or a gigabit Ethernet interface, and is used for a physical link for receiving and transmitting messages.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810923439.XA CN109150355B (en) | 2018-08-14 | 2018-08-14 | System for realizing PTP network card under FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810923439.XA CN109150355B (en) | 2018-08-14 | 2018-08-14 | System for realizing PTP network card under FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109150355A CN109150355A (en) | 2019-01-04 |
| CN109150355B true CN109150355B (en) | 2020-04-24 |
Family
ID=64792977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810923439.XA Active CN109150355B (en) | 2018-08-14 | 2018-08-14 | System for realizing PTP network card under FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109150355B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112994818B (en) * | 2019-12-18 | 2022-12-16 | 海信视像科技股份有限公司 | Time synchronization method and display device |
| CN112436948B (en) * | 2020-11-12 | 2023-04-18 | 中国铁道科学研究院集团有限公司 | Train Ethernet card based on TSN and data receiving and transmitting method |
| CN112904932A (en) * | 2021-05-08 | 2021-06-04 | 鹏城实验室 | Clock synchronization method, board card, computer storage medium and terminal equipment |
| CN114844590A (en) * | 2022-04-24 | 2022-08-02 | 中国科学院精密测量科学与技术创新研究院 | PTP hardware timestamp processing method based on FPGA |
| CN114968893B (en) * | 2022-07-27 | 2022-09-30 | 井芯微电子技术(天津)有限公司 | PCIe message queue scheduling method, system and device based on timestamp |
| CN116028426B (en) * | 2023-03-28 | 2023-08-15 | 无锡沐创集成电路设计有限公司 | Multi-PCIe access network card and single-port network card driving method for uploading messages |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388741B (en) * | 2008-10-24 | 2012-12-12 | 中国科学院计算技术研究所 | Highly precised time synchronization device, system and method for computer network |
| CN101739011B (en) * | 2009-12-08 | 2012-09-05 | 中国科学院声学研究所 | CPCI bus-based high-accuracy clock synchronization method and system thereof |
| CN101800648A (en) * | 2010-01-27 | 2010-08-11 | 成都天奥电子有限公司 | Ethernet card with NTP and PTP function and method for realizing same |
| US8879552B2 (en) * | 2012-02-22 | 2014-11-04 | Telefonaktiebolaget L M Ericsson (Publ) | Precision time protocol offloading in a PTP boundary clock |
| CN104901844B (en) * | 2015-05-13 | 2019-01-22 | 国家计算机网络与信息安全管理中心 | High Precision Time Stamps acquisition methods, device and network interface card based on PCIE |
-
2018
- 2018-08-14 CN CN201810923439.XA patent/CN109150355B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109150355A (en) | 2019-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109150355B (en) | System for realizing PTP network card under FPGA | |
| US7835402B2 (en) | Synchronization module | |
| KR102652569B1 (en) | Implementation of PHY-level hardware timestamping and time synchronization in cost-optimized environments | |
| US8325767B2 (en) | Enhancement of IEEE 1588 synchronization using out-of-band communication path | |
| US7573914B2 (en) | Systems and methods for synchronizing time across networks | |
| US20100189206A1 (en) | Precise Clock Synchronization | |
| EP3531610B1 (en) | Frequency synchronization method and slave clock | |
| US11979481B2 (en) | Time synchronisation | |
| CN108259109B (en) | Network equipment in PTP domain and TOD synchronization method | |
| CN104378193A (en) | Time synchronization system and method, exchanger and embedded interface board | |
| JP2013106329A (en) | Communication apparatus | |
| EP3174237B1 (en) | Time synchronization method and apparatus for network devices and time synchronization server | |
| CN111147176A (en) | High-precision time synchronization system based on IEEE1588 protocol | |
| Dong et al. | The design and implementation of ieee 1588v2 clock synchronization system by generating hardware timestamps in mac layer | |
| CN101800648A (en) | Ethernet card with NTP and PTP function and method for realizing same | |
| Ohly et al. | Hardware assisted precision time protocol. Design and case study | |
| CN117320144A (en) | Primary and secondary clock time synchronization method and system based on wireless communication | |
| Horauer | Clock synchronization in distributed systems | |
| JP2016184811A (en) | Synchronous message transmission device, time synchronization system, synchronous message transmission method, and program | |
| CN101359985A (en) | Embedded system based on LXI equipment accurate time synchronization protocol | |
| CN116346272A (en) | IEEE802.1AS clock synchronization system based on cooperation of PS end and PL end of Xilinx | |
| CN214480655U (en) | Embedded equipment compatible with definable deterministic communication Ethernet | |
| Deev et al. | Subnanosecond synchronization method based on the synchronous Ethernet network | |
| Hartwich | CAN frame time-stamping—Supporting AUTOSAR time base synchronization | |
| CN111865467A (en) | Clock synchronization system and method between distributed chassis board cards for time delay test |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |