CN114844590A - PTP hardware timestamp processing method based on FPGA - Google Patents

Abstract

The invention discloses a PTP hardware timestamp processing method based on FPGA, wherein a hardware timestamp unit carries out hardware timestamp on a data frame from PHY under the drive of a receiving clock and provides timestamp data to an interface signal processing unit at any time; the interface signal processing unit detects effective signals, collision detection signals, carrier detection signals, error signals of received data and 8-bit received data from the PHY under the drive of the receiving clock and delays 1 receiving clock to send to the MAC, after all the received data sent by the PHY are transmitted to the MAC, the interface signal processing unit sends timestamp data as the received data to the MAC.

Description

PTP hardware timestamp processing method based on FPGA

Technical Field

The invention relates to the technical field of time and frequency synchronization, in particular to a PTP hardware timestamp processing method based on an FPGA, which is suitable for a PTP technology-based time service network system.

Background

The PTP Protocol (Precision Time Protocol), also called IEEE1588 Protocol, is a high-Precision network timing Protocol. With the vigorous development of the ethernet technology, a PTP technical protocol established based on the ethernet adopts a hardware timestamp mode, overcomes the bottleneck of the NTP technology, and improves the clock synchronization precision to a sub-microsecond level, so that the PTP technical protocol is widely applied to the military and civil dual-purpose fields of measuring instruments, intelligent rail transit, intelligent power grids, communication engineering and the like.

The hardware approach of PTP has long been popular. Common hardware timestamp markers in the market generally use a PTP function of a physical layer PHY chip, or a timestamp unit constructed by an FPGA is adopted to mark a timestamp and cache the timestamp into an FIFO (first in first out) for fetching, and all functions of PTP can be realized; of course, some schemes also use PTP functions in processor-integrated MAC to realize precise time service, but usually only some functions of PTP are supported, and not all functions of PTP are realized.

In the above several implementation schemes of full-function PTP, the timestamp data of the PTP event message from the network is cached first and then waits for the processor running the PTP protocol stack to acquire the timestamp data. When facing a plurality of PTP node clocks, the arrival of a large number of PTP event messages may cause the processor to be replaced by new timestamp data instead of acquiring corresponding "cache" timestamp data, thereby generating a large time error. The processing method for hardware timestamp marking of the message from the network can effectively avoid the condition that timestamp data cannot be corresponded, thereby realizing high throughput and reliable PTP time service.

Disclosure of Invention

The invention aims to provide a PTP hardware timestamp processing method based on FPGA aiming at the problems in the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

a PTP hardware timestamp processing method based on FPGA comprises the following steps:

step 1, the interface signal processing unit and the hardware timestamp unit are all driven by a receiving clock RX _ CLK generated by a PHY, after the interface signal processing unit detects the rising edge of a receiving data effective signal RX _ DV sent by the PHY, 1 receiving clock RX _ CLK is delayed for the receiving data effective signal RX _ DV, a collision detection signal COL, a carrier detection signal CRS, a receiving data error signal RX _ ER and 8-bit receiving data RXD [7:0], and corresponding receiving data effective delay signal SP _ RX _ DV, a collision detection delay signal SP _ COL, a carrier detection delay signal SP _ CRS, a receiving data error delay signal SP _ RX _ ER and delayed receiving data SP _ D [7:0] are generated and sent to the MAC; the hardware time stamping unit generates 64-bit time stamping data TS [63:0] after detecting the rising edge of a receiving data effective signal RX _ DV from the PHY; the interface signal processing unit reads the 64-bit time stamp data TS [63:0] at the rising edge of the 2 nd receiving clock RX _ CLK after the receiving data valid signal RX _ DV of the PHY is pulled high;

step 2, after detecting the falling edge of a received data effective signal RX _ DV sent by the PHY, the interface signal processing unit continuously keeps the received data effective delay signal SP _ RX _ DV at a high level, divides 64-bit timestamp data TS [63:0] acquired from the hardware timestamp unit into timestamp segment data of 8 bits respectively, and sequentially sends the timestamp segment data serving as delayed received data SP _ RXD [7:0] to the MAC; after 8 receiving clocks RX _ CLK, 64-bit time stamp data TS [63:0] are transmitted to MAC from the interface signal processing unit, and the interface signal processing unit sets SP _ RX _ DV to be low level;

and step 3, after the interface signal processing unit detects the falling edge of the carrier detection signal CRS sent by the PHY, the interface signal processing unit continuously keeps the SP _ CRS high level, and after 8 receiving clocks RX _ CLK, the interface signal processing unit sets the carrier detection delay signal SP _ CRS to be low level.

Through the processing, the Ethernet messages received by the MAC side all include corresponding 64-bit hardware timestamp data, and the timestamp data are transmitted to an application layer along with the messages and are used by a PTP (precision time protocol) stack of the application layer.

Compared with the prior art, the invention has the following beneficial effects:

hardware timestamp data along with the messages have a one-to-one correspondence relationship, an application layer PTP protocol stack processes according to actual needs, and the problem that the timestamp data and the messages cannot be in one-to-one correspondence due to too low processing speed is avoided, so that high-throughput and reliable PTP time service is achieved.

Drawings

Fig. 1 is a schematic diagram of the principle in the example.

FIG. 2 is a timing diagram of signals according to an embodiment.

Detailed Description

The present invention will be described in further detail with reference to examples for the purpose of facilitating understanding and practice of the invention by those of ordinary skill in the art, and it is to be understood that the present invention has been described in the illustrative embodiments and is not to be construed as limited thereto.

A PTP hardware timestamp processing method system based on FPGA comprises an MAC, an interface signal processing unit, a hardware timestamp unit and a PHY.

In fig. 1, PHY is a physical layer transceiver chip and MAC is a medium access controller. The invention only relates to the marking and processing of the hardware timestamp of the message from the Ethernet end, and does not relate to the marking and processing process of the hardware timestamp of the message sent to the Ethernet end, so the principle schematic diagram only comprises the receiving end signal of the GMII interface. As a preferred scheme, the interface signal processing unit and the hardware time stamp unit are both implemented in an FPGA and located between the PHY and the MAC. The interface signal processing unit detects and processes a collision detection signal COL, a carrier detection signal CRS, a received data error signal RX _ ER, 8-bit received data RXD [7:0] and a received data valid signal RX _ DV from the PHY under the drive of a receiving clock RX _ CLK, and then outputs the signals to the MAC; the delayed collision detection signal COL, the carrier detection signal CRS, the received data error signal RX _ ER, the 8-bit received data RXD [7:0] and the received data valid signal RX _ DV are respectively called a collision detection delay signal SP _ COL, a carrier detection delay signal SP _ CRS, delayed received data SP _ RXD [7:0], a received data error delay signal SP _ RX _ ER and a received data valid delay signal SP _ RX _ DV signal. The hardware time stamping unit detects and time stamps the valid RX _ DV driven by the RX _ CLK and provides 64 bits of time stamp data TS [63:0] to the interface signal processing unit at any time.

Fig. 2 is a timing diagram of signals such as a collision detection signal COL, a carrier detection signal CRS, 8-bit received data RXD [7:0], a received data error signal RX _ ER, a received clock RX _ CLK, and a received data valid signal RX _ DV entering the interface signal processing unit, and signals such as a collision detection delay signal SP _ COL, a carrier detection delay signal SP _ CRS, delayed received data SP _ RXD [7:0], a received data error delay signal SP _ RX _ ER, and a received data valid delay signal SP _ RX _ DV output after processing by the interface signal processing unit.

A PTP hardware timestamp processing method based on FPGA comprises the following steps:

step 1, the interface signal processing unit and the hardware time stamp unit are all driven by a receiving clock RX _ CLK generated by the PHY. According to the GMII interface protocol, whenever the PHY receives a new frame of ethernet packet, the RX valid signal RX _ DV is pulled high until the packet is received and then pulled low. After detecting the rising edge of a received data valid signal RX _ DV sent by the PHY, the interface signal processing unit delays 1 receiving clock RX _ CLK from the received data valid signal RX _ DV, a collision detection signal COL, a carrier detection signal CRS, a received data error signal RX _ ER and 8-bit received data RXD [7:0] of the PHY, generates a corresponding received data valid delay signal SP _ RX _ DV, a corresponding collision detection delay signal SP _ COL, a corresponding carrier detection delay signal SP _ CRS, a corresponding received data error delay signal SP _ RX _ ER and corresponding delayed received data SP _ RXD [7:0] and sends the signals to the MAC; after detecting the rising edge of a receiving data valid signal RX _ DV from the PHY, the hardware time stamp unit generates 64-bit time stamp data TS [63:0] to wait for the acquisition of the interface signal processing unit; the interface signal processing unit reads the 64-bit time stamp data TS [63:0] at the 2 nd rising edge of the reception clock RX _ CLK after the reception data valid signal RX _ DV of the PHY is pulled high.

Step 2, after detecting the falling edge of the received data valid signal RX _ DV sent by the PHY, the interface signal processing unit continuously keeps the received data valid delay signal SP _ RX _ DV at a high level, and divides 64-bit time stamp data TS [63:0] acquired from the hardware time stamp unit into 8-byte time stamp segment data of TS [63:56], TS [55:48], TS [47:40], TS [39:32], TS [31:24], TS [23:16], TS [15:8] and TS [7:0], and the interface signal processing unit sequentially sends each time stamp segment data to the MAC as delayed received data SP _ RXD [7:0 ]; after 8 receiving clocks RX _ CLK, the divided 64-bit time stamp data TS [63:0] (namely each time stamp segment data) is transmitted to MAC from the interface signal processing unit, and the interface signal processing unit sets SP _ RX _ DV to be low level;

and 3, after detecting the falling edge of a carrier detection signal CRS sent by the PHY, the interface signal processing unit continues to keep the SP _ CRS high level, the carrier detection signal CRS is kept consistent with a received data effective signal under the normal condition, namely the carrier detection signal CRS and the received data effective signal RX _ DV are synchronously set to be high and low, and after 8 receiving clocks RX _ CLK are passed (namely 64-bit timestamp data TS [63:0] is completely transmitted), the interface signal processing unit sets the carrier detection delay signal SP _ CRS to be low level.

It should be noted that, in the present invention, the processing procedure is the same whether the MAC and PHY use GMII/MII interface or RGMII/RMII interface. Therefore, the present invention only uses the GMII interface as an example to detail the processing procedure.

The specific embodiments described herein are merely illustrative of the invention. Various modifications, additions and substitutions may be made by those skilled in the art to which the invention pertains without departing from the spirit of the invention or exceeding the scope of the claims defined thereby.

Claims (1)

1. A PTP hardware timestamp processing method based on FPGA is characterized by comprising the following steps:

step 1, the interface signal processing unit and the hardware timestamp unit are all driven by a receiving clock RX _ CLK generated by a PHY, after the interface signal processing unit detects the rising edge of a receiving data effective signal RX _ DV sent by the PHY, 1 receiving clock RX _ CLK is delayed for the receiving data effective signal RX _ DV, a collision detection signal COL, a carrier detection signal CRS, a receiving data error signal RX _ ER and 8-bit receiving data RXD [7:0], and corresponding receiving data effective delay signal SP _ RX _ DV, a collision detection delay signal SP _ COL, a carrier detection delay signal SP _ CRS, a receiving data error delay signal SP _ RX _ ER and delayed receiving data SP _ D [7:0] are generated and sent to the MAC; the hardware time stamping unit generates 64-bit time stamping data TS [63:0] after detecting the rising edge of a receiving data effective signal RX _ DV from the PHY; the interface signal processing unit reads the 64-bit time stamp data TS [63:0] at the rising edge of the 2 nd receiving clock RX _ CLK after the receiving data valid signal RX _ DV of the PHY is pulled high;

step 2, after detecting the falling edge of a received data effective signal RX _ DV sent by the PHY, the interface signal processing unit continuously keeps the received data effective delay signal SP _ RX _ DV at a high level, divides 64-bit timestamp data TS [63:0] acquired from the hardware timestamp unit into 8-bit timestamp segment data, and sequentially sends the timestamp segment data serving as delayed received data SP _ RXD [7:0] to the MAC; after 8 receiving clocks RX _ CLK, the interface signal processing unit sets SP _ RX _ DV to be at a low level;

and step 3, after the interface signal processing unit detects the falling edge of the carrier detection signal CRS sent by the PHY, the interface signal processing unit continuously keeps the SP _ CRS high level, and after 8 receiving clocks RX _ CLK, the interface signal processing unit sets the carrier detection delay signal SP _ CRS to be low level.

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