CN101252404A - Distributed network clock synchronizing system and method based on FPGA - Google Patents
Distributed network clock synchronizing system and method based on FPGA Download PDFInfo
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Abstract
The invention requests to protect a small-size distributed network clock synchronization system based on a field programmable gate array (FPGA), which relates to the distributed network synchronization technique. The synchronization system comprises a PC, a HUB and a distributed unit based on the FPGA; each distributed unit is provided with a general network interface; the fixed synchronization cycle time proposal is adopted to realize the clock synchronization of the small-size distributed network, enabling the system to reach the microsecond grade synchronization. The synchronization mode adopted in the small-size distributed network clock synchronization system is similar to the mode of the IEEE1588 standards; based on the high accuracy synchronization property of the IEEE1588 standards, the initial synchronization speed of the synchronization system is improved so that a distributed system which has the advantages of high initial synchronization speed and high accuracy clock synchronization is realized. The network clock synchronization system provides each composite unit of the distributed network system with synchronization clock used as the reference of the working clock of the system; thereby, the small-size distributed network clock synchronization system is applicable to the distributed network which has high real-time requirement for data transmission.
Description
Technical field
The present invention relates to Computer Control Technology, relate in particular to the distributed network simultaneous techniques.
Background technology
Along with development of computer network, the expanded range of distributed system and dispersion more become more and more important by the real-time between the decentralized control node of net connection.Influence mainly have its source in the timing differential and transmission delay and the shake of measuring and control data in network between each measuring and controlling equipment of real-time distributed systems.These problems are that distributed system is intrinsic, and the key that addresses these problems is exactly a time synchronized, and the purpose of time synchronized will be delivered to time reference point each control point of network exactly exactly.Popular method for synchronous has both at home and abroad at present: the accurate clock synchronization protocol IEEE1588 standard of simple time synchronization protocol SNTP, networking measurement and control system etc.
1, simple time synchronization protocol SNTP can also can operate under the ip multicast mode with mode of unicast (point-to-point) and broadcast mode (point-to-multipoint) operation.But the time precision of SNTP depends on the situation of client and service end network, adopts this method of synchronization can reach the precision of 0.5～2ms in distributed system.Under the situation that the system that takes a flight test that has relatively high expectations synchronously, industry are gathered and controlled, this synchronous precision can not reach requirement far away.
2, IEEE1588 standard, defined one be suitable for measure and automated system in the clock synchronization protocol that uses, the highest clock synchronization that can realize the superhigh precision of microsecond magnitude is higher than the precision of other network time synchronization agreements.But this standard is also quite high to the requirement of network, is suitable for having only the operational environment of Ethernet.And join in the network or during change of network environment, network needs synchronous again as new unit, it is long to finish the synchronous time.In the system of Unit 2, finish subsynchronous needs 10 secondary lines and postpone, and along with the increase of lock unit, finishing the synchronous time will increase exponentially.
Along with computer and development of electronic technology, the FPGA technology has obtained using widely and is quite ripe, FPGA has also increased High Speed I/O, embedded memory, special-purpose phase-locked loop (PLL) and flush bonding processor, also exists the pre-design circuit module that presents with IP kernel in a large number at present.
Secondly programmable system SOPC (System On a Programmable Chip) is the convergent point and the developing direction of modern electronic technology and electronic system design on the sheet.SOPC combines SOC and PLD, FPGA advantage separately, integrated stone or soft nucleus CPU, OSP, memory, peripheral I/O and FPGA (Field Programmable Gate Array), the user can utilize the SOPC platform to design the CPU processor of high speed, high performance dsp processor or specific function voluntarily, thereby makes electronic system design enter a brand-new pattern.
Adopt the FPGA technology to realize the distributed network clock synchronization, can satisfy the clock synchronization of following between networks of different protocol, the synchronization accuracy height, the increase of lock unit can significantly not increase the synchronous time.Improved network work efficient.
Summary of the invention
Technical problem to be solved by this invention is, network environment is required high at the distributed network clock synchronizing system that exists in the prior art, the defective that lock in time is long, design a kind of distributed network clock synchronizing system, to realize that network enters synchronous regime fast and high accuracy clock is synchronous based on FPGA.
The technical scheme that the present invention solves the problems of the technologies described above is, proposes a kind of distributed network clock synchronizing system based on FPGA, and this distributed network clock synchronizing system comprises control and processing section, clock synchronization part, tcp data segment.
Described control and processing section comprise network center's control and treatment part and each distributed unit control and treatment part, each distributed unit control and treatment part all is to be the unit of core with FPGA, be embedded with 1 microprocessor among the FPGA, each distributed unit realizes in real time synchronously in the Control Network, and timing sends to data in the distributed network or receives the data that other distributed unit sends.
Network center's control and treatment part is implemented control and treatment by main control computer and supervisory control comuter, comprises computer detecting part, computer configuration part and packet test section.
Computer detecting part: main control computer sends detecting data, in the detecting network how many distributed unit is arranged; The computer configuration part: main control computer sends configuration data, disposes each distributed unit function, and definition comprises that work period, data produce constantly, data produce frequency and data delivery time etc.; The packet test section: after system entered real-time working (beginning to carry out transfer of data), master control and supervisory control comuter were finished the monitoring to packet.
Described clock synchronization partly comprises 1 main distributed unit MASTER and a plurality of from distributed unit SLAVER, by in fact the time control module realize between the master and slave distributed unit synchronously.Receive, send the time interval of message according to it and from the distributed unit unit number from the real-time control module of distributed unit, calculating respectively postpones Delay from the network line of distributed unit, according to respectively determining that from the network line delay of distributed unit the clock of MASTER unit and SLAVER unit makes zero constantly, MASTER unit and each SLAVER unit are made zero at the synchronization clock.
Like this, a plurality of terminals can be carried out synchronously simultaneously, so this is a kind of network clocking method of synchronization that is fit to more frequent distributed system multiple terminals synchronizing cycle more.
Described tcp data segment adopts the Ethernet transmission means, and Asynchronous Mode transmits detecting, configuration data down, initiates message etc. synchronously, and synchronous mode is each distributed unit real time data of transmission down.
The present invention also proposes a kind of distributed network clock synchronizing method based on FPGA, and main distributed unit sends to network and initiates message synchronously; Respectively return the sync response message in the processing time that comprises its unit number, sends and receive between the packet from distributed unit; Main distributed unit is according to the time interval and processing time, and calculating respectively postpones from the network line of distributed unit; Again according to line delay notice from distributed unit synchronous zero hour.
This method comprises the steps:
1, the MASTER unit sends to the SLAVER unit and initiates message synchronously;
2, the message of MASTER unit is received in the SLAVER unit, returns a sync response message, and this message has MASTER unit unit number and message processing time (from receiving that message is to the time the returned packet);
3, after the sync response message is received in the MASTER unit, according to sending message and receiving that the moment computational scheme of message postpones;
4, the MASTER unit sends to the SLAVER unit according to line delay and begins bag synchronously;
5, MASTER unit and all SLAVER unit while clock makes zero.
This distributed network clock synchronizing system adopts the distributed network clock based on FPGA, realized the high-precise synchronization of this distributed system in network, can satisfy the system of taking a flight test, high accuracy industry collection and the needs of controlling distributed real-time data acquisition and control, and changing in initial synchronisation or network environment need be again synchronously the time, can realize entering fast synchronous regime.Native system is not as long as each cell data delivery time conflicts, and the data that system can gather each are very accurately constantly delivered to appointed positions, and transmission is reliable, antijamming capability is strong, good stability, real-time and compatible strong.Show through practical application, this system clock synchronously, data acquisition and handle by FPGA and realize, not only can realize the time synchronized of microsecond level, and the required time of initial synchronisation of distributed system is reduced greatly.Working stability, reliable; Data communication can be finished in real time.
Description of drawings
Accompanying drawing 1: distributed system framework
Accompanying drawing 2: each distributed unit architecture
Accompanying drawing 3:2 units synchronization fundamental diagram
Accompanying drawing 4: multiple unit synchronous working schematic diagram
Accompanying drawing 5:MASTER cell processing flow chart
Accompanying drawing 6:SLAVER cell processing flow chart
Specific embodiments
The present invention proposes a kind of distributed network clock synchronizing system based on FPGA, and this distributed network clock synchronizing system comprises control and processing section, clock synchronization part, tcp data segment.
Control comprises network center's control and treatment part and each distributed unit control and treatment part with the processing section, each distributed unit control and treatment part all is to be the unit of core with FPGA, be embedded with 1 microprocessor among the FPGA, each distributed unit realizes in real time synchronously in the Control Network, and timing sends to data in the distributed network or receives the data that other distributed unit sends.Network center's control and treatment part is implemented control and treatment by main control computer and supervisory control comuter, comprises computer detecting part, computer configuration part and packet test section.Computer detecting part: main control computer sends detecting data, in the detecting network how many distributed unit is arranged; The computer configuration part: main control computer sends configuration data, disposes each distributed unit function, and definition comprises that work period, data produce constantly, data produce frequency and data delivery time etc.; The packet test section: after system entered real-time working, begins to carry out transfer of data, master control and supervisory control comuter were finished the monitoring to packet.Clock synchronization partly comprises 1 main distributed unit MASTER and a plurality of from distributed unit SLAVER, network clocking adopts the mode of similar IEEE1588 standard synchronously, but according to the slow-footed shortcoming of its initial synchronisation, make zero simultaneously with the clock of each distributed unit and to be substituted in adjustment in the IEEE1588 standard clock skew
Like this, a plurality of terminals can be carried out synchronously simultaneously, so this is a kind of network clocking method of synchronization that is fit to more frequent distributed system multiple terminals synchronizing cycle more.
Below at accompanying drawing and instantiation enforcement of the present invention is described specifically.
Be illustrated in figure 1 as distributed network clock synchronizing system structured flowchart of the present invention.This system comprises that a main distributed unit MASTER and a plurality of (as n) are from distributed unit SLAVER, be connected to the master control and the supervisory control comuter of network center's control and treatment part between each unit respectively by hub HUB, each distributed unit (comprising MASTER and SLAVER unit) all comprises network interface and FPGA plate, is that the distributed unit control and treatment part of core connects HUB by network interface separately with FPGA.
The function of MASTER unit and SLAVER unit is except the clock synchronization part is different, and other function is all identical with structure.The MASTER unit is the clock synchronization promoter, and SLAVER follows the unit clock of MASTER unit.
Network center's control and treatment part realizes control and treatment by main control computer and supervisory control comuter, finishes to comprise computer detecting part, computer configuration part and packet test section function.How many distributed unit are the configuration packet that main control computer is responsible for sending detecting data, synch command (promptly withdrawing from state of a control) or is sent each unit have in the detecting network; Dispose each distributed unit function, definition comprises that work period, data produce constantly, data produce frequency and data delivery time etc.; After system entered real-time working (beginning to carry out transfer of data), master control and supervisory control comuter were monitored packet in real time by the packet test section.
Be illustrated in figure 2 as each distributed unit architecture.Each distributed unit control and treatment part all is to be the unit of core with FPGA, is embedded with the SOPC soft-core processor in the FPGA plate.Be provided with system configuration, functional configuration, transmission control, control in real time, UDP and modules such as collection and output.Each distributed unit realizes in real time synchronously in the Control Network, and timing sends to data in the distributed network or receives the data that other distributed unit sends.
Wherein system configuration module, functional configuration module and transmission control module all belong to application layer module, and they and collection and output module all are to be realized by FPGA.Control module, UDP module are realized by the SOPC system among the FPGA in real time.Main control computer transmitting system configuration information and functional configuration information, distributed unit deposits it among FLASH of distributed unit in after receiving the said system configuration information, distributed unit system configuration module is according to system configuration information initialization system operating state, and system configuration information comprises that system synchronization cycle, data transmitting period, data send length, Data Receiving buffer address, data delivery time; The functional configuration module is determined information such as each initial acquisition moment synchronizing cycle, data acquisition rate, data acquisition channel number, data acquisition memory address, data output buffers address according to functional configuration information.Enter the system configuration of storing among initialization or the FLASH and functional configuration information when changing when system powers on, FPGA initiatively changes systemic-function by read-write FLASH.
Transmission control module comprises transmission control module between interior transmission control module in station and station, the storage that transmission control module is gathered acquisition module under real-time status in standing is perhaps delivered to the data among the SRAM in the buffer address of output module in memory SRAM.Transmission control module will store real time data among the SRAM this moment into to be combined into UDP packet format etc. to be sent between standing under real-time status.
Control module is according to receiving synchronous initiation message Sync from the unit to the time interval Adjust and the SLAVER unit unit number that send sync response message Sync_Responce in real time, the network line that calculates each SLAVER unit postpones Delay, according to respectively postponing to determine that from the network line of distributed unit the clock of MASTER unit and SLAVER unit makes zero constantly, realize between the master and slave distributed unit synchronously.
The UDP module: UDP wraps the transmission that realizes real time data by transmission, and transfer of data is realized by control command by the SOPC soft-core processor.Its transmitting-receiving function is respectively and sends message TransmitPacket and receive message ReceivePacket.
Be example with Unit 2 and multiunit system respectively below, the Synchronization Control process of distributed network clock synchronizing system of the present invention is specifically described.
Be illustrated in figure 3 as the distributed system synchronizing process schematic diagram of Unit 2.This synchronizing process has defined 3 sync messages: initiate message Sync, sync response message Sync_Responce synchronously and begin message Sync_Start synchronously.System clock is produced by the crystal oscillator of distributed unit counting, but is 32M as the selective system crystal oscillator frequency.Flow process is as follows synchronously:
At first MASTER unit transmission control module control output module sends the Sync message to the SLAVER unit, after SLAVER cell data acquisition module is received the Sync message, transmission control module control output module comprises the SLAVER unit from receiving the Sync message to the time interval Adjust that sends the Sync_Responce message and the Sync_Responce message of SLAVER unit unit number to one of MASTER unit feedback, after the Sync_Responce message is received in the MASTER unit, determine that the MASTER unit sends Sync message and the time T m1 that receives the Sync_Responce message, Tm2, the real-time control module in MASTER unit is according to time interval Adjust and send Sync message and the time T m1 that receives the Sync_Responce message, Tm2 calls the line delay Delay of formula Delay=(Tm2-Tm1-Adjust)/2 computing network.The transmission control module of Tm3 moment MASTER unit is controlled its output module and is sent the Sync_Start message to the SLAVER unit then, and after postponing Delay clock, the Ts3 MASTER of control module control in real time unit clock constantly makes zero, after SLAVER receives the Sync_Start message in the unit simultaneously, clock also makes zero, and clock control cell picks up counting from 0.MASTER unit and SLAVER unit make zero at synchronization like this, have realized the synchronous of clock.
Adopt this method only just to finish the clock synchronization of the master-slave unit of 2 distributed unit networks by the transmission of 3 secondary lines.So when distributed system environment changes, need the synchronous again time very short, can satisfy the needs of system.
As Fig. 4 is multiunit distributed system synchronizing process schematic diagram.
When distributed system is multiple unit (n), transmission control module control output module in MASTER unit sends the Sync message in the predetermined priority blanking time all SLAVER unit in system that send, and write down delivery time respectively, after the Sync message is received by data acquisition module in each SLAVER unit, transmission control module control output module comprises the SLAVER unit from receiving the Sync message to the time interval Adjust and the SLAVER unit unit number that send the Sync_Responce message to Sync_Responce message of MASTER unit feedback in this Sync_Responce message.After MASTER cell data acquisition module is received the Sync_Responce message, calculate the line delay Delay of each SLAVER unit according to top line delay computing formula Delay=(Tm2-Tm1-Adjust)/2.Again according to the line delay of each SLAVER unit, determine to send the moment Tm4-Tmk of Sync_Start message to each SLAVER unit, the transmission control module of MASTER unit is controlled its output module and is sent the Sync_Start message to each SLAVER unit then, determine the moment that message is received in each SLAVER unit according to the line delay time of each SLAVER unit, real-time control module control MASTER unit clock makes zero when reaching the line delay of n SLAVER unit, SLAVER has received the Sync_Start message in the unit simultaneously, and clock also makes zero.MASTER unit and each SLAVER unit are made zero at the synchronization clock.
When distributed unit increases, may cause the conflict that the MASTER unit sends and receives, so can carry out synchronously SLAVER unit and MASTER unit in batches.After tested, a line delay probably is about 100000 clocks in the system, so a subsynchronous SLAVER unit can be limited in the predetermined number.Main control computer sends detecting data, in the detecting network how many distributed unit are arranged, when main control computer detects in the network SLAVER unit when surpassing predetermined number, the MASTER unit according to the Sync_Responce message that receives each SLAVER unit constantly, and the information that is comprised, the line delay of a predetermined SLAVER unit before calculating earlier, calculate the line delay of other SLAVER unit again, in real time control module is according to the line delay of all SLAVER unit in the network, and transmitting control commands makes that all distributed unit clocks make zero simultaneously in the system.
Because the deviation of clock crystal oscillator, behind system's operation certain hour, system needs again synchronously once.There is shown the various moment that system clock need make zero.As: Tsnk=0 represents to be classified as 0 from the k time clock of unit n.
Be illustrated in figure 5 as MASTER cell processing flow chart, distributed system comprises synchronous regime and asynchronous regime two states.
Under asynchronous regime, after system powered on, MASTER read the unit configuration information among the FLASH, initialization system configuration and functional configuration.MASTER cell broadcast hello bag detects on the network whether main control computer is arranged then, if do not detect main control computer or wait for that the scheduled time do not receive feedback information, system directly enters real-time status, carries out real-time Data Transmission; Receive the response bag that main control computer returns when the MASTER unit, enter the MASTER state of a control.MASTER under state of a control, main control computer to network detect, work such as system configuration and functional configuration.
Detecting: main control computer is detected the distributed unit in the network to Web broadcast UnitGet bag, and online distributed unit all can be returned a UnitInform bag to main control computer; Main control computer determines in the network how many distributed unit are arranged according to the UnitInform bag that receives.
System configuration: main control computer is to MASTER unit transmitting system configuration SysConfig bag, determine the SysConfig bag according to system configuration data, comprise that system synchronization cycle, data transmitting period, data send length, Data Receiving buffer address, data delivery time.
After MASTER receives the unit SysConfig bag, configuration data is write among its FLASH, according to each operating state of system configuration information initialization system, comprise that system synchronization cycle, data transmitting period, data send length, Data Receiving buffer address, data delivery time; Functional configuration: main control computer sends the FunConfig bag to the MASTER unit, after MASTER receives the unit FunConfig bag, configuration data is write among the FLASH, determine information such as each initial acquisition moment synchronizing cycle of each distributed unit, data acquisition rate, data acquisition channel number, data acquisition memory address, data output buffers address in the network according to functional configuration information.
After system finished detecting, configuration, main control computer sent the QuitCongfig bag, and MASTER receives the unit QuitCongfig bag that main control computer sends, and withdraws from state of a control, starts in real time, and system enters Synchronization Control process as shown in Figure 4.After system finishes synchronously, the transmission that system configuration configuration information of sending according to main control computer in the state of a control and functional configuration information realize data in the network;
If the MASTER unit does not detect main control computer, system directly enters the real-time Data Transmission state, and system realizes transfer of data according to system configuration that has deposited among the FLASH and functional configuration after realizing synchronously.Under the real-time Data Transmission state, system sends length, Data Receiving buffer address, data delivery time, each initial acquisition moment synchronizing cycle, data acquisition rate, data acquisition channel number, data acquisition memory address and data output buffers address according to synchronizing cycle, data transmitting period, data and carries out real-time Data Transmission.
In the real-time Data Transmission stage, the same by each initial acquisition moment synchronizing cycle of each distributed unit with acquisition rate, make the data acquisition of each distributed unit all the same constantly.Like this, the image data of other distributed unit that certain distributed unit is received in a data transmitting period all is that synchronization produces, and can handle the data of each distributed unit collection.
Be illustrated in figure 6 as SLAVER cell processing flow chart.When system is under the asynchronous regime, behind the system initialization, directly enter the SLAVER state of a control, do not receive the Sync bag that the MASTER unit sends as the SLAVER unit, the SLAVER unit is in the SLAVER state of a control always, at this moment, work such as main control computer can be detected the SLAVER unit, system configuration and functional configuration, the work disposal process is the same with the MASTER unit.When the MASTER unit after the SLAVER unit sends the Sync bag, SLAVER follows the unit MASTER unit and enters synchronous regime (as described in Figure 4).Synchronously, transfer of data realizes according to state of a control computer-chronograph configuration real-time status function; If state of a control does not have system configuration and functional configuration, transfer of data realizes according to system configuration among the FLASH and functional configuration.Under the real-time Data Transmission state, system sends length, Data Receiving buffer address, data delivery time, data acquisition rate, data acquisition channel number, data acquisition memory address and data output buffers address according to synchronizing cycle, data transmitting period, data and carries out real-time Data Transmission.
Define according to the form of system configuration various messages in the system.Below the form of several messages is illustrated.Network UDP package definition: (44332211 for being different from the ad hoc packets fields of other system)
Hello bag: UDP packet header+44332211+90
Response bag: UDP packet header+44332211+91
UnitGet bag: UDP packet header+44332211+99
UnitInform bag: UDP packet header+44332211+9a+ unit number (can establish the MASTER unit is 00, and the SLAVER unit is 01-ff, and each SLAVER unit unit number must be unique)
SysConfig bag: UDP packet header+44332211+01+ unit number (with the UnitInform bag)+FLASH address (2 bytes)+configuration data (system synchronization cycle+data transmitting period+data send length+data delivery time+Data Receiving buffer address)+ffffffff (configuration data end mark)
FunConfig bag: UDP packet header+44332211+01+ unit number (with the UnitInform bag)+FLASH address (2 bytes)+configuration data (data acquisition rate+data acquisition channel number+data acquisition memory address+data output buffers address)+ffffffff (configuration data end mark)
Sync message: UDP packet header+44332211+70+ unit number (with the UnitInform bag)
Sync_Responce message: UDP packet header+44332211+71+ unit number (with the UnitInform bag)+Delay (4 bytes)
Sync_Start message: UDP packet header+44332211+72+ unit number (with the UnitInform bag).
Claims (7)
1. distributed network clock synchronization system based on the FPGA technology, comprise control and processing section, clock synchronization part, tcp data segment, it is characterized in that, described control and processing section comprise network center's control and treatment part and each distributed unit control and treatment part, each distributed unit control and treatment part is a core with FPGA, each distributed unit realizes in real time synchronously in the Control Network, timed sending and reception data; Network center's control and treatment part: implement control and treatment by main control computer and supervisory control comuter, in the main control computer detecting network how many distributed unit are arranged and according to system configuration information and each distributed unit function of functional configuration information configuration, main control computer and supervisory control comuter are finished the monitoring to packet; Described clock synchronization partly comprises 1 main distributed unit MASTER and a plurality of from distributed unit SLAVER, main distributed unit is according to respectively postponing to determine main distributed unit and make zero constantly from the clock of distributed unit from the network line of distributed unit, realize between the master and slave distributed unit synchronously; Described tcp data segment transmits detecting, configuration data and initiates message synchronously under Asynchronous Mode, synchronous mode is each distributed unit real time data of transmission down
2. distributed network clock synchronization system according to claim 1, it is characterized in that, respectively from the processing time of the real-time control module of distributed unit according to its reception and transmission message, send the time interval of message and from the distributed unit unit number, calculate respectively from the network line of distributed unit and postpone Delay.
3. distributed network clock synchronization system according to claim 1 is characterized in that, system configuration information comprises that system synchronization cycle, data transmitting period, data send length, Data Receiving buffer address, data delivery time; The functional configuration module is according to functional configuration information specified data acquisition rate, data acquisition channel number, data acquisition memory address, data output buffers address.
4. distributed network clock synchronization system according to claim 1, it is characterized in that, be embedded with the SOPC soft-core processor among the FPGA, be provided with system configuration, functional configuration, transmission control, control in real time, UDP and collection and output module, wherein system configuration module, functional configuration module and transmission control module are realized by FPGA; Control module, UDP module are realized by the SOPC among the FPGA in real time.
5. distributed network method for synchronizing time based on the FPGA technology, it is characterized in that, receive the synchronous initiation message of main distributed unit transmission from distributed unit after, the output module of control module control in real time returns one and comprises the message processing time at interval with from the sync response message of distributed unit unit number, main distributed unit is according to the sync response message, send the time T m1 that initiates message synchronously, receive the time T m2 of sync response message, calculating respectively postpones from the network line of distributed unit, in real time control module realizes main according to respectively postponing to determine main distributed unit and make zero constantly from the clock of distributed unit from the network line of distributed unit, from between the distributed unit synchronously.
6. distributed network method for synchronizing time according to claim 5, it is characterized in that, the described message processing time is spaced apart from distributed unit from receiving synchronous initiation message to the time interval Adjust that sends the sync response message, calculates according to formula Delay=(Tm2-Tm1-Adjust)/2 to postpone from the distributed unit network line.
7. distributed network method for synchronizing time according to claim 5 is characterized in that, when distributed unit increases, in batches to carrying out synchronously from distributed unit and main distributed unit.
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| US7145362B1 (en) * | 2004-09-10 | 2006-12-05 | Xilinx, Inc. | Clock signal-distribution network for an integrated circuit |
| CN1333538C (en) * | 2005-03-18 | 2007-08-22 | 北京北方烽火科技有限公司 | Digital phase-lock method for clock signal in radio-frequency Layuan module |
| CN100533600C (en) * | 2007-03-14 | 2009-08-26 | 北京中星微电子有限公司 | Apparatus and method for identifying synchronous memory controller based on field programmable gate array |
| CN101114896A (en) * | 2007-05-15 | 2008-01-30 | 北京东土科技股份有限公司 | Method for implementing precise synchronization clock |
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