CN103369036A - Point to point message synchrony-based sampling and controlling method - Google Patents
Point to point message synchrony-based sampling and controlling method Download PDFInfo
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- CN103369036A CN103369036A CN201310262761XA CN201310262761A CN103369036A CN 103369036 A CN103369036 A CN 103369036A CN 201310262761X A CN201310262761X A CN 201310262761XA CN 201310262761 A CN201310262761 A CN 201310262761A CN 103369036 A CN103369036 A CN 103369036A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40143—Bus networks involving priority mechanisms
- H04L12/4015—Bus networks involving priority mechanisms by scheduling the transmission of messages at the communication node
Abstract
The invention discloses a point to point message synchrony-based sampling and controlling method. The FPGA (Field Programmable Gate Array) technology is used for realizing functions of punctual sending, receiving locking, delay calculation and timing triggering of synchronous messages, information of a distributed main control unit and subunits is interacted periodically by using point to point message transmission, each subunit uses FPGA to analyze synchronous pulse signal triggering sampling and controlling logic, and thus a point to point method lower message level synchrony-based sampling and controlling function is realized between the main control unit and the subunits in a distributed sampling control system. According to the method, the implementation of the distributed system or equipment can be simplified, the reliability is enhanced, the system construction cost can be lowered, and the system maintainability can be optimized.
Description
Technical field
The present invention relates to electric power the typical case based on the equipment of distributed sample and control or system relevant with Industry Control and use, relate in particular to a kind ofly based on point-to-point message synchronous sampling and control method, belong to electric and electronic technical field.
Background technology
In the application process of electric power system control protection and power electronic equipment; because different or single covering device design resource capacity in the geographical position that relevant device is installed is limited; can not in single device, realize whole samplings and control function; equipment or system need to be designed to realize all whole function based on distributed sampling and control system, such as application such as common wind-powered electricity generation Variable flow control system, distributed power failure wave-recording collector equipment, distributed electrical minor instrument transformer collectors.These equipment need strict sample-synchronous and control synchronously, so the normal operation of equipment need to realize based on the synchronizing signal of master controller the coordination control of whole system.
Current stage, the designed distributed sample control system majority of each device fabrication producer adopts independently, and the mode of outer synchronous control signal realizes synchronizing function, and then realize sampling and control function synchronously (such as PPS synchronously, the CNVT/INT signal is synchronous), the impact that the control system that this kind mode realizes is disturbed by external electromagnetic field very easily, the reliability of system makes easily that synchronizing signal is of short duration loses pulse or signal even lose, so that can not be guaranteed; In addition, owing to only be the driving control mode that adopts external synchronization signal, the amount of information that signal link carries is less, be unfavorable for that more and more the signal between each distributed unit is mutual, if the communication that needs to increase between each unit also needs to increase special-purpose communication port, increase the system cost cost, in engineering construction, also increased the communication wiring, be unfavorable for the raising of the integrated level of whole system.
New situation for this class distributed sample control system appearance, patent of the present invention has proposed a kind of based on point-to-point message synchronous sampling and control technology, for distributed sample control control system provides a kind of brand-new solution, improved reliability and the flexibility of system.
Summary of the invention
Goal of the invention
The objective of the invention is by the communication packet with regard to specific coding, adopt point-to-point transmission means, utilize the realization of FPGA technology based on the simultaneous techniques of message mode, triggering and then triggering synchronous sampling and Synchronization Control by lock-out pulse, so that the reliability of distributed sample control system further improves, the information interaction between each distributed unit is able to more flexibly, also be beneficial to simultaneously and reduce engineering site wiring complexity, the integrated level that improves system and the maintainability of operation like this.
Technical scheme
To achieve these goals, the invention provides following technical scheme:
A kind ofly it is characterized in that based on point-to-point message synchronous sampling and control method, may further comprise the steps:
Main control unit is handed down to each distributed subelement with sync message by the moment of setting by fpga chip, each distributed subelement by fpga chip to the sync message due in that receives along lock and resolve sync message information, according to message delay and synchronization delayed time triggering synchronous signal.Emphasis carries out the design of three aspects: point-to-point communication, message transmissions mechanism, FPGA send control and receive synchronization processing method.
That point-to-point communication is connected between main control unit and each subelement, transmission channel is shared, be not network organizing form (such as the Ethernet network construction form), the physical layer medium of point-to-point transmission is the cable form, or is fit to the optical fiber cable communication media of all kinds of wavelength.
In the described point-to-point communication, be man-to-man two-way link communication between main control unit and the subelement; For main control unit, be the communication of an one-to-many subelement, be separate between each subelement, each passage is separate in the main control unit.
Message transmissions mechanism is followed in the transmission of described message, and what transmit on the bidirectional communication link is the data flow of message form, and it is not simple logic control signal, and message is to exist with certain coding form; Message transmissions mechanism comprises synchronization frame, synchronized sampling frame or synchronous control frame, data value frame, the agreement that communication frames adopts or stipulations adopt general Standards Code, or the stipulations form of employing self-defining, the link layer coded system of message transmissions is the form of Manchester's code, UART form, 4B5B or 8B10B.
FPGA sends control and receives synchronization processing method: realize the real-time transmission of sync message by FPGA; The reception of sync message is to sample to lock the moment edge that the message frame head arrives by the FPGA high-frequency clock, and goes to drive and trigger sampling or control logic by time-delay given and the calculating gained.
FPGA sends control and receives synchronization processing method, and main control unit is by the punctual transmission of FPGA realization for the sync message of each different objects; Each distributed subelement detects the initial frame head of sync message and receipt decoding association message, realizes the triggering on the synchronous edge of sampling or control by time-delay control that by FPGA each distributed subelement also realizes that by FPGA the reception of sync message is fault-tolerant simultaneously.
Type of message comprises:
The synchronized sampling message is used for synchronously each sampling unit, uses and simplifies agreement minimizing transmission delay;
Sampling value message is used for collecting unit with the analog quantity framing loopback that gathers;
The Synchronization Control message is used for synchronous each control unit and transmits relevant control information;
Control feedback message, be used for control unit with the feedback result framing of carrying out after loopback.
Beneficial effect
1) by optimize the field network wiring of distributed sample control system based on the synchronous mode of point-to-point message, the optimization system cost increases integrated level;
2) use the FPGA technology to improve synchronous performance parameter, can reach below the 1 μ s, possess simultaneously fault tolerance and interference free performance;
3) different coding forms is supported in the message communication, such as Manchester's code, 4B5B coding etc.;
4) can support different transmission rates according to the requirement of different distributions formula control system, such as 5Mbps, 10Mbps, 20Mbps or 100Mbps etc.;
5) the communication transfer medium is applicable to cable and two kinds of communication medias of optical cable;
6) FPGA associative processor system realizes the concurrency calculating of distributed sample control system, and handling property is strong.The present invention has adopted the FPGA technology to realize the punctual transmission of sync message, receive locking, time-delay is calculated, the function of clocked flip, it is mutual by point-to-point message transmissions the information between distributed main control unit and the subelement to be carried out timing, the synchronization pulse that each subelement uses FPGA to parse triggers sampling and control logic, like this so that realized between the main control unit in the distributed sample control system and each subelement based on message level under the point-to-point mode synchronous sampling and control function, the method so that the realization of distributed system or equipment simplified, reliability is strengthened, system cost is minimized, the maintainability of system is optimized.
Description of drawings
Fig. 1 is the sequential logic figure of this programme;
Fig. 2 is master controller end theory diagram;
Fig. 3 is distributed capture end block diagram;
Fig. 4 is distributed control end block diagram;
Fig. 5 is the general principles block diagram.
Embodiment
The present invention is further described below in conjunction with accompanying drawing.
Master controller is handed down to each distributed subelement with sync message (synchronized sampling frame or synchronous control frame) by the moment of setting by fpga chip, each distributed subelement locks and resolves sync message information by FPGA to the sync message due in edge that receives, according to message delay and synchronization delayed time triggering synchronous signal, issue master controller such as the distributed capture unit after according to this synchronizing signal sampling framing, master controller is resolved the sampling message and is given main arithmetic processor to calculate, after finishing the result is issued the control message by FPGA by the moment of setting and control subelement to each, the control subelement is according to Synchronization Control message triggering synchronous signal and then trigger the control logic function, the control subelement feeds back to master controller with feedback result with the message form after finishing synchronous execution, realized synchronized sampling and the control function of whole system.Message between master controller and each distributed unit is distinguished realization by different type of messages.Its sequential logic as shown in Figure 1.
Operation principle of the present invention is as follows:
1, master controller end principle as shown in Figure 2, comprises main arithmetic processor DSP and FPGA processor, by FPGA expansion multichannel packet sending and receiving passage; Master controller sends the synchronized sampling message according to the time-delay of setting in each control cycle, carry out corresponding calculation process after receiving sampled value, sends the Synchronization Control message according to the time-delay of setting after finishing dealing with, and waits value of feedback message to be controlled; Successively circulation.
2, distributed capture end principle as shown in Figure 3, is comprised of FPGA processor and ADC Acquisition Circuit; Collecting unit carries out after receiving the synchronized sampling message synchronously and time-delay triggers the ADC sampling, framing and send sampling value message after sampling is finished; Simultaneously, the processing by FPGA has certain fault-tolerant processing and anti-interference function to the synchronized sampling message.
3, distributed control end principle as shown in Figure 4, is comprised of FPGA processor and peripheral driver control module, four partial contents be to realize at the FPGA internal main, Synchronization Control message reception ﹠ disposal unit, logic control element, control retaking of a year or grade unit, packet sending unit comprised.Control unit carries out after receiving sync message synchronously and time-delay triggers the logic control function, control carry out and feedback finish after framing send the feedback message; Simultaneously, the processing by FPGA has certain fault-tolerant processing and anti-interference function to the Synchronization Control message.
4, the design of EDI messages explanation:
Type of message comprises synchronized sampling message (be used for synchronously each sampling unit, use simplify agreement reduce transmission delay), sampling value message (being used for collecting unit with the analog quantity framing loopback that gathers), Synchronization Control message (be used for synchronously each control unit and transmit relevant control information), control feedback message (be used for control unit with the feedback result framing of carrying out after loopback).
Fig. 5 is based on point-to-point message and realizes synchronously the general principles block diagram of sampling and controlling, and this technical scheme comprises the content in the three class distributed unit, is respectively Main Control Unit, collecting unit and control unit.
Main Control Unit i.e. the Main Processor Unit of distributed system for this reason, responsible synchronously each distributed subelement, processing are resolved the Various types of data of each subelement, are processed the functions such as calculating, the transmission of control message and parameter configuration in real time, and it is generally and contains processor treatment facility unit.
Collecting unit 1,2 is mainly realized independently data sampling sending function, can be the functions such as dual transmission, also can realize parametric calibration optimization etc., be generally be distributed in each collection capacity near, arrange that nearby the optimization system design improves antijamming capability.
Control unit 1, the 2 main control logics that realize each different application demand can realize carrying out parameter configuration etc., are used for concrete real-time control, feedback and the relevant fault-tolerant processing of carrying out object.
More than be used for the distributed unit (collecting unit or control unit) of principle of specification, be not limited to title, it can be multi-functional distributed director, and its inside can be microprocessor-based control unit such as containing CPU or DSP.
Claims (7)
1. one kind based on point-to-point message synchronous sampling and control method, it is characterized in that, may further comprise the steps:
Main control unit is handed down to each distributed subelement with sync message by the moment of setting by fpga chip, each distributed subelement by fpga chip to the sync message due in that receives along lock and resolve sync message information, according to message delay and synchronization delayed time triggering synchronous signal.
2. according to claim 1 based on point-to-point message synchronous sampling and control method, it is characterized in that, that point-to-point communication is connected between main control unit and each subelement, transmission channel is shared, the physical layer medium of point-to-point transmission is the cable form, or is fit to the optical fiber cable communication media of all kinds of wavelength.
3. according to claim 2ly it is characterized in that based on point-to-point message synchronous sampling and control method, in the described point-to-point communication, is man-to-man two-way link communication between main control unit and the subelement; For main control unit, be the communication of an one-to-many subelement, be separate between each subelement, each passage is separate in the main control unit.
4. according to claim 1ly it is characterized in that based on point-to-point message synchronous sampling and control method message transmissions mechanism is followed in the transmission of described message, what transmit on the bidirectional communication link is the data flow of message form; Message transmissions mechanism comprises synchronization frame, synchronized sampling frame or synchronous control frame, data value frame, the agreement that communication frames adopts or stipulations adopt general Standards Code, or the stipulations form of employing self-defining, the link layer coded system of message transmissions is the form of Manchester's code, UART form, 4B5B or 8B10B.
5. according to claim 1ly it is characterized in that based on point-to-point message synchronous sampling and control method that FPGA sends control and receives synchronization processing method and is: realize the real-time transmission of sync message by FPGA; The reception of sync message is to sample to lock the moment edge that the message frame head arrives by the FPGA high-frequency clock, and goes to drive and trigger sampling or control logic by time-delay given and the calculating gained.
6. according to claim 1ly it is characterized in that based on point-to-point message synchronous sampling and control method that FPGA sends control and receives synchronization processing method and is, main control unit is realized punctual transmission for the sync message of each different objects by FPGA; Each distributed subelement detects the initial frame head of sync message and receipt decoding association message, realizes the triggering on the synchronous edge of sampling or control by time-delay control that by FPGA each distributed subelement also realizes that by FPGA the reception of sync message is fault-tolerant simultaneously.
7. according to claim 1ly it is characterized in that based on point-to-point message synchronous sampling and control method,
Type of message comprises:
The synchronized sampling message is used for synchronously each sampling unit, uses and simplifies agreement minimizing transmission delay;
Sampling value message is used for collecting unit with the analog quantity framing loopback that gathers;
The Synchronization Control message is used for synchronous each control unit and transmits relevant control information;
Control feedback message, be used for control unit with the feedback result framing of carrying out after loopback.
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| CN201310262761XA CN103369036A (en) | 2013-06-27 | 2013-06-27 | Point to point message synchrony-based sampling and controlling method |
| PCT/CN2013/084177 WO2014205936A1 (en) | 2013-06-27 | 2013-09-25 | Sampling and control method based on point-to-point message synchronization |
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| CN201310262761XA CN103369036A (en) | 2013-06-27 | 2013-06-27 | Point to point message synchrony-based sampling and controlling method |
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Cited By (6)
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| CN103795790A (en) * | 2014-01-23 | 2014-05-14 | 国电南瑞科技股份有限公司 | Distributed synchronous sampling and control system and method based on communication |
| CN105162726A (en) * | 2015-09-02 | 2015-12-16 | 南京磐能电力科技股份有限公司 | Remote SV data transmission and delay compensation method based on E1 link |
| CN103795520B (en) * | 2014-01-23 | 2017-01-25 | 国家电网公司 | Method for real-time synchronization based on FPGA message |
| CN107817721A (en) * | 2017-10-26 | 2018-03-20 | 上海乐耘电气技术有限公司 | Electric power wave-recording synchronous data sampling system |
| CN108111224A (en) * | 2017-12-05 | 2018-06-01 | 艾乐德电子（南京）有限公司 | A kind of asynchronous fiber optic communication method, apparatus and network |
| CN111130070A (en) * | 2019-12-18 | 2020-05-08 | 南京国电南自电网自动化有限公司 | Line differential protection method based on wireless network retransmission mechanism |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103795790A (en) * | 2014-01-23 | 2014-05-14 | 国电南瑞科技股份有限公司 | Distributed synchronous sampling and control system and method based on communication |
| CN103795520B (en) * | 2014-01-23 | 2017-01-25 | 国家电网公司 | Method for real-time synchronization based on FPGA message |
| CN105162726A (en) * | 2015-09-02 | 2015-12-16 | 南京磐能电力科技股份有限公司 | Remote SV data transmission and delay compensation method based on E1 link |
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| CN111130070A (en) * | 2019-12-18 | 2020-05-08 | 南京国电南自电网自动化有限公司 | Line differential protection method based on wireless network retransmission mechanism |
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| WO2014205936A1 (en) | 2014-12-31 |
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