CN103607270B - Method for improving synchronous performance of Powerlink Ethernet - Google Patents
Method for improving synchronous performance of Powerlink Ethernet Download PDFInfo
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- CN103607270B CN103607270B CN201310628093.8A CN201310628093A CN103607270B CN 103607270 B CN103607270 B CN 103607270B CN 201310628093 A CN201310628093 A CN 201310628093A CN 103607270 B CN103607270 B CN 103607270B
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Abstract
A method for improving synchronous performance of the Powerlink Ethernet comprises the steps that all slave stations establish local timers; the Ethernet communication cycle Tp and deterministic delay compensation value Toffset are obtained; when initially receiving an SOC package, each slave station starts the local timer and sets T as T=Tp-Toffset; from the second time of receiving the SOC package on, the actual timing movement and expected timing movement are compared at each time that the SOC package is received, and the time deviation tn of the actual timing movement and the expected timing movement is stored, wherein before the SOC package is received for the N+1 time, the timing period T in which the timing period circulation number is equal to reaching times of the SOC package at each time that the SOC package is received; later, n is cleared and counting is conducted again every time n is equal to N, the time deviation average value is calculated, and T is adjusted in N timing periods after a timing period one less than the reaching times of the SOC package which should be reached. The method has certain fault-tolerant capability on synchronous vibration of a main station.
Description
Technical field
The present invention relates to a kind of method improving Powerlink Ethernet net synchronization capability.
Background technology
Along with ethernet technology and the development of electronic information technology, traditional fieldbus towards industry with
The direction netted very much is developed.The main advantage of EPA is that propagation rate is fast, packet size big, passes
Defeated distance, topological structure are flexible.Bus is applied at industrial circle especially motor control, it is desirable to work
Industrial Ethernet has the i.e. definitiveness communication of real-time, definitiveness response and synchronicity.New international mark
Quasi-IEC61784 industrial communication network professional etiquette specification (Industrial communication
Networks-Profiles), require to define real-time ether according to real-time (if net synchronization capability is less than 1us)
Net, and included 10 kinds of real-time ethernets, including Ethernet Powerlink.
Real-time ethernet in IEC61784 is each provided with definitiveness communication modes and the method for synchronization of oneself.
Powerlink uses request, answer-mode and time-sharing multiplex TDMA(Time Division Multiple
Access) mechanism realizes definitiveness communication, as shown in Figure 1.Each communication cycle is divided into synchronous phase
And asynchronous stages.Synchronous phase is by SOC(Start Of Cycle) synchronize packet broadcast and issue startup, main website with
Slave station carries out data exchange according to request (the Preq bag in figure), response (the Pres bag in figure) pattern.
Asynchronous stages is by SOA(Start of Asynchronous) asynchronous unwrap the beginning.
The method of synchronization of Powerlink can use IEEE1588/IEC61588 agreement (Standard for a
Precision Clock Synchronization Protocol for Networked Measurement and Control
Systems), also referred to as precision clock agreement Precision Time Protocol (PTP).IEEE1588's is excellent
Gesture be that node is more and all can provide during across a network less than and close to the synchronization accuracy (hardware of 1 μ s
Realize).But, the implementation of IEEE1588 is more complicated.At the less Powerlink of node data
In network, such as based on Powerlink DNC system, then without using IEEE1588 only to use
SOC synchronizes also to reach that < synchronization accuracy of 1 μ s even synchronization accuracy than IEEE1588 is high.
But, for the occasion that requirement of real-time is higher, such as distributed motor control, net synchronization capability gets over Gao Yue
Good.The synchronization accuracy of 1 μ s still can not meet the demand of High-speed machining.It addition, these networks generally use
Linear, annular, tree-like topological structure.For such network, if synchronizing bag synchronization only with SOC,
Then SOC is often through a node, and its jitter amplitude all can increase (jitter accumulation).(ratio when node is less
Such as 3,4) may be provided for the synchronization accuracy of 100ns, but when node is more, just can not meet requirement.
Meanwhile, slave station depends directly on main website SOC and synchronizes bag, and main website real-time also results in SOC shake,
Afterwards slave station can be passed to.
Physical layer and the link layer of Powerlink Ethernet as in figure 2 it is shown, Powerlink link layer generally by
FPGA realizes, and Powerlink packet is flowed into RJ45 network interface by twisted-pair feeder, becomes then in turn through network
Depressor, PHY chip flow into FPGA, then pass sequentially through another PHY chip, network transformer, RJ45
Network interface, twisted-pair feeder flow into next node.Obviously, there are two factors to have impact on SOC and synchronize the accuracy of bag,
Then have impact on the net synchronization capability of each node of whole system: SOC and synchronize shake and the SOC synchronization bag of bag
Delay.
The reason of SOC shake is: SOC synchronizes bag often through a node, it just by a upper node time
Clock territory proceeds to the clock zone of next node, and SOC must be caused between two asynchronous clocks to synchronize the shake of bag.
The shake of individual node will not be big, but this shake is accumulation, will necessarily this be amplified when node is many.
The reason that SOC postpones is mainly deterministic delays, comprising: netting twine and wiring board transmission delay are (false
If the most more switching network after equipment installation)；PHY chip postpones；SOC synchronizes the Forwarding Latency of bag；SOC
Synchronize the transmission time (SOC synchronizes bag size and fixes) of bag.
Summary of the invention
The technical problem to be solved is to provide a kind of method of synchronization synchronizing to wrap based on SOC to carry
The method of the high Powerlink Ethernet net synchronization capability not using IEEE1588 agreement, the method is to main website
Synchronization jitter has certain fault-tolerant ability.
The technical solution adopted in the present invention is: the method improving Powerl ink Ethernet net synchronization capability, bag
Include:
All slave stations set up local timer respectively, and each slave station is determined whenever full one of the chronoscope of local timer
Time cycle T time, just produce and once interrupt；
Each slave station prolongs from the definitiveness of communication cycle Tp and this slave station that main website obtains this Powerlink Ethernet
Offset T lateoffset；
Each from stand in receive for the first time SOC synchronize bag time, start local timer, and this locality is fixed
Time device timing cycle T be set to T=Tp-Toffset；
Each slave station receives SOC from second time and synchronizes to package, and starts to synchronize SOC the reception number of times of bag
Counting, count value is n, and count value n is compared with count threshold N set in advance, exists simultaneously
Receive SOC every time and synchronize the actual timing moment of local timer when SOC is synchronized to wrap arrival by Bao Shijun
Ts makes comparisons with expectation timer time Tl, during to obtain and to store this actual timing moment Ts with expectation timing
Carve time deviation t between TlnIf actual timing moment Ts, early than expectation timer time Tl, makes tnFor
Negative value, if actual timing moment Ts is later than expectation timer time Tl, makes tnFor on the occasion of；SOC synchronizes bag
During arrival, desired local timer timer time refers to that timing cycle circulation number is more same than the SOC of this arrival
The finish time of that timing cycle arriving number of times little 1 of step bag；Wherein:
Each from stand in the N+1 time receive SOC synchronize bag before, receive every time SOC synchronize bag time,
That timing cycle T arriving number of times identical that circulation number all synchronizes bag with the SOC of this arrival sets
For Tp；
Each slave station receives SOC from the N+1 time and synchronizes to package, whenever n=N, and weight after n is reset
Newly start SOC is synchronized the reception counting how many times of bag, and obtain the meansigma methods of time deviation
Further, that of the arrival number of times little 1 wrapped than the SOC of this arrival synchronization in timing cycle circulation number is fixed
Time the cycle after N number of timing cycle all the timing cycle T of local timer is adjusted to
The invention have the advantages that
1, the method for the raising Powerlink net synchronization capability that the present invention provides, owing to determining local timer
Time the cycle done static compensation and dynamic compensation, such that it is able to significantly improve the synchronicity of Powerlink network
Energy；In DNC system based on Powerlink, synchronization accuracy can be made to be less than 100ns, thus
The machining accuracy of distributed type high speed processing industry can be improved.And then the product matter of distributive knowledge network can be improved
Amount and efficiency, and make that field wiring is succinct, be easily installed；
2, in the present invention, the synchronizing signal (interruption) of slave station is given by local timer rather than with SOC
Synchronization bag is given.SOC synchronizes to wrap in the shake rule of current slave station and substantially conforms to normal distribution, uses SOC
Synchronize the meansigma methods of bag time of reception to substitute single value and dynamically adjust the drift of local timer timing, can carry
The high fault-tolerant ability that SOC is synchronized bag；
3, the implementation of the present invention is simpler than IEEE1588, but can reach the effect better than its net synchronization capability
Really；Completely compatible to existing Powerlink standard agreement, can directly replace existing Powerlink net
Network and without changing main website code.
Accompanying drawing explanation
Fig. 1 is the Principle of Communication schematic diagram of Powerlink Ethernet.
Fig. 2 is physical layer and the structural representation of link layer of the slave station of Powerlink Ethernet.
Fig. 3 shows that a slave station in Powerlink Ethernet uses and improves according to an embodiment of the invention
The schematic flow sheet of the method for Powerlink Ethernet net synchronization capability.
Fig. 4 is the schematic diagram of the Powerlink Ethernet with linear topology structure.
Fig. 5 is the slave station fpga chip that the employing present invention improves the method for Powerlink Ethernet net synchronization capability
Theory diagram.
Detailed description of the invention
Below in conjunction with the accompanying drawings the present invention is made and further illustrating.
Fig. 3 shows that a slave station in Powerlink Ethernet uses and improves according to an embodiment of the invention
The schematic flow sheet of the method for Powerlink Ethernet net synchronization capability, the flow process of remaining slave station is identical with this.
Shown in Fig. 3, improve Powerlink Ethernet net synchronization capability according to an embodiment of the invention
Method, comprises the following steps:
All slave stations set up local timer respectively, and each slave station is whenever the full timing of the chronoscope of local timer
During cycle T, just produce once interruption (refer to the S11 of Fig. 3).
In the asynchronous communication stage of Powerlink Ethernet, each slave station obtains this Powerlink Ethernet from main website
Communication cycle Tp and definitiveness delay compensation value T of this slave stationoffset(refer to the S12 of Fig. 3)
In deterministic delays, only netting twine is relevant with in-site installation with the nodes of cascade, and other factor is all at hardware
Just secure after being fixed up, thus fixed delay can be measured when hardware is fixed and (be set to Tdelay), then exist
During in-site installation, the slave station number according to length of mesh wire and the SOC synchronization bag current slave station process of arrival compensates.Netting twine
What length caused is that nanosecond postpones, and ignores (DNC system for simplifying when calculating can specify that less than 2m
In, the length of two nodes is typically not greater than half meter).If the slave station number that SOC synchronizes bag process is m, the most currently
The offset T of the deterministic delays of slave stationoffsetFor m*Tdelay。
If consideration line length, take every meter of 5ns and postpone, if the wire length of present node and a upper node is lm, then
Tdelay_m=Tdelay+5lm, then
(n is continuous number of current node, and m is ibid)
When each slave station receives the SOC synchronization bag sent by main website, it is judged that be which time receives SOC together
Step bag (refer to the S13 of Fig. 3).
Each from stand in receive for the first time SOC synchronize bag time, start local timer, and to first timing
Cycle carries out static compensation, and the timing cycle T of local timer is set to T=Tp-Toffset(refer to Fig. 3's
S15).
Each slave station receives SOC from second time and synchronizes to package, and starts to synchronize SOC the reception number of times of bag
Counting, count value is n, and count value n is compared with count threshold N set in advance, exists simultaneously
Receive SOC every time and synchronize the actual timing moment of local timer when SOC is synchronized to wrap arrival by Bao Shijun
Ts makes comparisons with expectation timer time Tl, during to obtain and to store this actual timing moment Ts with expectation timing
Carve time deviation t between Tln(step S16 see in Fig. 3), if actual timing moment Ts early than
Expect timer time Tl, make tnFor negative value, if actual timing moment Ts is later than expectation timer time Tl,
Make tnFor on the occasion of.SOC synchronizes desired local timer timer time when bag arrives and refers to that timing cycle circulates
Number synchronizes the finish time of that timing cycle arriving number of times little 1 of bag, example than the SOC of this arrival
As, SOC synchronizes bag when reaching for the second time, it is desirable to local timer timer time refer to the of local timer
The finish time of one timing cycle (i.e. timing cycle circulation number is 1), when the bag of SOC synchronization for the third time reaches,
Desired local timer timer time refers to second timing cycle (i.e. timing cycle circulation of local timer
Number is 2) finish time, the like.This finish time namely local timer just count a full cycle,
Slave station produces that moment interrupted.Wherein:
Each from stand in the N+1 time receive SOC synchronize bag before, receive every time SOC synchronize bag time,
All timing cycle is circulated that timing that number is identical with the arrival number of times of the SOC of this arrival synchronization bag
Cycle T is set to Tp；
Each slave station receives SOC from the N+1 time and synchronizes to package, whenever n=N, and weight after n is reset
Newly start SOC is synchronized the reception counting how many times of bag, and obtain the meansigma methods of time deviation
Further, that of the arrival number of times little 1 wrapped than the SOC of this arrival synchronization in timing cycle circulation number is fixed
Time the cycle after N number of timing cycle all the timing cycle T of local timer is adjusted to T=Tp+(see step S17～S19).
For example, if N=10, communication cycle Tp=4ms, the T of slave station 2offset=0.002ms, the most same
When step bag arrives, slave station 2 is using T=4-0.002ms as this timing cycle, in second time to the tenth SOC
When synchronizing bag arrival, the 2nd to the 10th timing cycle is disposed as T=4ms.If synchronizing bag second from SOC
Secondary arrival slave station 2 is until the tenth once arrives slave station 2, and each SOC synchronizes the basis of slave station 2 when bag arrives
The actual timing moment of ground intervalometer is 0.003ms, shows that the SOC synchronization bag ratio arriving slave station 2 is desired
Intervalometer timer time loses time 0.003ms.(n=10) when bag the tenth once arrives, slave station 2 is synchronized at SOC
Count value n is reset, and by lower ten timing cycles (i.e. the 11st timing cycle to the 20th timing cycle)
Periodic quantity be all set to (Tp+0.003/10) ms.Slave station 2 is when SOC synchronizes the 12nd arrival of bag, heavy
The reception number of times newly starting to synchronize SOC bag counts.If synchronizing bag from SOC to arrive slave station 2 the 12nd time
Rising until the 20th once arrives slave station 2, each SOC synchronizes the local timer of slave station 2 when bag arrives
The actual timing moment is 3.9ms, shows to arrive the SOC of slave station 2 and synchronizes bag and walk fast 0.1ms than expected value,
When SOC synchronizes bag the 20th once arrival (n=10), slave station 2 is by lower ten timing cycles the (the i.e. the 21st
Individual timing cycle to the 30th timing cycle) periodic quantity be all set to (Tp-0.1/10) ms.
In another specific embodiment, above-mentioned ordinal number threshold value N=P × m × Tphy/Tpl, P are sampling
Dot factor, P ＞ 1, m are the slave station quantity that SOC synchronizes bag process, and Tphy is the PHY core of slave station physical layer
The clock cycle of sheet, Tpl is the clock cycle of the fpga chip intervalometer of slave station link layer.If N too conference
Increase the lag time adjusting timing cycle, if the least, affect the precision of adjustment.Preferably, P=10.
This algorithm is suitable for linear, annular, the topological structure of tree level connection, linear structure as shown in Figure 4.
This system at least Yao Youyige main website configuration Powerlink network.
Fig. 5 is the slave station fpga chip that the employing present invention improves the method for Powerlink Ethernet net synchronization capability
Theory diagram.In figure, OpenMAC, OpenHub of fpga chip are from POWERLINK standardization body
The Powerlink IP kernel that EPSG provides.User application realizes in NIOS.Clock unit is responsible for product
The raw due in interrupted and store Powerl ink packet.Clock management module is responsible for initializing and dynamic
Compensating clock unit.If slave station uses the implementation of MCU+FPGA, then need slave station application program
Realize at MCU, and add the PDI interface that EPSG provides.
Claims (3)
1. the method improving Powerlink Ethernet net synchronization capability, it is characterised in that including:
All slave stations set up local timer respectively, and each slave station is determined whenever full one of the chronoscope of local timer
Time cycle T time, just produce and once interrupt；
Each slave station prolongs from the definitiveness of communication cycle Tp and this slave station that main website obtains this Powerlink Ethernet
Offset T lateoffset；
Each from stand in receive for the first time SOC synchronize bag time, start local timer, and this locality is fixed
Time device timing cycle T be set to T=Tp-Toffset；
Each slave station receives SOC from second time and synchronizes to package, and starts to synchronize SOC the reception number of times of bag
Counting, count value is n, and count value n is compared with count threshold N set in advance, exists simultaneously
Receive SOC every time and synchronize the actual timing moment of local timer when SOC is synchronized to wrap arrival by Bao Shijun
Ts makes comparisons with expectation timer time Tl, during to obtain and to store this actual timing moment Ts with expectation timing
Carve time deviation t between TlnIf actual timing moment Ts, early than expectation timer time Tl, makes tnFor
Negative value, if actual timing moment Ts is later than expectation timer time Tl, makes tnFor on the occasion of；SOC synchronizes bag
During arrival, desired local timer timer time refers to that timing cycle circulation number is more same than the SOC of this arrival
The finish time of that timing cycle arriving number of times little 1 of step bag；Wherein:
Each from stand in the N+1 time receive SOC synchronize bag before, receive every time SOC synchronize bag time,
All timing cycle is circulated that timing that number is identical with the arrival number of times of the SOC of this arrival synchronization bag
Cycle T is set to Tp；
Each slave station receives SOC from the N+1 time and synchronizes to package, whenever n=N, and weight after n is reset
Newly start SOC is synchronized the reception counting how many times of bag, and obtain the meansigma methods of time deviation
Further, that of the arrival number of times little 1 wrapped than the SOC of this arrival synchronization in timing cycle circulation number is fixed
Time the cycle after N number of timing cycle all the timing cycle T of local timer is adjusted to
2. the method improving Powerlink Ethernet net synchronization capability as claimed in claim 1, it is characterised in that
Described count threshold N=P × m × Tphy/Tpl, P are sampled point coefficient, and P ＞ 1, m are that SOC is same
Step bag arrives the slave station quantity of this node process, and Tphy is the clock cycle of the PHY chip of slave station physical layer, Tpl
Clock cycle for the fpga chip intervalometer of slave station link layer.
3. the method improving Powerlink Ethernet net synchronization capability as claimed in claim 1, it is characterised in that
Each slave station is to obtain the logical of this Powerlink Ethernet in the asynchronous communication stage of Powerlink Ethernet from main website
News cycle T p and deterministic delays offset Toffset。
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103812635B (en) * | 2014-03-05 | 2017-01-11 | 武汉迈信电气技术有限公司 | Method for reducing jittering in POWERLINK SoC frame synchronization based on MCU |
| CN103825695B (en) * | 2014-03-11 | 2017-02-08 | 武汉迈信电气技术有限公司 | Compensation method for synchronous time delay of network based on POWERLINK |
| CN105743758A (en) * | 2014-12-08 | 2016-07-06 | 上海中科再启医疗设备有限公司 | Communication method |
| CN106230541B (en) * | 2016-08-05 | 2018-08-21 | 深圳市骏龙电子有限公司 | A kind of Site synch system and method for Industrial Ethernet |
| CN107800528B (en) * | 2016-08-31 | 2021-04-06 | 中兴通讯股份有限公司 | Method, device and system for transmitting synchronous information |
| RU185051U1 (en) * | 2018-07-24 | 2018-11-19 | Федеральное государственное бюджетное образовательное учреждение высшего образования "МИРЭА - Российский технологический университет" | FPGA ETHERNET POWER SLIN SLAVE |
| RU184683U1 (en) * | 2018-07-26 | 2018-11-02 | Федеральное государственное бюджетное образовательное учреждение высшего образования "МИРЭА - Российский технологический университет" | ETHERNET POWERLINK NETWORK RESINCHRONIZER |
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| CN1866803A (en) * | 2005-09-13 | 2006-11-22 | 华为技术有限公司 | Ethernet apparatus and method for solving clock synchronization in total Ethernet |
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