CN103378916A - Clock transmission method, boundary clock and transparent clock - Google Patents
Clock transmission method, boundary clock and transparent clock Download PDFInfo
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- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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Abstract
The invention discloses a clock transmission method, a boundary clock and a transparent clock. The method comprises the following steps that firstly, clock or time synchronization is finished between an ordinary clock-slave clock physical entity of the boundary clock and a master clock, and the clock or time synchronization is carried out on a middle physical entity of the boundary clock; secondly, the clock or time synchronization is carried out on an ordinary clock-master clock physical entity of the boundary clock through the middle physical entity, and the clock or time synchronization is carried out on a slave clock through the ordinary clock-master clock physical entity. The problem that an IEEE 1588v2 protocol in the network of the IEEE 1588v2 protocol cannot be supported is solved through a virtual network element.
Description
Technical field
The present invention relates to universal Clock Synchronization Technology, relate in particular to a kind of clock transfer method, boundary clock and transmission clock.
Background technology
The air interface synchronization of the wireless technologys such as CDMA2000, TD-SCDMA, LTE-TDD and LTE-A in the wireless system, and multimedia (Multimedia Broadcast/Multicast Service, MBMS) application have corresponding requirement to time synchronized.In these wireless systems, generally by base station controller (BSC/RNC) to the base station passing time, the return network in the middle of this requires is supported the time synchronized of the whole network.
IEEE 1588v2 agreement is a kind of clock synchronization of ad agreement that realizes that precision clock is synchronous that is proposed by institute of Electrical and Electronic Engineers (IEEE), its precision can reach the submicrosecond level, is widely used at present the fields such as Ethernet, communication network and system, distributed measurement and control.Along with the development of 1588 Clock Synchronization Technology, its application in the communications field is also more and more extensive at present.
IEEE 1588v2 agreement realizes clock or time synchronized by master clock (1588v2Master) and from exchange sync message between the clock (1588v2Slave), wherein, master clock and agreement, be also referred to as ordinary clock (Ordinary Clock, OC) from clock.
Fig. 1 is the master-salve clock synchronization message switching schematic diagram based on IEEE 1588v2 agreement, and its synchronizing information exchange process comprises:
Steps A .1588v2Master periodically sends sync message (Sync message) and gives 1588v2Slave, and by sync message or follow-up message (FollowUp message) sync message is gone out moment T1 timestamp and send to 1588v2Slave;
Step records sync message due in T2 timestamp after B.1588v2Slave receiving sync message, and parses the T1 timestamp from sync message or follow-up message;
If it is synchronous that 1588v2Slave and 1588v2Master will realize clock (frequency), it is through steps A and the T1 of step B gained and the demand that the T2 timestamp can satisfy clock synchronous, if the realization time (phase place) is synchronous, also need step C and D.
Step is C.1588v2Slave to 1588v2Master forward delay interval request message (DelayReq message) and record its delivery time T3 timestamp;
Step records its due in T4 timestamp and rapid answer time-delay answer message (DelayResp message) and in this message the T4 timestamp is sent to 1588v2Slave after D.1588v2Master receiving the time-delay request message, 1588v2Slave replys packet parsing from time-delay and goes out the T4 timestamp, and utilizes estimation and the calibration of these four timestamp deadline deviations.
1588 clocks are typical classes of packets clocks, the delay jitter variation of transmission network equipment (Packet Delay Variant between the principal and subordinate, PDV) can introduce noise to the entrained clock of the packet message of end-to-end transmission or time signal, and then 1588 net synchronization capabilities are produced material impact.Boundary clock (Boundary Clock in the IEEE 1588v2 agreement, BC) and transmission clock (Transparent Clock, TC) can reduce to a great extent PDV to the impact of 1588 timing synchronization performance, applicable cases from present 1588, the general transmission equipment support 1588v2 that requires between 1588 master-slave equipments, the role of transmission equipment can select boundary clock or transmission clock according to the practical application scene.
Fig. 2 is BC model in the IEEE 1588v2 agreement, and its processing unit comprises:
The 1588v2Slave port: the input port of 1588 signals, input signal was presented as 1588 message forms before the rise time stamp;
1588 timestamp makers: the timestamp of 1588 messages when input and output generates to be processed, and 1588 messages form 1588 clock signals after through 1588 timestamp makers;
System clock and time quantum: after local clock or time are controlled through 1588 input signals as 1588BC network element system clock and time;
The 1588v2Master port: the output port of 1588 signals, the 1588BC network element by the output of 1588v2Master port, is finished 1588 clocks to next stage 1588 network element transmission with the controlled system clock.
Fig. 3 is TC model in the IEEE 1588v2 agreement, and its processing unit comprises:
Local clock and time quantum: 1588TC network element work clock and time, constantly gather and time-delay correcting process unit provides work clock and time for going out, 1588TC network element work clock and time not mandatory requirement be controlled by external clock and time reference source;
Enter constantly collecting unit: to 1588 signals collecting input times of input, enter constantly to be carried in 1588 messages with the timestamp form;
1588 signal transparent transmission unit: 1588 signals are through the transparent transmission unit transparent transmission of 1588TC network element internal, and the concrete thing s reason form of 1588 signal transparent transmission unit is Ethernet switching chip normally;
Go out constantly to gather and time-delay correcting process unit: to 1588 signals collecting output times of output, and with entering of the inner carrying of 1588 messages constantly do poor, calculate 1588 signals in the resident time-delay of 1588TC network element internal, and in the correction territory (correctionField) with resident delay accumulation to 1588 message.
By the function of BC and TC in the standard IEEE 1588v2 agreement, BC mainly by the step by step lower control of clock or time, reduces PDV to the impact of end-to-end 1588 master-slave synchronisation performances.TC mainly by revising the time-delay of passing through of clock or time signal, reduces the noise that PDV introduces.
In 1588 clock subnets, return network is generally played the part of the role of BC and TC, this requires each network element of return network to support IEEE 1588v2 agreement, but IEEE 1588v2 agreement could realize at the Ethernet interface of network element usually, therefore for the non-Ethernet return network, can't realize IEEE 1588v2BC and the TC of standard.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of clock transfer method, boundary clock and transmission clock, solves the problem that the non-Ethernet return network can't be supported IEEE 1588v2 agreement.
For solving the problems of the technologies described above, a kind of clock transfer method of the present invention comprises:
The ordinary clock of boundary clock-finish clock or time synchronized with master clock from the clock physical entity, and the intermediate physical entity of described boundary clock is carried out clock or time synchronized;
Described intermediate physical entity is carried out clock or time synchronized to the ordinary clock of described boundary clock-master clock physical entity, and described ordinary clock-master clock physical entity is to carrying out clock or time from clock synchronous.
Further, when carrying out clock synchronous, carry out clock synchronous by clock signal between the physical entity of described boundary clock; When carrying out time synchronized, carry out clock synchronous by clock signal between the physical entity of described boundary clock after, carry out time synchronized by time signal.
Further, when the physical NE at each physical entity place of boundary clock was the microwave physical NE, clock signal was the microwave clock of eating dishes without rice or wine; When physical NE was SDH (Synchronous Digital Hierarchy) (SDH) physical NE, clock signal was the STM-N line clock; When physical NE was the synchronous ethernet network, clock signal was synchronous Ethernet clock.
When the physical NE at each physical entity place of boundary clock was the microwave physical NE, time signal was microwave 1 pulse per second (PPS) (PPS) of eating dishes without rice or wine; When physical NE was the cascade network element, time signal was the 1PPS Signal coding of 1PPS cable or timestamp form.
Further, a kind of clock transfer method comprises:
The border physical entity of transmission clock gathers message and enters constantly behind the message that receives the master clock transmission, will enter constantly to multiply by (1) to be added to sync message correction territory, with the intermediate physical entity of message transmission to transmission clock;
Described intermediate physical entity is with the physical entity of message transmission to the output port place, and the physical entity at output port place gathers going out constantly of message, will go out constantly to multiply by (+1) to be added in the sync message correction territory.
Further, when carrying out clock synchronous, carry out clock synchronous by clock signal between the physical entity of described transmission clock; When carrying out time synchronized, carry out clock synchronous by clock signal between the physical entity of described transmission clock after, carry out time synchronized by time signal.
Further, a kind of boundary clock comprises: ordinary clock-from clock physical entity, intermediate physical entity and ordinary clock-master clock physical entity, wherein:
Described ordinary clock-from the clock physical entity is used for finishing clock or time synchronized with master clock, and the intermediate physical entity of described boundary clock is carried out clock or time synchronized;
Described intermediate physical entity, the ordinary clock-master clock physical entity that is used for described boundary clock carries out clock or time synchronized;
Described ordinary clock-master clock physical entity is used for carrying out clock or time synchronized from clock.
Further, described ordinary clock-comprise from the clock physical entity: standard interface and processing unit, clock and time signal input and output processing unit and system clock and time synchronized maintenance unit, wherein:
Described standard interface and processing unit are used for realizing protocol interface, dock with the network element of supporting respective protocol;
Described clock and time signal input and output processing unit are used for realizing that input signal is to the conversion of system clock and time reference source signal; And, realize that system clock and time are to the conversion of output clock and time signal;
Described system clock and time synchronized maintenance unit are used for realizing the synchronous and distribution of system clock and reference source selection, clock and the time of time.
Further, described standard interface and processing unit comprise: 1588v2 protocol process module, 1588v2 timestamp maker module and 1588v2 signal input and output processing module, wherein:
Described 1588v2 protocol process module is used for parsing timestamp from described 1588v2 timestamp maker module read local timestamp and from the 1588v2 protocol massages, with timestamp be matched to after send to described 1588v2 signal input and output processing module;
Described 1588v2 timestamp maker module is used for identification and checks output and the Ethernet message of input, the rise time stamp;
Described 1588v2 signal input and output processing module is used for the paired timestamp, output clock or the time reference source signal that send according to described 1588v2 protocol process module.
Further, described clock and time signal input and output processing unit comprise: clock signal input and output processing module and time signal input and output processing module, wherein:
Described clock signal input and output processing module is used for realizing that input signal is to the conversion of system-timing reference source signal; And system clock is to the conversion of clock signal;
Described time signal input and output processing module is used for realizing that input signal is to the conversion of system time reference source signal; And realize that system time is to the conversion of output time signal.
Further, described system clock and time synchronized maintenance unit comprise: module is selected in system clock and time distribution module, system clock and time synchronized module and clock and time reference source, wherein:
Module is selected in described clock and time reference source, be used for selecting active clock and time reference source and exporting to described system clock and time synchronized module from the clock of described 1588v2 signal input and output processing module output or clock or the time reference source signal of time reference source signal and clock and the transmission of time signal input and output processing unit;
Described system clock and time synchronized module are used for according to active clock and time reference source, realize system clock and time synchronized, system clock and time signal after the output synchronously;
Described system clock and time distribution module are used for carrying out the distribution of system clock and time.
Further, described ordinary clock-master clock physical entity comprises: 1588v2 protocol process module, 1588 timestamp maker modules, clock and time signal input and output processing unit and system clock and time synchronized maintenance unit;
Described intermediate physical entity comprises: clock and time signal input and output processing unit and system clock and time synchronized maintenance unit.
Further, a kind of transmission clock comprises: border physical entity and intermediate physical entity, wherein:
Described border physical entity is used for gathering message and entering constantly after receiving the message that master clock sends, will enter constantly to multiply by (1) to be added to sync message correction territory, with message transmission to intermediate physical entity; After receiving the message that intermediate physical entity sends, gather going out constantly of message, will go out constantly to multiply by (+1) and be added in the sync message correction territory;
Described intermediate physical entity is used for the physical entity of message transmission to the output port place.
Further, described border physical entity comprises: clock and time signal input and output processing unit, system clock and time synchronized maintenance unit and time-delay correcting process unit, wherein:
Described clock and time signal input and output processing unit are used for realizing that input signal is to the conversion of system clock and time reference source signal; And, realize that system clock and time are to the conversion of output clock and time signal;
Described system clock and time synchronized maintenance unit are used for realizing the synchronous and distribution of system clock and reference source selection, clock and the time of time;
Described time-delay correcting process unit is used for realizing the transparent transmission of signal and the correction of resident time-delay.
Further, described time-delay correcting process unit comprises: enter moment acquisition module, 1588 signal transparent transmissions and go out constantly acquisition module and time-delay correcting process module, wherein:
Describedly enter constantly acquisition module, be used for 1588 signals collecting are entered constantly, and 1588 signals are delivered to 1588 signal transparent transmission modules;
Described 1588 signal transparent transmission modules are used for receiving describedly when entering 1588 signal that acquisition module constantly sends, and 1588 signals are pass-through to the next stage physical entity; When receiving 1588 signal of upper level physical entity transparent transmission, 1588 signal transparent transmissions are provided the correcting process module that constantly gathers and delay time;
Describedly go out constantly to gather and time-delay correcting process module, be used for gathering going out constantly and carrying out the signal lag correcting process of 1588 signals that receive, revised 1588 signals are exported to from clock.
Further, described intermediate physical entity comprises: clock and time signal input and output processing unit, system clock and time synchronized maintenance unit and time-delay correcting process unit, and described time-delay correcting process unit comprises 1588 signal transparent transmission modules, wherein:
Described 1588 signal transparent transmission modules, 1588 signals that are used for the upper level physical entity transparent transmission that will receive are pass-through to the next stage physical entity.
In sum, the present invention solves in the network that can't realize IEEE 1588v2 agreement, for the support issue of IEEE 1588v2 agreement by Virtual NE.
Description of drawings
Fig. 1 is the master-salve clock synchronization message switching schematic diagram of IEEE 1588v2 agreement in the prior art;
Fig. 2 is IEEE 1588v2 agreement BC implementation method schematic diagram in the prior art;
Fig. 3 is IEEE 1588v2 agreement TC implementation method schematic diagram in the prior art;
Fig. 4～Fig. 5 is the schematic diagram of the virtual BC of 1588v2 of present embodiment;
Fig. 6 is the schematic diagram of the virtual TC of 1588v2 of present embodiment;
Fig. 7 is the schematic diagram of the physical entity of present embodiment.
Embodiment
Present embodiment provides the Virtual NE of a kind of IEEE of support 1588v2, comprises the virtual TC that supports IEEE 1588v2 and the virtual BC that supports IEEE 1588v2, wherein:
(1) the virtual BC of support IEEE 1588v2 physically is presented as the non-Ethernet return network, and network is comprised of a plurality of physical entities, comprising:
(1) virtual BC docks with 1588v2Master by IEEE 1588v2 clock or time interface, wherein the physical entity that docks with 1588v2Master of BC is ordinary clock-from clock (OC-Slave) physical entity, realize that BC is synchronized with input 1588v2 clock or time signal;
(2) realize Frequency Synchronization by clock signal between the virtual BC internal physical entity;
Clock signal is multi-form for different transmission networks, for SDH (SDH (Synchronous Digital Hierarchy)) network, is the STM-N line clock; For microwave network, it is the microwave clock of eating dishes without rice or wine; For the synchronous ethernet network, it is SyncE (synchronous ethernet) clock.
(3) time signal by inner definition realizes time synchronized between the virtual BC internal physical entity, and time signal can be selected multi-form, such as 1 pulse per second (PPS) (PPS) signal;
(4) virtual BC docks with 1588v2Slave by IEEE 1588v2 clock or time interface, wherein, the physical entity that BC docks with 1588v2Slave is ordinary clock-master clock (OC-Master) physical entity, realizes that BC is to 1588v2Slave output clock or time signal.
(2) the virtual TC of support IEEE 1588v2 physically is presented as the non-Ethernet return network, and network is comprised of a plurality of physical entities, comprising:
(1) virtual TC docks with 1588v2Master by IEEE 1588v2 clock or time interface.Wherein the physical entity that docks with 1588v2Master of TC is the border physical entity, realizes constantly acquisition function;
(2) realize Frequency Synchronization by clock signal between the physical entity;
Clock signal is multi-form for different transmission networks, for the SDH network, is the STM-N line clock; For microwave network, it is the microwave clock of eating dishes without rice or wine; For the synchronous ethernet network, it is the SyncE clock.
(3) time signal by inner definition realizes time synchronized between the physical entity;
Time signal can be selected multi-form, such as the 1PPS signal.
(4) TC transparent transmission signal is through the intermediate physical entity transparent transmission; Virtual TC docks with 1588v2Slave by IEEE 1588v2 clock or time interface, wherein, the physical entity that docks with 1588v2Slave of TC is that the physical entity (physical entity at output port place belongs to the border physical entity) at output port place is realized out constantly gathering and the resident time-delay debugging functions in TC inside.
Consist of the physical entity that above-mentioned BC and TC etc. support the Virtual NE of IEEE 1588v2 in the present embodiment, comprising:
Standard interface and processing unit comprise 1588v2 protocol process module, 1588 timestamp maker modules and 1588v2 clock input and output processing module, mainly realize IEEE 1588v2 protocol interface, can dock with other network elements of supporting IEEE 1588v2 agreement;
Clock and time signal input and output processing unit comprise clock signal input and output processing module and time signal input and output processing module.For input clock and time signal, realize that input signal is to the conversion of system clock and time reference source signal; For output clock and time signal, realize that system clock and time are to the conversion of output clock and time signal;
System clock and time synchronized maintenance unit comprise system clock and time distribution, system clock and time synchronized and clock and time reference source selection module, realize that mainly the reference source of system clock and time is selected, synchronous and distribution.System clock and time are clock and the time references of physical entity.
Time-delay correcting process unit includes moment collection, 1588 signal transparent transmissions and goes out constantly collection and time-delay correcting process module.The transparent transmission of 1588 signals and the correction of the inner resident time-delay of Virtual NE are mainly realized in this unit.
Be described in further detail below in conjunction with the specific embodiment of accompanying drawing to present embodiment.
Fig. 4 is the virtual BC of present embodiment 1588v2.Wherein the physical entity that docks with 1588v2Master of BC is ordinary clock-from the clock physical entity, realize 1588v2OC-Slave function (being called for short this physical entity is the OC-Slave physical entity of BC), realize that BC is synchronized with input 1588v2 clock or time signal; The method of synchronization between the physical entity of BC inside may for clock (frequency) synchronously or the time (phase place) synchronous, be that clock synchronous or time synchronized are relevant with 1588 synchronous applications patterns of Virtual NE.The physical entity that BC docks with 1588v2Slave is ordinary clock-master clock physical entity, realize 1588v2OC-Master function (being called for short this physical entity is the OC-Master physical entity of BC), realize that BC is to 1588v2Slave output clock or time signal.
(1) when adopting based on 1588 clock (frequency) synchronously, as shown in Figure 4, clock synchronous between each physical entity is realized by clock signal in BC inside, to realize the clock transmission based on 1588.
Clock signal between inner each physical entity of BC depends on the physical NE at physical entity place.For the microwave physical NE, clock signal is generally the microwave clock of eating dishes without rice or wine; For the SDH physical NE, clock signal is generally the STM-N line clock.
(2) when employing is synchronous based on 1588 time (phase place), as shown in Figure 5, clock synchronous between each physical entity is realized by clock signal in BC inside, on the clock synchronous basis, BC inside realizes that by time signal the time (phase place) between inner each physical entity of Virtual NE is synchronous, to realize the time transmission based on 1588.Time signal between inner each physical entity of BC is generally the 1PPS signal, and the 1PPS signal can be presented as different forms during practical application.For the microwave physical NE, time signal is generally the microwave 1PPS that eats dishes without rice or wine, and for the cascade network element, time signal is generally the 1PPS Signal coding of 1PPS cable or timestamp form.Present embodiment does not limit for the concrete form of 1PPS signal.
The detailed process of 1588 signal transmission is described below:
(1) 1588v2Master transmission sync message and recorded message go out constantly T1 timestamp, and by sync message or follow-up message sync message are gone out the OC-Slave physical entity that moment T1 timestamp sends to BC;
Recorded message entered constantly T2 timestamp when (two) the OC-Slave physical entity of BC received the sync message of 1588v2Master, 1588 messages are in the inner termination of the OC-Slave physical entity that docks with 1588v2Master, if BC is used for the clock transmission, the OC-Slave physical entity of BC utilizes T1 and T2 timestamp to finish the clock synchronous of BC and 1588v2Master; If BC is used for the time and transmits, the OC-Slave physical entity of BC needs the forward delay interval request message and records its delivery time T3 timestamp;
(3) its due in of record T4 timestamp was also replied rapidly the OC-Slave physical entity that time-delay is replied message and the T4 timestamp sent to BC in this message after 1588v2Master received the time-delay request message;
(4) the OC-Slave physical entity of BC goes out the T4 timestamp from time-delay answer packet parsing, and utilizes estimation and the calibration of these four timestamp deadline deviations, realizes the time synchronized of BC and 1588v2Master;
(5) the OC-Master physical entity of BC sends sync message to the 1588v2Slave cycle, and go out sync message constantly by sync message or follow-up message that the T1 timestamp sends to 1588v2Slave, if BC is used for the clock transmission, 1588v2Slave utilizes T1 and T2 timestamp to finish the clock synchronous of 1588v2Slave and BC; If BC is used for the time and transmits, 1588v2Slave needs the forward delay interval request message and records its delivery time T3 timestamp, the OC-Master physical entity of BC records its due in T4 timestamp and rapid answer time-delay answer message and in this message the T4 timestamp is sent to 1588v2Slave after receiving the time-delay request message, 1588v2Slave replys packet parsing from time-delay and goes out the T4 timestamp, and utilize estimation and the calibration of these four timestamp deadline deviations, realize the time synchronized of 1588v2Slave and BC.
Accompanying drawing 6 is the virtual TC of 1588v2 of present embodiment.
Need between the physical entity of TC inside to realize time synchronized between each physical entity by time (phase place) signal, with the accuracy that guarantees that resident time-delay is calculated to 1588 signals.Clock synchronous between each physical entity is realized by clock signal in TC inside, and on the clock synchronous basis, time synchronized between each physical entity is come by time signal in TC inside.
Clock signal between inner each physical entity of TC depends on the physical NE at physical entity place.For the microwave physical NE, clock signal is generally the microwave clock of eating dishes without rice or wine; For the SDH network element, clock signal is generally the STM-N line clock.Time signal between inner each physical entity of TC is generally the 1PPS signal, and the 1PPS signal can be presented as different forms during practical application.For the microwave physical NE, time signal is generally the microwave 1PPS that eats dishes without rice or wine, and for the cascade network element, time signal is generally the 1PPS Signal coding of 1PPS cable or timestamp form.Present embodiment does not limit for the concrete form of 1PPS signal.
The detailed process of 1588 signal transparent transmissions is described below:
When (one) the border physical entity of the 1588v2Master sync message (virtual TC transparent transmission signal) that sends to 1588v2Slave by TC enters virtual TC, gather sync message and enter constantly (stamp input time) and multiply by (1) to be added in the sync message correction territory (correctionField);
(2) sync message is at the inner transparent transmission of virtual TC, when passing through the physical entity at virtual TC output port place, gather sync message and go out the moment (output time stamp) and multiply by (+1) to be added in the sync message correction territory, the resident time-delay of sync message in virtual TC inside just obtains revising like this.
(3) the 1588v2Slave Time delay measurement request message (if exist) when entering virtual TC that sends to 1588v2Master gathers message and enters constantly and multiply by (1) to be added in the sync message correction territory;
(4) the Time delay measurement request message is at the inner transparent transmission of virtual TC, when passing through the physical entity at virtual TC output port place, gather the Time delay measurement request message and go out constantly and multiply by (+1) to be added in the Time delay measurement request message correction territory, the resident time-delay of Time delay measurement request message in virtual TC inside just obtains revising like this.
Fig. 7 is that the physical entity of Virtual NE of the formation support 1588 of present embodiment is comprised of a plurality of processing units, and the processing unit that specifically comprises is as follows:
Standard interface and processing unit comprise 1588v2 protocol process module, 1588v2 timestamp maker module and 1588v2 signal input and output processing module, and wherein the function of modules is as follows:
The 1588v2 protocol process module: finish input and output 1588v2 protocol massages and process, realize different I EEE 1588v2 agreement clock type to the processing of 1588v2 protocol massages, the deadline stamp is collected and coupling.Collection process comprises from 1588v2 timestamp maker read local timestamp with from the 1588v2 protocol massages and parses timestamp, the timestamp after the collection be matched to after deliver to 1588v2 signal input and output processing module;
1588v2 signal input and output processing module: this module is input as paired 1588 timestamps, is output as 1588 clocks or time reference source signal;
1588 timestamp maker modules: identification also checks output and the Ethernet message of input, generates 1588 timestamps for the event message that meets standard IEEE 1588v2 agreement;
Clock and time signal input and output processing unit comprise clock signal input and output processing module and time signal input and output processing module.Wherein the function of modules is as follows:
Clock signal input and output processing module: for input clock signal, realize that input signal is to the conversion of system-timing reference source signal; For clock signal, realize that system clock is to the conversion of clock signal;
Time signal input and output processing module: for signal input time, realize that input signal is to the conversion of system time reference source signal; For the output time signal, realize that system time is to the conversion of output time signal;
System clock and time synchronized maintenance unit comprise system clock and time distribution module, system clock and time synchronized module, and clock and time reference source selection module, and wherein, the function of modules is as follows:
Module is selected in clock and time reference source: is input as multipath clock and time signal, comprises clock or time reference source signal, and clock and time signal input and output processing unit the other types clock or the time reference source signal that send over.This module is according to information such as system clock and time reference source state and priority, and the clock that decision systems is primary and time reference source are selected active clock and time reference source and exported to system clock and time synchronized module;
System clock and time synchronized module: this module is input as system clock and time reference source signal, according to active clock and time reference source, mainly realizes system clock and time synchronized, system clock and time signal after the output synchronously;
System clock and time distribution module: system clock and time signal after this module is input as synchronously, main completion system clock and time are to the inner modules distribution of device;
Time-delay correcting process unit includes constantly acquisition module, 1588 signal transparent transmission modules, and goes out constantly to gather and time-delay correcting process module, and wherein the function of modules is as follows:
Enter constantly acquisition module: the Virtual NE transparent transmission is inputted 1588 signals collecting enter constantly, and will gather into 1588 signals constantly and deliver to 1588 signal transparent transmission modules;
1588 signal transparent transmission modules: realize 1588 signal transparent transmissions.Concrete, when this physical entity is the border physical entity of TC, if be input as from entering constantly gathering into transparent transmission 1588 signals constantly of acquisition module, export the direct transparent transmission of this signal to the next stage physical entity; If be input as 1588 signals of upper level physical entity transparent transmission, this signal transparent transmission output is provided the correcting process module that constantly gathers and delay time.When this physical entity is the intermediate physical entity of TC inside, is input as 1588 signals of upper level physical entity transparent transmission, and exports the direct transparent transmission of this signal to next stage TC physical entity;
Go out constantly to gather and time-delay correcting process module: this module is input as transparent transmission 1588 signals that come from 1588 signal transparent transmission modules, gather transparent transmission 1588 signals and go out the moment and carry out the signal lag correcting process, revised 1588 signals are exported to 1588v2Slave.
Above-mentioned a plurality of processing unit is for realizing the processing unit complete or collected works of virtual BC/TC physical entity, and different physical entities can select to comprise wherein section processes unit in the inner residing position of virtual BC/TC difference.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (15)
1. a clock transfer method is characterized in that, comprising:
The ordinary clock of boundary clock-finish clock or time synchronized with master clock from the clock physical entity, and the intermediate physical entity of described boundary clock is carried out clock or time synchronized;
Described intermediate physical entity is carried out clock or time synchronized to the ordinary clock of described boundary clock-master clock physical entity, and described ordinary clock-master clock physical entity is to carrying out clock or time from clock synchronous.
2. the method for claim 1 is characterized in that, when carrying out clock synchronous, carries out clock synchronous by clock signal between the physical entity of described boundary clock; When carrying out time synchronized, carry out clock synchronous by clock signal between the physical entity of described boundary clock after, carry out time synchronized by time signal.
3. method as claimed in claim 2 is characterized in that:
When the physical NE at each physical entity place of boundary clock was the microwave physical NE, clock signal was the microwave clock of eating dishes without rice or wine; When physical NE was SDH (Synchronous Digital Hierarchy) (SDH) physical NE, clock signal was the STM-N line clock; When physical NE was the synchronous ethernet network, clock signal was synchronous Ethernet clock;
When the physical NE at each physical entity place of boundary clock was the microwave physical NE, time signal was microwave 1 pulse per second (PPS) (PPS) of eating dishes without rice or wine; When physical NE was the cascade network element, time signal was the 1PPS Signal coding of 1PPS cable or timestamp form.
4. a clock transfer method is characterized in that, comprising:
The border physical entity of transmission clock gathers message and enters constantly behind the message that receives the master clock transmission, will enter constantly to multiply by (1) to be added to sync message correction territory, with the intermediate physical entity of message transmission to transmission clock;
Described intermediate physical entity is with the physical entity of message transmission to the output port place, and the physical entity at output port place gathers going out constantly of message, will go out constantly to multiply by (+1) to be added in the sync message correction territory.
5. method as claimed in claim 4 is characterized in that, when carrying out clock synchronous, carries out clock synchronous by clock signal between the physical entity of described transmission clock; When carrying out time synchronized, carry out clock synchronous by clock signal between the physical entity of described transmission clock after, carry out time synchronized by time signal.
6. a boundary clock is characterized in that, comprising: ordinary clock-from clock physical entity, intermediate physical entity and ordinary clock-master clock physical entity, wherein:
Described ordinary clock-from the clock physical entity is used for finishing clock or time synchronized with master clock, and the intermediate physical entity of described boundary clock is carried out clock or time synchronized;
Described intermediate physical entity, the ordinary clock-master clock physical entity that is used for described boundary clock carries out clock or time synchronized;
Described ordinary clock-master clock physical entity is used for carrying out clock or time synchronized from clock.
7. boundary clock as claimed in claim 6 is characterized in that, described ordinary clock-comprise from the clock physical entity: standard interface and processing unit, clock and time signal input and output processing unit and system clock and time synchronized maintenance unit, wherein:
Described standard interface and processing unit are used for realizing protocol interface, dock with the network element of supporting respective protocol;
Described clock and time signal input and output processing unit are used for realizing that input signal is to the conversion of system clock and time reference source signal; And, realize that system clock and time are to the conversion of output clock and time signal;
Described system clock and time synchronized maintenance unit are used for realizing the synchronous and distribution of system clock and reference source selection, clock and the time of time.
8. boundary clock as claimed in claim 7 is characterized in that, described standard interface and processing unit comprise: 1588v2 protocol process module, 1588v2 timestamp maker module and 1588v2 signal input and output processing module, wherein:
Described 1588v2 protocol process module is used for parsing timestamp from described 1588v2 timestamp maker module read local timestamp and from the 1588v2 protocol massages, with timestamp be matched to after send to described 1588v2 signal input and output processing module;
Described 1588v2 timestamp maker module is used for identification and checks output and the Ethernet message of input, the rise time stamp;
Described 1588v2 signal input and output processing module is used for the paired timestamp, output clock or the time reference source signal that send according to described 1588v2 protocol process module.
9. boundary clock as claimed in claim 8 is characterized in that, described clock and time signal input and output processing unit comprise: clock signal input and output processing module and time signal input and output processing module, wherein:
Described clock signal input and output processing module is used for realizing that input signal is to the conversion of system-timing reference source signal; And system clock is to the conversion of clock signal;
Described time signal input and output processing module is used for realizing that input signal is to the conversion of system time reference source signal; And realize that system time is to the conversion of output time signal.
10. boundary clock as claimed in claim 9 is characterized in that, described system clock and time synchronized maintenance unit comprise: module is selected in system clock and time distribution module, system clock and time synchronized module and clock and time reference source, wherein:
Module is selected in described clock and time reference source, be used for selecting active clock and time reference source and exporting to described system clock and time synchronized module from the clock of described 1588v2 signal input and output processing module output or clock or the time reference source signal of time reference source signal and clock and the transmission of time signal input and output processing unit;
Described system clock and time synchronized module are used for according to active clock and time reference source, realize system clock and time synchronized, system clock and time signal after the output synchronously;
Described system clock and time distribution module are used for carrying out the distribution of system clock and time.
11. boundary clock as claimed in claim 10 is characterized in that:
Described ordinary clock-master clock physical entity comprises: 1588v2 protocol process module, 1588 timestamp maker modules, clock and time signal input and output processing unit and system clock and time synchronized maintenance unit;
Described intermediate physical entity comprises: clock and time signal input and output processing unit and system clock and time synchronized maintenance unit.
12. a transmission clock is characterized in that, comprising: border physical entity and intermediate physical entity, wherein:
Described border physical entity is used for gathering message and entering constantly after receiving the message that master clock sends, will enter constantly to multiply by (1) to be added to sync message correction territory, with message transmission to intermediate physical entity; After receiving the message that intermediate physical entity sends, gather going out constantly of message, will go out constantly to multiply by (+1) and be added in the sync message correction territory;
Described intermediate physical entity is used for the physical entity of message transmission to the output port place.
13. transmission clock as claimed in claim 12 is characterized in that, described border physical entity comprises: clock and time signal input and output processing unit, system clock and time synchronized maintenance unit and time-delay correcting process unit, wherein:
Described clock and time signal input and output processing unit are used for realizing that input signal is to the conversion of system clock and time reference source signal; And, realize that system clock and time are to the conversion of output clock and time signal;
Described system clock and time synchronized maintenance unit are used for realizing the synchronous and distribution of system clock and reference source selection, clock and the time of time;
Described time-delay correcting process unit is used for realizing the transparent transmission of signal and the correction of resident time-delay.
14. transmission clock as claimed in claim 13 is characterized in that, described time-delay correcting process unit comprises: enter moment acquisition module, 1588 signal transparent transmissions and go out constantly acquisition module and time-delay correcting process module, wherein:
Describedly enter constantly acquisition module, be used for 1588 signals collecting are entered constantly, and 1588 signals are delivered to 1588 signal transparent transmission modules;
Described 1588 signal transparent transmission modules are used for receiving describedly when entering 1588 signal that acquisition module constantly sends, and 1588 signals are pass-through to the next stage physical entity; When receiving 1588 signal of upper level physical entity transparent transmission, 1588 signal transparent transmissions are provided the correcting process module that constantly gathers and delay time;
Describedly go out constantly to gather and time-delay correcting process module, be used for gathering going out constantly and carrying out the signal lag correcting process of 1588 signals that receive, revised 1588 signals are exported to from clock.
15. transmission clock as claimed in claim 13, it is characterized in that, described intermediate physical entity comprises: clock and time signal input and output processing unit, system clock and time synchronized maintenance unit and time-delay correcting process unit, described time-delay correcting process unit comprises 1588 signal transparent transmission modules, wherein:
Described 1588 signal transparent transmission modules, 1588 signals that are used for the upper level physical entity transparent transmission that will receive are pass-through to the next stage physical entity.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012101173386A CN103378916A (en) | 2012-04-19 | 2012-04-19 | Clock transmission method, boundary clock and transparent clock |
| PCT/CN2013/074098 WO2013155944A1 (en) | 2012-04-19 | 2013-04-11 | Boundary clock, transparent clock, and method for clock transmission |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012101173386A CN103378916A (en) | 2012-04-19 | 2012-04-19 | Clock transmission method, boundary clock and transparent clock |
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| WO2013155944A1 (en) | 2013-10-24 |
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