CN102916758B - Ethernet time synchronism apparatus and the network equipment - Google Patents
Ethernet time synchronism apparatus and the network equipment Download PDFInfo
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Abstract
The invention discloses a kind of Ethernet time synchronism apparatus and the network equipment, main time port recovers clock signal from the primary data from higher level's time synchronism equipment, and on carrying in primary data timestamp information as intermediate data, CPU is according to the master clock signal information in intermediate data, timestamp information and precision interval clock agreement determination adjustment information, time synchronized unit is according to adjustment information adjustment clock signal and synchronization pulse, each time port is sent to by unified after the clock signal after adjustment and synchronization pulse shunt, the quantity of switching device can be reduced and reduce the quantity of the data wire that switching device is connected with time port, can avoid causing device structure complexity high for the quantity of the data wire of transmit clock signal in prior art more, for the problem of the time signal time delay that the data wire Length discrepancy of transmit clock signal causes.
Description
Technical field
The present invention relates to a kind of network communicating system, especially relate to a kind of Ethernet time synchronism apparatus and the network equipment.
Background technology
In a communication network, need the equipment carrying out time synchronized can referred to as time synchronism equipment.Network time synchronization technology main at present comprises IEEE1588 standard.
IEEE1588 is the precise clock synchronization consensus standard of network measure and control system, IEEE1588 standard is the specification of general lifting network system Timing Synchronization ability, work out drafting Primary Reference Ethernet in process, enable distributed communication network have strict Timing Synchronization, and be applied to industrial automation system.Basic conception realizes synchronous by the internal clock of the network equipment (client computer) with the master clock of main control computer by hardware and software, the utilization being less than 10 μ s synchronous settling time is provided, with the Ethernet time of delay 1 not performing IEEE1588 standard, 000 μ s compares, and the Timing Synchronization index of whole network is significantly improved.
Precision interval clock agreement (PTP, PrecisionTimeProtocol) can provide network time synchronization for time synchronism equipment, particularly remote time synchronism equipment.Because this agreement is without the need to setting up special network, but realizing by adding the time synchronized message only taking a small amount of Internet resources on existing network basis, being therefore able to be able to Rapid Popularization in time synchronized field.The specific works principle of this PTP protocol mainly comprises: the ethernet port hardware of the node that each participation is synchronous measures the precise time of precise time that PTP packet leaves and arrival, this node calculates chain circuit transmission time delay and packet in this node time of staying, and is exchanged the information of these practical measurement and calculating by PTP packet and adjacent node.
IEEE1588 is primarily implemented in and transmits high precision clock in ethernet network and the agreement designed, in network arrangement, all devices needs to support IEEE1588 standard, Fig. 1 shows the network device architecture block diagram that application IEEE1588 standard carries out time synchronized, that in system, clock accuracy is the highest is grandmother's clock (GMC, GrandMotherClock), GMC receives the reference signal of GPS broadcast as master clock source, clock signal is passed through local synchronization port P1 by GMC ... Pn send to n boundary clock (BC, BridgeClock) from port S.BC by receiving clock data from port S, then passes through master port M to second line of a couplet equipment or other port transmission clock data.IEEE1588 can solve the bottleneck of commodity ethernet length time of delay and synchronizing capacity difference.In real network running, the ethernet port of application IEEE1588 can either receive the clock signal of higher level equipment transmission as master port M, also as from port S, time signal can be passed to subordinate equipment.
The structured flowchart of the ethernet device as BC has been shown in Fig. 2, the ethernet port be associated, PHY and PTP arithmetic element can be collectively referred to as time port, ethernet port 1, physical layer interface unit 1 form time port 1, ethernet port 2, physical layer interface unit 2 form time port 2, and ethernet port 3, physical layer interface unit 3 form time port 3.Wherein, when a port in ethernet port 1,2,3 is master port, other port is from port, and the time port comprising master port is main time port, comprises from the time port of port for from time port.
Such as, when ethernet port 1 is master port, ethernet port 2, 3 when being from port, BC receives the clock data from upper level clock synchronizer (such as GMC) by ethernet port 1, correction process is carried out by physical layer interface unit 1 pair of clock data, namely the deviation between local clock and master clock and delay is calculated, correct operating frequency and the phase place of local clock, obtain the clock signal after correcting, local clock is set to the clock signal after correcting, wherein, clock signal after correction comprises pulse per second (PPS) (PPS, PulsePerSecond) synchronization pulse and the timestamp transmission of signal carrying timestamp corresponding to each pulse per second (PPS) (Timestamp), by data wire (also be namely clock line for the data wire of transmit clock signal) R_clk1, timestamp transmission of signal is sent to switching device 1, by clock line R_pps1, PPS synchronization pulse is sent to switching device 1, PPS synchronization pulse is sent to ethernet port 2 by clock line pps1to2 by switching device 1 again, timestamp transmission of signal is sent to ethernet port 2 by clock line clk1to2, PPS synchronization pulse is sent to ethernet port 3 by clock line pps1to3, timestamp transmission of signal is sent to ethernet port 3 by clock line clk1to3, ethernet port 1, 2, clock signal is sent to the network equipment be connected separately by 3 respectively, time synchronizing is carried out according to clock signal to make the network equipment be connected.
In like manner, ethernet port 2 is master port, ethernet port 1, 3 when being from port, ethernet port 2 obtains clock signal to the clock data received through correction process, clock signal will be sent to switching device 2 by clock line R_clk2 and clock line R_pps2, PPS synchronization pulse and timestamp transmission of signal are sent to ethernet port 1 by clock line pps2to1 and clock line clk2to1 by switching device 2 respectively, respectively PPS synchronization pulse and timestamp transmission of signal are sent to ethernet port 3 by clock line pps2to3 and clock line clk2to3, ethernet port 1, 2, clock signal is sent to the network equipment be connected separately by 3 respectively, time synchronizing is carried out according to clock signal to make the network equipment be connected.
In like manner, ethernet port 3 is master port, ethernet port 1, 2 when being from port, the clock signal that ethernet port 3 obtains through correction process the clock data received, clock signal is sent to switching device 3 by clock line R_clk3 and clock line R_pps3, PPS synchronization pulse and timestamp transmission of signal are sent to ethernet port 1 by clock line pps3to1 and clock line clk3to1 by switching device 3 respectively, respectively PPS synchronization pulse and timestamp transmission of signal are sent to ethernet port 2 by clock line pps3to2 and clock line clk3to2, ethernet port 1, 2, clock signal is sent to the network equipment be connected separately by 3 respectively, time synchronizing is carried out according to clock signal to make the network equipment be connected.Wherein, CPU 4 and control unit 5 do not participate in the transmission of clock signal.
Known by the principle of the structure shown in Fig. 2 and transmission clock signal thereof, multiple port may be there is in same ethernet device, realize the time signal transmission between ethernet port, will realize switching and transmitting by the logic switch device of multiple complexity, like this, how many ethernet ports are had just to have how many switching devices, also just multiple clock lines is certainly existed, and often increase a port, a switching device will be increased, the quantity of clock line also will increase and decrease in a large number, especially when port number is more, the complexity of device structure will be increased.And the increasing number of clock line, by isometric for the physical length of each for very difficult control clock lines, if the physical length Length discrepancy of clock line, will cause the time delay of time of reception signal between each port.
Visible, in current ethernet device, the quantity that there is clock line causes the problem of the time signal time delay that device structure complexity is high, clock line Length discrepancy causes more.
Summary of the invention
The embodiment of the present invention provides a kind of Ethernet time synchronism apparatus and the network equipment, and the quantity in order to solve the data wire for transmit clock signal existed in prior art causes the problem of device structure complexity time signal time delay that is high, that cause for the data wire Length discrepancy of transmit clock signal more.
Embodiment of the present invention technical scheme is as follows:
A kind of Ethernet time synchronism apparatus, comprising: main time port, N number of from time port, time synchronized unit and CPU; Wherein, N is natural number; Described main time port, for receiving the primary data from higher level's time synchronism equipment, clock signal is recovered from described primary data, the described primary data of the receiving time information of described primary data is received as intermediate data using carrying described main time port, described intermediate data and the described clock signal recovered are sent to described time synchronized unit, and in described intermediate data, carries the transmission time information that described main time port sends described intermediate data; Wherein, carry master clock signal information in described primary data, described receiving time information and described transmission time information form timestamp information; Described time synchronized unit, for sending to described CPU by the intermediate data from described main time port; And, the synchronization pulse that described time synchronized unit generates and the described clock signal received is adjusted respectively according to the adjustment information from described CPU, synchronization pulse after being adjusted and the clock signal after adjusting, be along separate routes N way synchronization pulse and N way clock signal by the clock signal after the synchronization pulse after adjustment and adjustment respectively, and correspondingly sub-synchronization pulse described in sub-clock signal described in a road and a road sent to described in one from time port; Described CPU, for according to determining described adjustment information from described master clock signal information, described timestamp information and the precision interval clock agreement in the described intermediate data of described time synchronized unit, described adjustment information is sent to described time synchronized unit;
Described from time port, for the described sub-clock signal received is sent to described sub-synchronization pulse the network equipment be connected.
A kind of network equipment, comprises Ethernet time synchronism apparatus as above.
According to the technical scheme of the embodiment of the present invention, main time port recovers clock signal from the primary data from higher level's time synchronism equipment, the primary data of the temporal information of primary data is received as intermediate data using carrying main time port, intermediate data is sent to time synchronized unit, and in intermediate data, carry the data message sending intermediate data, the time receiving primary data and the data sending intermediate data form timestamp information, CPU is according to the master clock signal information in intermediate data, timestamp information and precision interval clock agreement determination adjustment information, clock signal after time synchronized unit is adjusted the clock signal adjustment that main time port recovers according to adjustment information, synchronization pulse after the synchronization pulse adjustment generated being adjusted according to adjustment information, and be N way clock signal along separate routes by the clock signal after adjustment, be along separate routes N way synchronization pulse by the synchronization pulse after adjustment, N way clock signal and N way synchronization pulse are sent to N number of from time port accordingly, sub-clock signal is sent to sub-synchronization pulse the network equipment be connected from time port by each, also namely clock signal and synchronization pulse is adjusted by time synchronized unit according to the adjustment information from CPU, each time port is sent to unified after the synchronization pulse shunt after the clock signal after adjustment and adjustment, avoid in prior art and have how many ethernet ports just to have the structure of how many switching devices, thus the quantity of switching device can be reduced and reduce the quantity of the data wire that switching device is connected with time port, can avoid causing for the quantity of the data wire of transmit clock signal the problem that device structure complexity is high in prior art more, and, owing to decreasing the quantity of data wire, be convenient to the length of control data line effectively, the problem of the time signal time delay that the data wire Length discrepancy for transmit clock signal can be avoided to cause.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from specification, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in write specification, claims and accompanying drawing and obtain.
Accompanying drawing explanation
Fig. 1 applies the network device architecture block diagram that IEEE1588 standard carries out time synchronized in prior art;
Fig. 2 is the structured flowchart as the ethernet device of BC in Fig. 1;
The structured flowchart of the Ethernet time synchronism apparatus that Fig. 3 a provides for inventive embodiments;
Fig. 3 b is the workflow diagram of Fig. 3 a shown device;
Fig. 4 a is the preferred enforcement structured flowchart of Fig. 3 a shown device;
Fig. 4 b is the workflow diagram of Fig. 4 a shown device.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the invention are described, should be appreciated that embodiment described herein is only for instruction and explanation of the present invention, is not intended to limit the present invention.
Embodiments provide a kind of Ethernet time synchronism apparatus, Fig. 3 a shows the structured flowchart of this device, as shown in Figure 3 a, this device comprises: main time port 31, N number of from time port 32, time synchronized unit 33 and central processing unit CPU 34; Wherein, N is natural number;
Main time port 31, for receiving the primary data from higher level's time synchronism equipment, clock signal is recovered from primary data, the primary data of the receiving time information of primary data is received as intermediate data using carrying main time port, intermediate data and the clock signal recovered are sent to time synchronized unit 33, and main time port 31 sends the transmission time information of intermediate data on carrying in intermediate data, wherein, carry master clock signal information in primary data, receiving time information and transmission time information form timestamp information; Particularly, the clock signal that recovers of main time port 31 is consistent with master clock signal;
Time synchronized unit 33, for future, the intermediate data of autonomous time port 31 sends to CPU 34; And, according to regulation time lock unit 33 synchronization pulse generated and the clock signal received respectively of the adjustment information from CPU 34, synchronization pulse after being adjusted and the clock signal after adjusting, clock signal after adjustment is consistent with master clock signal, be along separate routes N way synchronization pulse and N way clock signal by the clock signal after the synchronization pulse after adjustment and adjustment respectively, correspondingly a way clock signal and a way synchronization pulse sent to one from time port 32;
CPU 34, for according to from the master clock signal information in the intermediate data of time synchronized unit 33, timestamp information and precision interval clock agreement determination adjustment information, sends to time synchronized unit 33 by adjustment information; Wherein, CPU 34 determines that the method for adjustment information is prior art, intermediate data can be utilized to calculate adjustment information according to precision interval clock agreement (being called in the industry IEEE1588 agreement) in existing CPU, specifically can be realized by many algorithms, differ a citing here;
From time port 32, for the sub-clock signal received is sent to sub-synchronization pulse the network equipment be connected.
The operation principle of Fig. 3 a shown device as shown in Figure 3 b, comprises following processing procedure:
Step 301, main time port 31 receive the primary data from higher level's time synchronism equipment, carry master clock signal information in initial clock data;
Step 302, main time port 31 recover clock signal from primary data, receive the primary data of the receiving time information of primary data as intermediate data using carrying main time port 31;
Intermediate data and the clock signal that recovers are sent to time synchronized unit 33 by step 303, main time port 31;
Step 304, time synchronized unit 33 are while transmission intermediate data, and on also carrying in intermediate data, main time port 31 sends the transmission time information of intermediate data;
Step 305, CPU 34 are according to the master clock signal information in intermediate data, timestamp information and precision interval clock agreement determination adjustment information;
Adjustment information is sent to time synchronized unit 33 by step 306, CPU 34;
The synchronization pulse that step 307, time synchronized unit 33 adjust generation respectively according to the adjustment information from CPU 34 and the clock signal received, the clock signal after the synchronization pulse after being adjusted and adjustment;
Synchronization pulse after clock signal after adjustment and adjustment is along separate routes N way clock signal and N way synchronization pulse by step 308, time synchronized unit 33 respectively, correspondingly a way clock signal and a way synchronization pulse is sent to one from time port 32;
Step 309, sub-clock signal sends to sub-synchronization pulse the network equipment be connected from time port 32 by respectively.
According to device as shown in Figure 3 a and operation principle thereof, main time port recovers clock signal from the primary data from higher level's time synchronism equipment, the primary data of the temporal information of primary data is received as intermediate data using carrying main time port, intermediate data is sent to time synchronized unit, and in intermediate data, carry the data message sending intermediate data, the time receiving primary data and the data sending intermediate data form timestamp information, CPU is according to the master clock signal information in intermediate data, timestamp information and precision interval clock agreement determination adjustment information, clock signal after time synchronized unit is adjusted the clock signal adjustment that main time port recovers according to adjustment information, synchronization pulse after the synchronization pulse adjustment generated being adjusted according to adjustment information, and be N way clock signal along separate routes by the clock signal after adjustment, be along separate routes N way synchronization pulse by the synchronization pulse after adjustment, N way clock signal and N way synchronization pulse are sent to N number of from time port accordingly, sub-clock signal is sent to sub-synchronization pulse the network equipment be connected from time port by each, also namely clock signal and synchronization pulse is adjusted by time synchronized unit according to the adjustment information from CPU, each time port is sent to unified after the synchronization pulse shunt after the clock signal after adjustment and adjustment, avoid in prior art and have how many ethernet ports just to have the structure of how many switching devices, thus the quantity of switching device can be reduced and reduce the quantity of the data wire that switching device is connected with time port, thus can avoid causing for the quantity of the data wire of transmit clock signal the problem that device structure complexity is high in prior art more, and, owing to decreasing the quantity of data wire, be convenient to the length of control data line effectively, the problem of the time signal time delay that the data wire Length discrepancy for transmit clock signal can be avoided to cause.
Fig. 4 a shows the preferred enforcement structured flowchart of Fig. 3 a device, and as shown in fig. 4 a, time synchronized unit 33, specifically comprises: time synchronized module 331 and switching device 332; Main time port 31, specifically comprises: ethernet port 311 and physical layer interface unit 312; From time port 32, specifically comprise: ethernet port 321 and physical layer interface unit 322.
Wherein, the ethernet port 311 of main time port 31 receives the primary data from higher level's time synchronism equipment, and initial clock data are sent to physical layer interface unit 312;
The physical layer interface unit 312 of main time port 31 for recovering clock signal from primary data, the primary data of the receiving time information of primary data is received as intermediate data using carrying ethernet port 311, intermediate data and the clock signal recovered are sent to time synchronized unit 33, and main time port 311 sends the transmission time information of intermediate data on carrying in intermediate data, receiving time information and transmission time information form timestamp information;
The intermediate data of the time synchronized module 331 autonomous time port 31 in future of time synchronized unit 33 sends to CPU 34; And, the synchronization pulse adjusting generation respectively according to the adjustment information from CPU 34 and the clock signal received, synchronization pulse after being adjusted and the clock signal after adjusting, and the synchronization pulse after the clock signal after adjustment and adjustment is sent to switching device 332; Particularly, the synchronization pulse after the clock signal after adjustment and adjustment is sent to switching device 332 by two data lines by time synchronized module 331 respectively;
Switching device 332, for being along separate routes N way clock signal by the clock signal after adjustment, be along separate routes N way synchronization pulse by the synchronization pulse after adjustment, correspondingly a way clock signal and a way synchronization pulse sent to one from time port 32; Particularly, N way synchronization pulse and N way clock signal send to N number of from time port 32 by N to data wire by switching device 332 respectively, wherein, pair of data lines comprises two data lines, and this two data lines is respectively used to the sub-synchronization pulse of transmission of one line and a way clock signal; Preferably, N is all consistent to the length of data wire.
In the middle of practical application, switching device 332 can comprise the first switching device exporting sub-synchronization pulse and the second switch device exporting sub-clock signal, wherein, first switching device is generally clock BUFFER chip, second switch device is generally made up of phase-locked loop chip and clock BUFFER chip, clock signal after wherein phase-locked loop chip is used for adjustment time synchronized module exported becomes 125MHz differential clock signal from 25MHz single-ended signal, is then along separate routes that N way clock signal exports by clock BUFFER chip by the differential clock signal of 125MHz.
From the physical layer interface unit 322 of time port 32, for sending to ethernet port 321 by from the subpulse synchronizing signal of switching device 332 and sub-clock signal;
From the ethernet port 321 of time port 32, for subpulse synchronizing signal is sent to sub-clock signal the network equipment be connected.
Fig. 4 b shows the operation principle of Fig. 4 a shown device, illustrates the operation principle of Fig. 4 a shown device below.
The ethernet port 311 of step 401, main time port 31 receives the primary data from higher level's time synchronism equipment, and initial clock data are sent to physical layer interface unit 312;
The physical layer interface unit 312 of step 402, main time port 31 for recovering clock signal from primary data, the primary data of the receiving time information of primary data is received as intermediate data using carrying ethernet port 311, intermediate data and the clock signal recovered are sent to time synchronized unit 33, and on carrying in intermediate data, main time port 311 sends the transmission time information of intermediate data;
Intermediate data is sent to CPU 34 by step 403, time synchronized module 331;
Adjustment information according to the master clock signal information in intermediate data, timestamp information and precision interval clock agreement determination adjustment information, and is sent to time synchronized unit 33 by step 404, CPU 34;
The synchronization pulse that step 405, time synchronized module 331 adjust generation respectively according to the adjustment information from CPU 34 and the clock signal received, clock signal after being adjusted and the synchronization pulse after adjusting, and by two data lines, the synchronization pulse after the clock signal after adjustment and adjustment is sent to switching device 332;
Clock signal after adjustment is N way clock signal by step 6 406, switching device 332 along separate routes, is N way synchronization pulse along separate routes by the synchronization pulse after adjustment;
N way synchronization pulse and N way clock signal send to N number of from time port 32 by N to data wire by step 407, switching device 332 respectively, wherein, pair of data lines comprises two data lines, and this two data lines is respectively used to the sub-synchronization pulse of transmission of one line and a way clock signal;
Step 408, each sends to ethernet port 321 from the physical layer interface unit 322 of time port 32 by from the subpulse synchronizing signal of switching device 332 and sub-clock signal, and subpulse synchronizing signal is sent to sub-clock signal the network equipment be connected by ethernet port 321.
By device as shown in fig. 4 a and operation principle thereof, the adjustment information that time synchronized module 331 is determined according to CPU 34 adjusts synchronization pulse and clock signal, synchronization pulse after adjustment and clock signal are N way synchronization pulse and N way clock signal by switching device 332 along separate routes, to data wire, N way synchronization pulse and N way clock signal are sent to N number of from time port 32 by N, also namely the clock signal after All Time port repeat is adjusted is concentrated by a switching device 332, avoid in prior art and have how many ethernet ports just to have the structure of how many switching devices, thus the quantity of switching device can be reduced and reduce the quantity of the data wire that switching device is connected with time port, effectively can reduce the quantity of the data wire for transmit clock signal and pulse synchronous signal, thus can solve in prior art and cause for the quantity of the data wire of transmit clock signal the problem that device structure complexity is high more, and, owing to decreasing the quantity of data wire, be convenient to the length of control data line effectively, the problem of the time signal time delay that the data wire Length discrepancy for transmit clock signal can be avoided to cause.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (8)
1. an Ethernet time synchronism apparatus, is characterized in that, comprising: main time port, N number of from time port, time synchronized unit and CPU; Wherein, N is natural number;
Described main time port, for receiving the primary data from higher level's time synchronism equipment, clock signal is recovered from described primary data, the described primary data of the receiving time information of described primary data is received as intermediate data using carrying described main time port, described intermediate data and the described clock signal recovered are sent to described time synchronized unit, and in described intermediate data, carries the transmission time information that described main time port sends described intermediate data; Wherein, carry master clock signal information in described primary data, described receiving time information and described transmission time information form timestamp information;
Described time synchronized unit, for sending to described CPU by the intermediate data from described main time port; And, the synchronization pulse that described time synchronized unit generates and the described clock signal received is adjusted respectively according to the adjustment information from described CPU, synchronization pulse after being adjusted and the clock signal after adjusting, be along separate routes N way synchronization pulse and N way clock signal by the clock signal after the synchronization pulse after adjustment and adjustment respectively, and correspondingly sub-synchronization pulse described in sub-clock signal described in a road and a road sent to described in one from time port;
Described CPU, for according to determining described adjustment information from described master clock signal information, described timestamp information and the precision interval clock agreement in the described intermediate data of described time synchronized unit, described adjustment information is sent to described time synchronized unit;
Described from time port, for the described sub-clock signal received is sent to described sub-synchronization pulse the network equipment be connected.
2. device according to claim 1, is characterized in that, described time synchronized unit, specifically comprises: time synchronized module and switching device;
Described time synchronized module, for sending to described CPU by the intermediate data from described main time port; And, the synchronization pulse adjusting described time synchronized CMOS macro cell respectively according to the adjustment information from described CPU and the described clock signal received, synchronization pulse after being adjusted and the clock signal after adjusting, and the synchronization pulse after the clock signal after described adjustment and described adjustment is sent to described switching device;
Described switching device, for being along separate routes sub-clock signal described in N road by the clock signal after described adjustment, be along separate routes sub-synchronization pulse described in N road by the synchronization pulse after described adjustment, and correspondingly sub-synchronization pulse described in sub-clock signal described in a road and a road sent to described in one from time port.
3. device according to claim 2, is characterized in that, described time synchronized module, specifically for: respectively the synchronization pulse after the clock signal after described adjustment and described adjustment is sent to described switching device by two data lines.
4. device according to claim 2, it is characterized in that, described switching device, specifically for: sub-clock signal described in sub-synchronization pulse described in N road and N road is sent to by data wire respectively N number of described from time port by N, wherein, pair of data lines comprises two data lines, and this two data lines is respectively used to sub-clock signal described in sub-synchronization pulse described in transmission of one line and a road.
5. device according to claim 4, is characterized in that, described N is all consistent to the length of data wire.
6. device according to claim 1, is characterized in that, described main time port, specifically comprises: ethernet port and physical layer interface unit;
Described initial clock data for receiving the primary data from described higher level's time synchronism equipment, and are sent to described physical layer interface unit by described ethernet port;
Described physical layer interface unit, for recovering clock signal from described primary data, the primary data of the receiving time information of described primary data is received as intermediate data using carrying described ethernet port, described intermediate data and the described clock signal recovered are sent to described time synchronized unit, and in described intermediate data, carries the transmission time information that described main time port sends described intermediate data.
7. device according to claim 2, is characterized in that, described from time port, specifically comprises: ethernet port, physical layer interface unit;
Described physical layer interface unit, for sending to described ethernet port by from the described sub-synchronization pulse of described switching device and described sub-clock signal;
Described ethernet port, for sending to described sub-clock signal the network equipment be connected by described sub-synchronization pulse.
8. a network equipment, is characterized in that, comprises the Ethernet time synchronism apparatus according to any one of claim 1 to 7.
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| CN103401672B (en) * | 2013-07-24 | 2016-08-24 | 福建星网锐捷网络有限公司 | Time synchronism apparatus, equipment and system |
| US9541947B2 (en) * | 2013-08-07 | 2017-01-10 | General Electric Company | Time protocol based timing system for time-of-flight instruments |
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| CN101895384A (en) * | 2010-07-07 | 2010-11-24 | 中兴通讯股份有限公司 | Method and device for implementing boundary clock |
| CN102404105A (en) * | 2011-12-14 | 2012-04-04 | 盛科网络（苏州）有限公司 | Device and method for realizing time synchronization on Ethernet switch |
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