CN101114896A - Method for implementing precise synchronization clock - Google Patents
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- CN101114896A CN101114896A CNA2007101069485A CN200710106948A CN101114896A CN 101114896 A CN101114896 A CN 101114896A CN A2007101069485 A CNA2007101069485 A CN A2007101069485A CN 200710106948 A CN200710106948 A CN 200710106948A CN 101114896 A CN101114896 A CN 101114896A
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Abstract
The invention discloses a realization method of a precise synchronization clock and the exact transmission speed of the synchronization clock in the invention can reach a submicrosecond. In the invention, the methods such as a protocol packet of the precise synchronization clock inspected by a hardware FPGA, clock maintenance, software (CPU) computation, correction can be realized. In the FPGA, five modules are designed: a timer manager module, a smii interface module, a packet check module, a spi interface module, and a system state indicating module. In order to ensure the correct acquisition of a time-stamping and system clock maintenance, in a software part seven modules are designed: a data packet transmission module, a timer module, a Sync processing module, a Follow Up processing module, a Delay Req processing module, a Delay Req processing module, a Delay Resp processing module, a managing process to ensure the transmission and receiving of the protocol packet of the precise synchronization clock and system clock maintenance.
Description
Technical field
The present invention relates in measurement and automated system, transmit the precise synchronization clock technical field, be meant especially that at the transmission over networks precise synchronization clock transmission precision of clock can reach the wonderful rank of sub-micro based on Industrial Ethernet.
Background technology
Precise synchronization clock is usually used in the synchronous protocol of Ethernet TCP/IP network such as SNTP or NTP with other and compares, main difference is: precise synchronization clock is to design at more stable and safer network environment, so more simple, network that takies and computational resource are also still less.
Precise synchronization clock is primarily aimed in localized, networked relatively system, and subnet is better, and intraware is relatively stable, is particularly suitable for industrial automation and measurement environment.Different with precise synchronization clock, Network Time Protocol is aimed at the security descriptor of extensive dispersion each autonomous system on the internet.GPS (satellite-based global positioning system) also is aimed at extensively and separately system independently of dispersion.
The network configuration of precise synchronization clock definition can make the precision that self reaches very high, sets the unactivated state that redundant network path enters the precise synchronization clock agreement.Opposite with SNTP and NTP, the time seal is easier to be realized on hardware, and is not limited to application layer, and this makes PTP can reach microsecond with interior precision.In addition, the modular design of PTP also makes it be easy to adapt to low side devices.
The precision interval clock agreement will reach the synchronous accuracy in the wonderful scope of sub-micro, it is applicable to the finite element network field of the time synchronized that need realize pinpoint accuracy distribution clock, when distributing Control work, need not to carry out again special synchronous communication, thereby reached the effect that call duration time pattern and application program time of implementation pattern are separated.The big advantage of another of precise synchronization clock is that its standard is very representative, and is open.In the middle of their product, same standard is followed in the production commercial city of distinct device with this standard application in the supplier of many control system, guarantees good synchronism between the product.
Summary of the invention
In view of this, the invention provides a kind of method based on Industrial Ethernet transmission precise synchronization clock.The present invention includes two parts hardware detection, acquisition time stamp, the implementation method of safeguarding clock and software transmitting-receiving precise synchronization clock protocol massages, adjustment, critique system clock; For the technical scheme of the present invention that achieves the above object is to realize like this.
Description of drawings
Fig. 1 hardware principle block diagram
Fig. 2 FPGA program work theory diagram
Fig. 3 smii sequential chart
Fig. 4 data message transceiver module flow chart
Fig. 5 timer module flow chart
Fig. 6 Sync processing module flow chart
Fig. 7 Follow_Up processing module flow chart
Fig. 8 Delay_Req processing module flow chart
Fig. 9 Delay_Resp processing module flow chart
Figure 10 system management module block diagram
Figure 11 writes sequential
Figure 12 reads sequential
Embodiment
1.1 overall plan
The precision net synchronous protocol of the present invention's definition has been realized the high level of synchronization in the network, make and when distributing Control work, need not to carry out again special synchronous communication, thereby reached the effect that call duration time pattern and application program time of implementation pattern are separated, its step comprises:
● select optimized master clock, from all clock nodes, select optimized master clock according to optimized master clock algorithm
● the offset measurement stage is used for revising the time difference of master clock and slave clock.In this offset correction process, master clock cycle sends a definite synchronizing information (being called for short Sync information) (being generally per two seconds once), and it has comprised a time seal (time stamp), has accurately described the scheduled time that packet sends.
● delay measurements (delay measurement) stage is used for need to prove the time of delay that the Measurement Network transmission causes, in this measuring process, supposes that transmission medium is symmetrically and evenly.
● through the exchange of synchronizing information, slave clock and master clock have been realized precise synchronization.
1.2 hardware implementations
The mode that adopts hardware and software to realize, its hardware is realized the following Fig. 1 of theory diagram:
This precision interval clock synchronous protocol realizes that principle is as above shown in Figure 1, guaranteeing on the normal basis of ethernet communication, signal is connected on the PHY chip simultaneously, link to each other with fpga chip by the SMII interface, adopt the mode of monitoring the Ethernet data bag, by the details of FPGA extracting Ethernet data bag, obtain the clock synchronization information of Ethernet data bag, thereby realized accurate clock synchronization protocol.
The realization theory diagram of FPGA program is illustrated in fig. 2 shown below, owing to adopt the pattern of monitoring, FPGA only resolves the data that PHY receives, behind its data of receiving process FIFO, by parse module, the relevant informations such as timestamp in its packet are solved, by realizing data interaction between spi bus and the cpu, safeguard clock system simultaneously, thereby realize this accurate clock synchronization protocol.
Utilize FPGA to assist CPU to safeguard in the system and the adjustment clock, catch and resolve the PTP message.Utilize FPGA can make system design more flexible, effectively the maintenance system clock is determined PTP message due in accurately, thereby effectively reduces the deviation of local clock and grandmasterclock, improves systematic function.Can reduce simultaneously CPU and handle the PTP message time, make it have the more time to handle other tasks.
■ FPGA indoor design five modules: Clock management module (timer_manager), smii interface module (smii_interface), packet parsing module (packet_check), spi interface module (spi_interface), network connection state indicating lamp module.Interface is clear between each module, and the division of labor is clear and definite, and cooperation is smooth.
■ smii interface module (smii_interface) is responsible for providing reset signal to the phy interface chip, clock signal, and control signal and synchronizing signal, the work of control and management phy interface chip makes it that Ethernet data can correctly be provided.
■ packet parsing module (packet_check) is responsible for analytic message, and provides locking signal to the Clock management module, locking message due in, and the information such as PTP message id after will resolving note, and offer the Clock management module, by its management.
■ Clock management module (timer_manager) is responsible for safeguarding local clock, recorded message due in, and administrative message information.
■ spi interface module is responsible for passing on cpu order to the Clock management module, and the message due in value and the message relevant information of Clock management module records passed to cpu.
■ network connection state indicating lamp module is responsible for the indication network wire connection state.
Wherein packet parsing module (packet_check) waveform such as Fig. 3
Packet parsing module (packet_check) receives and analytic message according to the smii sequential.Arrange 96bits FIFO to receive the rxd data in the module.At first from RXD (data-signal that the PHY chip provides), parse the RX_DV signal, when the RX_DV signal is effective, the RXD data are preserved among the FIFO, design counter_bits record data position, every input 8 bit data just compare data among the FIFO and PREAMBLE, SFD, are that Ethernet data is unwrapped head if unanimity just shows, produce lock pulse, the recorded message due in is simultaneously with the counter_bits zero clearing.Derive counter_bytes message data byte counter by counter_bits.We judge the UDP PORT (udp port number) of message, IP multicast adderss (ip multicast address) field, to determine whether message is the PTP message, if PTP message, then further judge messagetype and control field, determine that sync still is the delay_req message, simultaneously packet uid, port number, the sequence number information of recorded message.
1.3 software implementation method
■ data message transceiver module: be responsible for receiving and sending the precise synchronization clock data message.See Fig. 4.
■ timer module: be responsible for handling the information relevant in the precise synchronization clock agreement, comprise timed sending sync, thereby the overtime port of checking enters the master port state and receives the overtime respective handling of sync as the master clock port with the time.See Fig. 5.
■ Sync processing module: responsible processing receives the respective handling behind the sync data message.See Fig. 6.
■ Follow_Up processing module: responsible processing receives the respective handling behind the Follow_Up data message.See Fig. 7.
■ Delay_Req processing module: responsible processing receives the respective handling behind the Delay_Req data message.See Fig. 8.
■ Delay_Resp processing module: responsible processing receives the respective handling behind the Delay_Resp data message.See Fig. 9.
The ■ system management module: be responsible for to whole precise synchronization clock agreement configuration, running status detection etc.
As Figure 10.
2 specifically implement
2.1 hardware principle
Adopt self-defining 3 line interfaces to realize communication between CPU and the FPGA, and this interface is the shared bus-type interfaces of many integrated circuit boards, the The data broadcast type is issued by CPU, comprise address information in the downward message, the integrated circuit board that has only 1 address to conform to is simultaneously replied instruction, and other integrated circuit boards then are in the state of intercepting.
The INT signal is that hardware sends emergency to CPU, the signal that notice CPU in time inquires about.
Wherein CPU is as the Master of bus, and FPGA is as the Slave of bus.
2.2 protocol specification
2.2.1 protocol interface sequential
The spi bus standard of this protocol specification normative reference, the following Figure 11 of interface sequence, Figure 12.
2.2.2 protocol instructions form
Read instruction
The form that reads instruction is as follows:
Bit7….. bit0
<CMD，CARD ID，R><REG ADDR><DATA0>…<DATAn>
Illustrate:
Each＜between be the 8bit data
2.CMD be the command field, account for 3bit, be 011 in this agreement
3.REG ADDR is the FPGA register address, accounts for 1Byte
4.DATA0 ~ DATAn is the data that Slave returns to Master, the length of concrete n is by concrete register specifications
Write command
The write command form is as follows:
Bit7….. bit0
<CMD，CARD ID，W><REG ADDR><DATA0>…<DATAn>
Illustrate:
Each＜between be the 8bit data
2.CMD be the command field, account for 3bit, be 011 in this agreement
3.REG ADDR is the FPGA register address, accounts for 1Byte
4.DATA0 ~ DATAn is the parameter that Master writes to Slave, the length of concrete n is by concrete register specifications
CARD ID：
| 0x00 | GE interface board slot position |
| 0x05 | FE interface |
| 0x06 | FE interface board slot position 2 |
| 0x07 | FE interface board slot position 3 |
| 0x08 | FE interface board slot position 4 |
| 0x09 | FE interface board slot position 5 |
| 0x0A | FE interface board slot position 6 |
2.2.3 agreement classification
The global register Table A:
| Register address | Read-write | Length Bytes | Register name | Describe | |
| | RO | 1 | Version | Hardware version numbers | software version number | |
| 0x01 | RW | 4 | Timer_S | The clock of current integrated circuit board (second) value | |
| 0x05 | RW | 4 | Timer_NS | The clock of current integrated circuit board (nanosecond) value | |
| 0x09 | WO | 9 | OFFSET | Clock is adjusted (nanosecond) value, and symbol is arranged | |
| 0xE | RO | 3 | -- | No used | |
| 0x20 | RO | 21 | PTP_RXD_P1 | Read the SYNC/Delay_Req message timestamp of Port1 RXD | |
| 0x38 | RO | 21 | PTP_TXD_P1 | Read the SYNC/Delay_Req message timestamp of Port1 TXD | |
| 0x50 | RO | 21 | PTP_RXD_P2 | Read the SYNC/Delay_Req message timestamp of Port2 RXD | |
| 0x68 | RO | 21 | PTP_TXD_P2 | Read the SYNC/Delay_Req message timestamp of Port2 TXD |
| 0x80 | RO | 21 | PTP_RXD_P3 | Read the SYNC/Delay_Req message timestamp of Port3 RXD |
| 0x98 | RO | 21 | PTP_TXD_P3 | Read the SYNC/Delay_Req message timestamp of Port3 TXD |
| 0xB0 | RO | 21 | PTP_RXD_P4 | Read the SYNC/Delay_Req message timestamp of Port4 RXD |
| 0xC8 | RO | 21 | PTP_TXD_P4 | Read the SYNC/Delay_Req message timestamp of Port4 TXD |
Global register table B:
| Register address | Register name | Describe |
| 0x00 | Version | Hardware version numbers | software version number |
| 0x01~0x04 | Timer_S | The clock of current integrated circuit board (second) value |
| 0x05~0x08 | Timer_NS | The clock of current integrated circuit board (nanosecond) value |
| 0x09~0x0D | OFFSET | Clock is adjusted (nanosecond) value, and symbol is arranged |
| 0x0E~0x0F | Keep | |
| 0x20~0x34 | PTP_RXD_P1 | Read the SYNC/Delay Req newspaper of Port1 RXD The literary composition timestamp |
| 0x35~0x37 | Keep | |
| 0x38~0x4C | PTP_TXD_P1 | Read the SYNC/Delay Req newspaper of Port1 TXD The literary composition timestamp |
| 0x4D~0x4F | Keep | |
| 0x50~0x64 | PTP_RXD_P2 | Read the SYNC/Delay Req newspaper of Port2 RXD |
| The literary composition timestamp | ||
| 0x65~0x67 | Keep | |
| 0x68~0x7C | PTP_TXD_P2 | Read the SYNC/Delav Req newspaper of Port2 TXD The literary composition timestamp |
| 0x7D~0x7F | Keep | |
| 0x80~0x94 | PTP_RXD_P3 | Read the SYNC/Delay Req newspaper of Port3 RXD The literary composition timestamp |
| 0x95~0x97 | Keep | |
| 0x98~0xAC | PTP_TXD_P3 | Read the SYNC/Delay Req newspaper of Port3 TXD The literary composition timestamp |
| 0xAD~0xAF | Keep | |
| 0xB0~0Xc4 | PTP_RXD_P4 | Read the SYNC/Delav Req newspaper of Port4 RXD The literary composition timestamp |
| 0xC5~0xC7 | Keep | |
| 0xC8~0xDC | PTP_TXD_P4 | Read the SYNC/Delay Req newspaper of Port4 TXD The literary composition timestamp |
| 0xDD~0xFF | Keep |
2.2.4 hardware version numbers | software version number
REG ADD＝0x00
| Bit | Name | R/W | Description | Default |
| 7:4 | Software version | RO | The FPGA program version of current integrated circuit board | |
| 3:0 | Hardware | RO | The integrated circuit board type of current integrated circuit board |
| Type | ● 0001:4 FE interface ● 0010: single mode optical interface, FE, FE, FE ● 0011: multi-mode optical interface, FE, FE, FE ● 0100: single mode optical interface, FE, FE, single mode optical interface ● 0101: multi-mode optical interface, FE, FE, multi-mode optical interface ● 0110: single mode optical interface, single mode optical interface, single mode optical interface, FE ● 0111: multi-mode optical interface, multi-mode optical interface, multi-mode optical interface, FE ● 1000:4 interface all is single mode optical interface ● 1001:4 interface all is multi-mode optical interface ● 1111: no integrated circuit board ● other: keep |
2.2.5 the clock of current integrated circuit board (second) value
REG ADD＝0x01
| Bit | Name | R/W | Description | Default |
| 31:0 | Time of Seconds | RO | The clock of current integrated circuit board (second) |
00000000 |
2.2.6 the clock of current integrated circuit board (nanosecond) value
REG ADD＝0x05
| Bit | Name | R/W | Description | Default |
| 31:0 | Time of nS | RO | The clock of current integrated circuit board (nanosecond) |
00000000 |
2.2.7 clock adjustment (nanosecond) value has symbol
REG ADD＝0x09
| Bit | Name | R/W | Description | Default |
| 71 | Offset Flag | WO | The sign that need adjust if FPGA finishes adjustment, can be 0 with this FLAG set ● 1: need carry out the clock adjustment ● 0: do not need to carry out the clock adjustment | |
| 70:65 | Reserved | RO | Keep | |
| 64 | Offset direction | WO | Need to adjust just/negative ● 0: present clock need deduct adjusted value ● 1: present clock need add adjusted value | |
| 63:32 | Offset of Seconds | WO | Be worth the second that needs to adjust | |
| 31:0 | Offset of nS | WO | The nS numerical value that needs adjustment |
2.2.8 read the SYNC/Delay_Req message timestamp of Port1 RXD
REG ADD＝0x20
| Bit | Name | R/W | Description | Default |
| 167 | Flag | RO | Obtain the PTP message flag | 0 |
| ● 1: obtain a PTP message, and this message is not read by CPU ● 0: do not obtain the PTP message, or this PTP message is read correctly by CPU | ||||
| 166:160 | Reserved | RO | 0 | |
| 159:128 | PTP Timer of Seconds | RO | Second value when obtaining this PTP message | 0 |
| 127:96 | PTP Timer of nS | RO | Nanosecond value when obtaining this PTP message | 0 |
| 95:88 | MessageType | RO | Obtain the MessageType value in the PTP message | 0 |
| 87:80 | SourceCommunicationTechno logy | RO | Obtain the SourceCommunicationTechno logy value in the PTP message | 0 |
| 79:32 | SourceUuID | RO | Obtain the SourceUuID value in the PTP message | 0 |
| 31:16 | SourcePortID | RO | Obtain the SourcePortID value in the PTP message | 0 |
| 15:0 | SequenceID | RO | Obtain the SequenceID value in the PTP message | 0 |
2.2.9 read the SYNC/Delay_Req message timestamp of Port1 TXD
REG ADD＝0x38
| Bit | Name | R/W | Description | Default |
| 167 | Flag | RO | Obtain the PTP message flag ● 1: obtain a PTP message, and | 0 |
| This message is not read by CPU ● 0: do not obtain the PTP message, or this PTP message is read correctly by CPU | ||||
| 166:160 | Reserved | RO | 0 | |
| 159:128 | PTP Timer of Seconds | RO | Second value when obtaining this PTP message | 0 |
| 127:96 | PTP Timer of nS | RO | Nanosecond value when obtaining this PTP message | 0 |
| 95:88 | MessageType | RO | Obtain the MessageType value in the PTP message | 0 |
| 87:80 | SourceCommunicationTechno logy | RO | Obtain the SourceCommunicationTechno logy value in the PTP message | 0 |
| 79:32 | SourceUuID | RO | Obtain the SourceUuID value in the PTP message | 0 |
| 31:16 | SourcePort ID | RO | Obtain the SourcePortID value in the PTP message | 0 |
| 15:0 | SequenceID | RO | Obtain the SequenceID value in the PTP message | 0 |
Claims (15)
1. the implementation method of a precise synchronization clock is characterized in that based on Ethernet transmission precise synchronization clock, makes to need not the special isochronous communication channel of reallocating when making up the control system network.The present invention includes that two parts hardware detection, extraction time are stabbed, the method for the implementation method of maintenance system clock and software transmitting-receiving precise synchronization clock protocol massages, adjustment, critique system clock.The precision of its precise synchronization clock can reach the wonderful level of sub-micro.
2. according to the described method of claim one, it is characterized in that hardware detection precise synchronization clock message, acquisition time stab, the maintenance system clock; Hardware is realized comprising smii interface module (smii_interface), packet parsing module (packet_check) Clock management module (timer_manager), spi interface module (spi_interface), system mode indicating module.
3. according to claim one, the described method of claim two, it is characterized in that Clock management module (timer_manager) is responsible for maintenance system clock, recorded message due in, and the information that E-Packets.
4. according to claim one, the described method of claim two, it is characterized in that, smii interface module (smii_interface) is responsible for providing reset signal to the phy interface chip, clock signal, control signal and synchronizing signal, the work of control and management phy interface chip makes it that Ethernet data can correctly be provided.
5. according to claim one, the described method of claim two, it is characterized in that, packet parsing module (packet_check) is responsible for analytic message, and provide locking signal to the Clock management module, locking message due in, and the information such as precise synchronization clock protocol massages id after will resolving note, and offer the Clock management module.
6. according to claim one, the described method of claim two, it is characterized in that the spi interface module is responsible for communicating by letter between FPGA and the CPU, the message due in value and the message relevant information of Clock management module records passed to CPU.
7. according to the described method of claim one, it is characterized in that, software transmitting-receiving precise synchronization clock protocol massages, adjustment, critique system clock, this part has comprised data message transceiver module, timer module, Sync processing module, Follow_Up processing module, Delay_Req processing module, Delay_Resp processing module, system management module.
8. according to claim one, the described method of claim seven, it is characterized in that the data message transceiver module is responsible for receiving and sending the precise synchronization clock protocol massages.
9. according to claim one, the described method of claim seven, it is characterized in that, timer module is responsible for handling the precise synchronization clock agreement information relevant with the time, comprise timed sending sync, thereby the overtime port of checking enters the master port state and receives the overtime respective handling of sync as the master clock port.
10. according to claim one, the described method of claim seven, it is characterized in that the Sync processing module is responsible for handling the respective handling that receives behind the sync data message.
11., it is characterized in that the Follow_Up processing module is responsible for handling the respective handling that receives behind the Follow_Up data message according to claim one, the described method of claim seven.
12., it is characterized in that the Delay_Req processing module is responsible for handling the respective handling that receives behind the Delay_Req data message according to claim one, the described method of claim seven.
13., it is characterized in that the Delay_Resp processing module is responsible for handling the respective handling that receives behind the Delay_Resp data message according to claim one, the described method of claim seven.
14., it is characterized in that system management module is responsible for the configuration to whole precise synchronization clock agreement, running status detection etc. according to claim one, the described method of claim seven.
15. according to claim one, claim two, the described method of claim seven, it is characterized in that, in the process of transmission and check and correction clock, at first select optimized master clock, from all clock nodes, select optimized master clock according to optimized master clock algorithm; Secondly the offset measurement stage is used for revising the time difference of master clock and slave clock.In this offset correction process, master clock cycle sends a definite synchronizing information (being called for short Sync information) (being generally per two seconds once), and it has comprised a time seal (time stamp), has accurately described the scheduled time that packet sends; Delay measurements (delay measurement) stage is used for passing through the exchange of synchronizing information at last the time of delay that the Measurement Network transmission causes once more, and slave clock and master clock have been realized accurate synchronous.
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