CN110350913A - A kind of more ADC synchronizing devices based on locking phase delay - Google Patents
A kind of more ADC synchronizing devices based on locking phase delay Download PDFInfo
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- CN110350913A CN110350913A CN201910554891.8A CN201910554891A CN110350913A CN 110350913 A CN110350913 A CN 110350913A CN 201910554891 A CN201910554891 A CN 201910554891A CN 110350913 A CN110350913 A CN 110350913A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1285—Synchronous circular sampling, i.e. using undersampling of periodic input signals
Abstract
The invention discloses a kind of more ADC synchronizing devices based on locking phase delay, it first passes through FPGA and generates clock sync signal SYNC and SPI control command, clock generator and impulse generator first carry out initial configuration under SPI control command, and successively first order phaselocked loop and second level phaselocked loop are locked, the phase-locked loop structures of double cascade connection types of Clock Tree structural union are then based on, realize the synchronous reset signal of more ADC.
Description
Technical field
The invention belongs to signal processing technology fields, more specifically, it is same to be related to a kind of more ADC based on locking phase delay
Walk device.
Background technique
In high-speed data acquistion system, sample rate is improved usually using multi-ADC parallel acquisition array.In parallel acquisition
Occasion, the reset to more ADC, directly influences the synchronization of ADC output data, finally influences whether the correct reconstruct of data.Cause
This, realizes that stablizing for multi-disc ADC resets, and guaranteeing that the acquisition of multi-disc ADC synchronizes is design key.
Due to the difference of the lag characteristic between the PCB trace and discrete component of collection plate, directly contributes synchronization signal and exist
Delay length on respective path is inconsistent.If synchronization signal is reset between the metastable zone of sampling clock, eventually result in
It is two different as a result, the output of ADC acquisition data has the difference of a sampling clock cycle, as shown in Figure 1.
Multi-disc ADC reset signal is other than between the metastable zone for needing to avoid resetting, it is also necessary to act on the same reset
Section.The acquisition data of ADC are exported under the action of sampling clock, when reset signal acts on different sampling intervals
When, the data of output can postpone by different sampling clock cycles, as shown in Figure 2.
Therefore, in order to guarantee acquire data correct reconstruct, need by adjust reset pulse delay so that reset letter
Number act on the same stable region.In previous reset circuit design, using the design method of multi-level pmultistage circuit.The circuit
By PLL, FPGA, d type flip flop, multichannel is fanned out to device and programmable delay chip composition, realization structure are as shown in Figure 3.
For this method using phaselocked loop to FPGA, d type flip flop provides homologous clock, and FPGA generates single reset pulse, D touching
Hair device synchronizes triggering to reset pulse, and multichannel is fanned out to device and single pulse is driven to 8 pulses, and delayer is to respective pulse
Delay adjusting is carried out, ADC is can finally be provided to and is resetted.
In the circuit of the above multilevel structure, all there is independent component in every level-one, while in the placement-and-routing of PCB, each
The track lengths of paths are all inconsistent.Due to PCB trace delay and discrete component delay be affected by temperature it is larger, in temperature
When degree variation, reset signal is be easy to cause to act between metastable zone or in next reset section, to multi-channel A/D C's
Stablize reset strap to adversely affect.Therefore, it is necessary to design a kind of synchronous reset device of Low Drift Temperature.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of synchronous dresses of more ADC based on locking phase delay
It sets, by using the phase-locked loop structures of double cascade connection types of Clock Tree structural union, the clock ensure that reset circuit is same
Source property reduces output delay because temperature is affected.
For achieving the above object, a kind of more ADC synchronizing devices based on locking phase delay of the present invention, which is characterized in that
It include: FPGA, clock generator, impulse generator and multi-disc ADC；
The FPGA is for generating clock sync signal SYNC and SPI control command, then by clock sync signal SYNC
It is sent to clock generator, SPI control command is sent to clock generator and impulse generator simultaneously；
The clock generator first carries out initial configuration under SPI control command, and successively to first order phaselocked loop
It is locked with second level phaselocked loop；Then under the excitation of clock sync signal, it is aligned the phase of internal frequency divider, is produced
The sampled clock signal of multi-disc ADC, and be distributed to per a piece of ADC；Meanwhile clock generator generate all the way reference clock signal and
Pulse synchronous signal and it is sent to impulse generator all the way, wherein reference clock believes the source clock as impulse generator, pulse
Synchronization signal synchronizes reset to impulse generator；
The impulse generator first carries out initial configuration under SPI control command, and successively to first order phaselocked loop
It is locked with second level phaselocked loop；Then under the excitation of pulse synchronous signal, make impulse generator output end keep with
The phase alignment of clock generator, then, impulse generator carry out multichannel driving to the source clock of input, produce multipath delay
Adjustable synchronization pulse, and be distributed to per a piece of ADC；
The ADC carries out reset operation according to synchronization pulse, then carries out letter when sampled clock signal arrives
Number sampling.
Goal of the invention of the invention is achieved in that
A kind of more ADC synchronizing devices based on locking phase delay of the present invention, first pass through FPGA and generate clock sync signal SYNC
With SPI control command, clock generator and impulse generator first carry out initial configuration under SPI control command, and successively right
First order phaselocked loop and second level phaselocked loop are locked, and the locking phase of double cascade connection types of Clock Tree structural union is then based on
Ring structure realizes the synchronous reset signal of more ADC.
Meanwhile a kind of more ADC synchronizing devices based on locking phase delay of the present invention also have the advantages that
(1), synchronous reset device is made of clock generator and impulse generator, provides equipment clock resource abundant
With flexible impulse generator function；
(2), the usage quantity for reducing discrete component ensure that the clock homology of reset circuit；
(3), the phase-locked loop structures based on double cascade connection types are affected by temperature output delay smaller, meet the present invention to low
The requirement of temperature drift performance.
Detailed description of the invention
Fig. 1 is ADC reset timing figure；
Fig. 2 is more ADC reset timing figures；
Fig. 3 is existing more ADC synchronous reset circuit realization principle figures；
Fig. 4 is a kind of more ADC synchronizing device schematic diagrams based on locking phase delay of the present invention；
Fig. 5 is charge pump phase lock loop structure chart；
Fig. 6 is double cascade connection type phase-locked loop structures figures；
Fig. 7 is the temperature curve of analogue delay
Fig. 8 is the global configuration block diagram of output channel.
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Embodiment
Fig. 4 is a kind of more ADC synchronizing device schematic diagrams based on locking phase delay of the present invention.
In the present embodiment, as shown in figure 4, a kind of more ADC synchronizing devices based on locking phase delay of the present invention, comprising:
FPGA, clock generator, impulse generator and multi-disc ADC.
FPGA is used to generate clock sync signal SYNC and SPI control command, then clock sync signal SYNC is sent to
SPI control command is sent to clock generator and impulse generator by clock generator simultaneously.
Clock generator and impulse generator use clock tree construction using the phase-locked loop structures of double cascade connection types between the two
Connection type；
The phase-locked loop structures of double cascade connection types include first order phaselocked loop and second level phaselocked loop, and every level-one phaselocked loop is by electricity
Lotus pump-type phase-locked loop structures；
Wherein, as shown in figure 5, charge pump type phaselocked loop structure includes phase discriminator, charge pump CPPFD, loop filter LF,
Voltage controlled oscillator VCO and frequency divider 1/N.Its phase locking process is as follows:
(1), phase discriminator carries out the comparison of phase difference to the reference clock and feedback clock of input, and output voltage is compared with
As a result directly proportional.
(2), charge pump carries out charge/discharge operation to loop according to the output voltage after phase demodulation.
(3), loop filter has low-pass nature, and charge pump current can be converted to the control electricity of voltage controlled oscillator
Pressure, and filter out radio-frequency component.
(4), the output frequency model- following control voltage linear variation of voltage controlled oscillator.
(5), frequency divider divides output signal.And feed back to the comparison end of phase discriminator.
Under the action of loop control voltage, output frequency follows input frequency variation, when the input frequency at phase discriminator both ends
When rate and equal feedback frequency, that is, realizes locking and require.
As shown in fig. 6, the course of work of the phase-locked loop structures of double cascade connection types is as follows:
Crystal oscillator is as reference source with high precision for first order loop, according to above-mentioned locking phase principle: as fin/R=fvcxo/N,
The locking of loop realization frequency and phase.When first order loop-locking, to second level loop provide one precisely, low noise
Reference clock.One internal voltage controlled oscillator of use of second level loop realizes clock multiplier, when the loop-locking of the second level, can produce
Give birth to and distribute a plurality of types of clock sources.
Clock tree construction, using clock generator as master clock chip, using impulse generator as branch's chip；It is main
Clock chip is using external crystal-controlled oscillation as reference source, input of the clock as rear class impulse generator of output high-precision, Low phase noise
Clock；In every level-one of Clock Tree, the clock chip of prime provides pulse synchronous signal and carries out phase to branch's chip of rear class
Alignment, so that realizing more accurate synchronization between each output.
The specific workflow of clock generator and impulse generator is described in we below:
Clock generator first carries out initial configuration under SPI control command, and successively to first order phaselocked loop and second
Grade phaselocked loop is locked；Then under the excitation of clock sync signal, it is aligned the phase of internal frequency divider, produces multi-disc
The sampled clock signal of ADC, and be distributed to per a piece of ADC；Meanwhile clock generator generates reference clock signal and all the way all the way
Pulse synchronous signal is simultaneously sent to impulse generator, wherein reference clock believes the source clock as impulse generator, impulsive synchronization
Signal synchronizes reset to impulse generator；
Impulse generator first carries out initial configuration under SPI control command, and successively to first order phaselocked loop and second
Grade phaselocked loop is locked；Then under the excitation of pulse synchronous signal, the output end of impulse generator is made to keep raw with clock
The phase alignment grown up to be a useful person, then, impulse generator carry out multichannel driving to the source clock of input, and it is adjustable to produce multipath delay
Synchronization pulse, and be distributed to per a piece of ADC；
ADC carries out reset operation according to synchronization pulse, then carries out signal sampling when sampled clock signal arrives.
Wherein, the output that the reset operation of ADC adjusts pulse using analogue delay and digital related method thereof postpones；
If analogue delay minimal adjustment stepping is ADly=25ps, number of steps is up to AStep=23；Digital delay is minimum
Adjusting stepping is DDly=200ps, and number of steps is up to DStep=17；When retardation is greater than the adjusting of T=1/2VCO, use
The method of digital delay is less than retardation the adjusting of T=1/2VCO, the method for sampling analogue delay；
Specific implementation steps are as follows:
(1), initialization delay value is sent；
(2), analogue delay amount is incrementally increased, ADC output data can successively undergo stable, unstable state；
(3), according to unstable twice central value AStep1, AStep2, the retardation for stablizing reset is calculated
AStep0=(AStep1+AStep2)/2；
(4), setting analogue delay amount is AStep0, realizes that stablizing for monolithic ADC resets；
(5), when more ADC reset at different sections, digital delay amount DStep=DStep+2, i.e. pulse daley are adjusted
One sampling clock cycle, so that synchronization signal resets at next stable period；
(6), on the basis of monolithic ADC stablizes, step (5) successively is repeated to multi-disc ADC, finally realize that more ADC's is steady
It is fixed to reset.
Example
Clock generator of the invention selects the HMC7044 of ADI company, and impulse generator selects ADI company
HMC7043.Two kinds of devices have similar characteristic, can be configured to equipment clock or SYSREF pulse mode.HMC7044/
7043 provide 14 output channels, highest output frequency 3.2GHz, while having channel frequency dividing, delay and synchronous function, defeated
Level standard supports LVDS, LVPECL, CML and LVCMOS out.In addition to this, the output of HMC7044/7043 clock or pulse is prolonged
Late be influenced by temperature it is smaller, as shown in Figure 7.The analogue delay step value of clock chip is 25ps, with prolonging for analogue delay
Amount increases late, and the influence of temperature increases with it.In -40 degrees Celsius to 85 degrees Celsius, delayed impact is no more than
100ps has biggish performance boost compared to previous method.Therefore, it is low to meet the present invention for the performance indicator of HMC7044/7043
The design requirement of temperature drift synchronizing function.
Using high-precision 10MHz crystal oscillator as reference source, the loop filter of first order loop uses clock generator
Narrow bandwidth design, voltage controlled oscillator use external 100MHz VCXO, and the loop filter of second level loop is set using wide bandwidth
Meter, voltage controlled oscillator use internal VCO.Exported after final locking 8 road 2.5GHz, low jitter, out of phase sampling clock, one
The source clock of road 2.5GHz and all the way SYNC synchronization signal.
Impulse generator has the function of that pulse generates and be fanned out to buffering.The impulse generator of the present embodiment is generated with clock
The clock of the 2.5GHz of device output generates and distributes 8 road lock-out pulses after precise synchronization as source clock.Finally by
The analogue delay or digital delay for adjusting impulse generator, so that reset signal acts on stable sampling interval.
The lock-out pulse of the present embodiment has mainly used the SYSREF pulse generation method of HMC7044/7043, and this method is not
It is same as the generation method of equipment clock, is mainly manifested in pulse setting and the configuration of output channel difference.
The Typical Disposition that pulse and clock generate is as shown in table 1:
Table 1
Channel frequency divider is divided to the clock after frequency multiplication of phase locked loop, supports 2 to 4096 even frequency division and 1,3,5
Frequency division by odd integers, and have 50% duty ratio.Since the count value of SYSREF timer is no more than the limitation of 4MHz, determine
The size of the frequency division value is larger.By constantly testing, final verifying is under the input clock of 2.5GHz, under SYSREF pulse mode
The frequency division value at least should be 256.
Start-up mode is divided into asynchronous and dynamic start-up mode, and asynchronous mode, that is, general mode generates, such as equipment clock
Fruit SYNC enables to be 1, then carries out phase alignment by SYNC event.Dynamic mode, that is, impulse generator mode is used for SYSREF
Pulse generates, if frequency divider receives impulse generator event, powers on before pulse generation, then carries out phase pair
Together, the power down after pulse generation.
Finely tune the delay of the adjustable divider signals of analogue delay, stepping 25ps, most adjustable 23 steppings, maximum
Retardation is 575ps.Coarse tune digital postpones adjustable divider phase, and stepping is 1/2 VCO period, and at most adjustable 17
Period, maximum delay amount are 3400ps.The present invention by accurately postpone adjust guarantee sampling clock phase and ADC it is steady
It is fixed to reset.
When jump mutually can allow for frequency divider to receive SYNC event, the phase adjusted in a VCO period is carried out.Multi-hop
Enabled then be to allow multiple phase adjusted, regulated quantity is multi-hop number × VCO period.Due to the phase jitter of frequency divider, it is possible to
SYSREF counter stops counting between the high period of pulse, and then generates freak pulses.So in impulse generator mode
Under, it jumps and mutually enables to be set to 0.
The biasing of high performance mode adjustable frequency divider and buffer improves the amplitude of oscillation and phase noise of output signal,
But to sacrifice power consumption as cost.In the design process, equipment clock is higher to the amplitude of oscillation of signal and performance requirement of mutually making an uproar, and
SYSREF pulse is then not necessarily to require.
SYNC can allow for channel to respond synchronization request event, the request may come from SPI order or
Person's SYNC reset signal.If channel needs accurate phase alignment, the position 1.
Dynamic driver makes can to make the enabled and frequency divider of output buffer enabled controlled together, allow channel not by
To pulse generation influence and dynamic power down.During the experiment, which should be set to 0, otherwise due to the shadow of dynamic power down
It rings, output level can generate step.
Force mute if on, then other than impulse generator link, the output of buffer is logical zero.It forces mute
If closed, other than impulse generator link, the output of buffer is to be worth near common-mode voltage.
CLKIN0 is the reference clock of phaselocked loop input in the present embodiment, not as SYNC input channel.The port SYNC mould
Formula (SYNC Pin MODE) is generated, corresponding selection according to the needs of pulse generation by external signal or internal register configuration
SYNC Pulse mode.
According to the mechanism that pulse generates, SYSREF counter set point (SYSREF Timer) and frequency division coefficient
(DIVIDER), the umber of pulse of pulse mode (Pulsor Mode) setting should meet following relationship:
P=(m+1) × n-1
In formula: p is the practical pulse number generated of impulse generator, and m is the pulse number of Pulsor MODE setting, and n is
The ratio of SYSREF Timer/DIVIDER, SYSREF Timer are counter, and DIVIDER is the frequency division value in channel.
Pulse setting parameter is unsatisfactory for the requirement of formula, can generate freak pulses or can not generate pulse.The global configuration of output channel
As shown in Figure 8.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (3)
1. a kind of more ADC synchronizing devices based on locking phase delay characterized by comprising FPGA, clock generator, pulse hair
Raw device and multi-disc ADC；
The FPGA is used to generate clock sync signal SYNC and SPI control command, then clock sync signal SYNC is sent
To clock generator, SPI control command is sent to clock generator and impulse generator simultaneously；
The clock generator first carries out initial configuration under SPI control command, and successively to first order phaselocked loop and
Second level phaselocked loop is locked；Then under the excitation of clock sync signal, it is aligned the phase of internal frequency divider, produces multi-disc
The sampled clock signal of ADC, and be distributed to per a piece of ADC；Meanwhile clock generator generates reference clock signal and all the way all the way
Pulse synchronous signal is simultaneously sent to impulse generator, wherein reference clock believes the source clock as impulse generator, impulsive synchronization
Signal synchronizes reset to impulse generator；
The impulse generator first carries out initial configuration under SPI control command, and successively to first order phaselocked loop and
Second level phaselocked loop is locked；Then under the excitation of pulse synchronous signal, make output end holding and the clock of impulse generator
The phase alignment of generator is aligned, and then, impulse generator carries out multichannel driving to the source clock of input, produces multipath delay
Adjustable synchronization pulse, and be distributed to per a piece of ADC；
The ADC carries out reset operation according to synchronization pulse, then carries out signal when sampled clock signal arrives and adopts
Sample.
2. more ADC synchronizing devices according to claim 1 based on locking phase delay characterized by comprising the clock
Generator and impulse generator use the connection type of clock tree construction using the phase-locked loop structures of double cascade connection types between the two；
The phase-locked loop structures of double cascade connection types include first order phaselocked loop and second level phaselocked loop, and every level-one phaselocked loop is by electricity
Lotus pump-type phase-locked loop structures；Wherein, crystal oscillator is as reference source with high precision for first order phaselocked loop, when first order phase lock loop locks
Accurate, low noise a reference clock is provided to second level phaselocked loop, second level phaselocked loop is using an internal voltage controlled oscillation
Device realizes clock multiplier, generates and distribute a plurality of types of clock sources when the phase lock loop locks of the second level；
The clock tree construction, using clock generator as master clock chip, using impulse generator as branch's chip；It is main
Clock chip is using external crystal-controlled oscillation as reference source, input of the clock as rear class impulse generator of output high-precision, Low phase noise
Clock；In every level-one of Clock Tree, the clock chip of prime provides pulse synchronous signal and carries out phase to branch's chip of rear class
Alignment, so that realizing more accurate synchronization between each output.
3. more ADC synchronizing devices according to claim 1 based on locking phase delay characterized by comprising the ADC
Reset operation, the output that pulse is adjusted using analogue delay and digital related method thereof postponed；
Wherein, the analogue delay minimal adjustment stepping is ADly=25ps, and number of steps is up to AStep=23；The number
Delay minimal adjustment stepping is DDly=200ps, and number of steps is up to DStep=17；When retardation is greater than the tune of T=1/2VCO
Section is less than retardation the adjusting of T=1/2VCO, the method for sampling analogue delay using the method for digital delay.
Specific implementation steps are as follows:
(1), initialization delay value is sent；
(2), analogue delay amount is incrementally increased, ADC output data can successively undergo stable, unstable state；
(3), according to unstable twice central value AStep1, AStep2, the retardation AStep0=for stablizing reset is calculated
(AStep1+AStep2)/2；
(4), setting analogue delay amount is AStep0, realizes that stablizing for monolithic ADC resets；
(5), when more ADC reset at different sections, digital delay amount DStep=DStep+2, i.e. pulse daley one are adjusted
Sampling clock cycle, so that synchronization signal resets at next stable period；
(6), on the basis of monolithic ADC stablizes, (5) item successively is repeated to multi-disc ADC, finally realizes that stablizing for more ADC resets.
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| CN111240401A (en) * | 2020-03-13 | 2020-06-05 | 杭州电子科技大学 | Multi-channel clock generating device |
| CN111262578A (en) * | 2020-04-26 | 2020-06-09 | 杭州城芯科技有限公司 | Multi-chip synchronization circuit, system and method for high-speed AD/DA (analog-to-digital/digital) chip |
| CN112187262A (en) * | 2020-06-16 | 2021-01-05 | 中国人民解放军战略支援部队航天工程大学 | Synchronous acquisition time delay control method for DBBC (database based block code) |
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