CN111240401A - Multi-channel clock generating device - Google Patents
Multi-channel clock generating device Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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Abstract
The invention discloses a multi-channel clock generating device which at least comprises a configuration unit, a high-frequency clock generator, a synchronous clock generator and a multi-channel output unit, wherein the configuration unit is connected with the high-frequency clock generator and the synchronous clock generator and is used for receiving a configuration instruction to configure the operating parameters and the working mode of the clock generating device; the high-frequency clock generator is used for generating a high-frequency clock; the synchronous clock generator is used for generating a synchronous clock according to the high-frequency clock output by the high-frequency clock generator as a frequency multiplication source; the multi-channel output unit is used for carrying out channel expansion on the high-frequency clock and the synchronous clock and then outputting the high-frequency clock and the synchronous clock to the target equipment; the high-frequency clock generator adopts an ADF4355 chip, and the synchronous clock generator adopts an LTC6952 chip. The invention designs 4 paths of highest 6.8GHz frequency output by adopting a mode of combining an ADF4355 chip and a high-frequency power divider, thereby simplifying the shunt design.
Description
Technical Field
The invention relates to the field of signal processing, in particular to a clock generating device applied to synchronous output of a JESD interface.
Background
The JESD interface has become the main data input/output interface of high-speed devices, such as AD, DA, etc. chips, and because the single-channel output adopts a differential form, the data speed of up to 12.8Gb/s can be realized under the condition of only 2 lines. However, the clock input synchronization requires a very high timing sequence, and the present invention mainly discloses a multi-channel synchronous clock output device and method for the system.
Usually, the JESD single-channel device needs at least two clock signals, one high-frequency clock signal is used for clock supply of chip cores and other modules, and the other low-frequency synchronous clock is mainly used for providing synchronous signals for JESD data transmission. At present, the common design of the JESD synchronous clock is only limited by the requirement of single-channel equipment, the output main frequency is not high, the synchronous clock can only be output to equipment connected with the main frequency, and the synchronous signal can not be transmitted to a main control center or other equipment.
Therefore, it is necessary to provide a technical solution to solve the technical problems of the prior art.
Disclosure of Invention
In view of the above, it is necessary to provide a synchronous clock output device with multiple outputs, a main frequency up to 6.8GHz, and a precise delay function.
In order to solve the technical problems in the prior art, the technical scheme of the invention is as follows:
multichannel clock generation device, characterized in that the clock generation device comprises at least a configuration unit, a high frequency clock generator, a synchronous clock generator and a multichannel output unit, wherein,
the configuration unit is connected with the high-frequency clock generator and the synchronous clock generator and is used for receiving a configuration instruction to configure the operation parameters and the working mode of the clock generation device;
the high-frequency clock generator is connected with the high-frequency crystal oscillator and the synchronous clock generator and is used for generating a high-frequency clock;
the synchronous clock generator is connected with the high-frequency crystal oscillator, the low-frequency crystal oscillator and the high-frequency clock generator and used for generating a synchronous clock according to a high-frequency clock output by the high-frequency clock generator as a frequency multiplication source;
the multi-channel output unit is used for performing channel expansion on the high-frequency clock and the synchronous clock and outputting the high-frequency clock and the synchronous clock to target equipment;
the high-frequency clock generator adopts an ADF4355 chip, and the synchronous clock generator adopts an LTC6952 chip.
As a further improvement, the multi-channel output unit at least comprises a plurality of baluns, a high-frequency power divider and a power dividing circuit, wherein the high-frequency power divider is used for channel expansion of a high-frequency clock; the power dividing circuit is used for channel expansion of a low-frequency clock.
As a further improvement, the clock generation device is configured at least in a high-precision operation mode or in a normal operation mode.
As a further improvement, the clock generating device further comprises a switching circuit, wherein the switching circuit is used for switching on the low-frequency crystal oscillator of the crystal oscillator group or the 8 th channel output clock of the LTC6952 chip according to the input REF clock of the ADF4355 chip; when the clock generating device is configured to be in a high-precision working mode, the LTC6952 chip uses a high-frequency crystal oscillator and monopolizes a low-frequency crystal oscillator, and the switching circuit switches on a REF input of the ADF4355 chip and an output clock of an 8 th channel of the LTC6952 chip; when the clock generation device is configured to be in a normal operation mode, the switching circuit controls the input REF clock of the ADF4355 chip to selectively switch on the low-frequency crystal oscillator.
As a further improvement scheme, the clock generation device further comprises an MCU, and the configuration unit is integrated in the MCU.
As a further improvement scheme, the configuration instruction is generated in the upper computer and transmitted to the configuration unit.
As a further improvement, the balun comprises NCS2-83X, ADT2-1T, TCM2-43X chips.
As a further improvement scheme, the high-frequency power divider comprises a PD4859J5050S2HF chip and a PD3150J5050S2HF chip; the power dividing circuit is a PCB direct design type double semi-circle circuit structure.
As a further improvement scheme, the switching circuit is a single-pole double-throw relay switch.
As a further improvement, the frequency of the low-frequency crystal oscillator is 100M; the frequency of the high-frequency crystal oscillator is 2500M.
Compared with the prior art, the invention has the following technical effects:
1. aiming at the fact that few chips capable of outputting high frequency in the market are available at present, the design of the multi-channel clock generating device with accurate time delay is achieved by combining an ADF4355 chip and an LTC6952 chip.
2. The invention designs 4 paths of highest 6.8GHz frequency output by adopting a mode of combining an ADF4355 chip and a high-frequency power divider, thereby simplifying the shunt design.
3. Aiming at the situation that no frequency doubling source exists in the LTC6952 chip, one path of high-frequency output signal of the ADF4355 chip is subjected to frequency halving and then is sent to the clock input of the LTC6952 chip, and therefore design is simplified.
4. Meanwhile, when the ADF4355 internal frequency doubling source is doubled from a low-frequency clock to a high frequency, a large signal frequency offset or phase shift is generated, and the requirement of a high-precision clock cannot be met.
5. The invention adopts the modes of upper computer human-computer interface input, USB data communication and system preset chip configuration program, and realizes simpler configuration process and fault check.
6. When strict requirements such as high precision, low phase difference, low frequency deviation and the like exist on the frequency of an output clock, the shielding high-frequency crystal oscillator or the use of the high-frequency crystal oscillator can be selected according to the frequency requirement of the output when the MCU configuration program is preset. If a high-frequency crystal oscillator is used, channels with the highest 3.4GHz can be output, the maximum channel can only output 2.5GHz, and high-quality signal output of ps level can be obtained.
Drawings
FIG. 1 is a schematic block diagram of a multi-channel clock generation apparatus of the present invention;
FIG. 2 is a block diagram of an implementation of a preferred embodiment of the multi-channel clock generation apparatus of the present invention;
FIG. 3 is a schematic circuit diagram of a preferred embodiment of the multi-channel clock generation apparatus of the present invention;
fig. 4 is a block diagram of a crystal group for providing clock detail for the ADF4355 and LTC6952 according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a 1-path differential signal to 4-path single-end output connection according to an embodiment of the present invention.
The following specific embodiments will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.
Referring to fig. 1, there is shown a schematic block diagram of a multi-channel clock generation apparatus of the present invention, the clock generation apparatus at least comprises a configuration unit, a high frequency clock generator, a synchronous clock generator and a multi-channel output unit, wherein,
the configuration unit is connected with the high-frequency clock generator and the synchronous clock generator and used for receiving a configuration instruction to configure the operation parameters and the working mode of the clock generation device;
the high-frequency clock generator is connected with the high-frequency crystal oscillator and the synchronous clock generator and is used for generating a high-frequency clock;
the synchronous clock generator is connected with the high-frequency crystal oscillator, the low-frequency crystal oscillator and the high-frequency clock generator and used for generating a synchronous clock according to a high-frequency clock output by the high-frequency clock generator as a frequency multiplication source;
the multi-channel output unit is used for performing channel expansion on the high-frequency clock and the synchronous clock and outputting the high-frequency clock and the synchronous clock to target equipment;
the high-frequency clock generator adopts an ADF4355 chip, and the synchronous clock generator adopts an LTC6952 chip.
In the above technical solution, the multi-channel output unit at least includes a plurality of baluns, a high-frequency power divider and a power dividing circuit, and the high-frequency power divider is used for channel expansion of a high-frequency clock; the power dividing circuit is used for channel expansion of a low-frequency clock.
In the above technical solution, the clock generation apparatus further includes an MCU, and the configuration unit is integrally disposed in the MCU.
Referring to fig. 2-5, circuit design diagrams of a preferred embodiment of the multichannel clock generating device according to the present invention are shown, which include an ADF4355 chip, an LTC6952 chip, a low-frequency crystal oscillator, a high-frequency crystal oscillator, a balun, a high-frequency power divider, a frequency-halving device, a power dividing circuit, a switching circuit, an MCU, a USB controller, a USB interface, and an SMA interface. The LTC6952 chip is connected with the MCU, the high-frequency crystal oscillator, the balun, the switching circuit, the frequency divider and the synchronous clock generator respectively; the MCU is also connected with the USB controller and the synchronous clock generator; the USB controller is connected with the USB interface; the switching circuit is connected with the low-frequency crystal oscillator and the synchronous clock generator; the low-frequency crystal oscillator is also connected with a synchronous clock generator; the frequency halving device is also connected with the synchronous clock generator; the high-frequency crystal oscillator is also connected with a synchronous clock generator; the synchronous clock generator is also connected with a balun interface and an SMA interface; the balun is also connected with the power dividing circuit and the high-frequency power divider; the power dividing circuit is also connected with the SMA interface; the high-frequency power divider is also connected with the SMA interface.
As a further improvement scheme, the MCU comprises a 430G2553 chip, the USB controller comprises a CH340T chip, the frequency of the low-frequency crystal oscillator is 100M, the frequency of the high-frequency crystal oscillator is 2500M, the balun comprises an NCS2-83X, ADT2-1T, TCM2-43X chip, the frequency divider comprises an HMC361 chip, the high-frequency power divider comprises a PD4859J5050S2HF chip and a PD3150J5050S2HF chip, the switching circuit is a single-pole double-throw relay switch, and the power dividing circuit is a double-semicircular-ring circuit structure directly designed for a PCB.
In the technical scheme, aiming at the fact that the number of chips capable of outputting high frequency in the market at present is small, the ADF4355 chip capable of outputting 6.8GHz dual-channel output is used, and because the number of output channels is small, the 4-channel maximum 6.8GHz frequency output is designed in a mode of combining the ADF4355 chip with the high-frequency power divider. Meanwhile, considering that an application system generally needs a low-frequency synchronous clock signal, the LTC6952 chip combination mode design for outputting 11 paths of synchronous clock signals to the maximum is selected and designed. Because there is no frequency doubling source inside the LTC6952 chip, one of the high frequency output signals of the ADF4355 chip is divided by two and then sent to the clock input of the LTC6952 chip, thereby simplifying the circuit design.
Further, the clock generation device is configured at least in a high-precision operation mode or a normal operation mode. The method mainly considers that when an ADF4355 internal frequency doubling source is doubled from a low-frequency clock to a high-frequency clock, a large signal frequency offset or phase shift is generated, and the requirement of a high-precision clock cannot be met, so that a 2500MHz high-frequency crystal oscillator is selected as an alternative input clock of an LTC6952 chip. Considering that both the low frequency crystal oscillator and the high frequency crystal oscillator can only provide frequency for the LTC6952 chip in the high precision operation mode, the 1 channel output of the LTC6952 is designed as the clock input of the ADF4355 and is controlled by the relay switch.
In addition, the clock scene of the communication system is satisfied by combination, and generally, an AD input clock only needs half of a DA clock, so that 4 paths of clock output with the highest frequency of 3.4GHz are designed by matching 2 paths in an LTC6952 output path with a high-frequency balun and a high-frequency power divider, and the 4 paths of output can be divided into 2 groups for delay adjustment. And considering the multi-plate cascade synchronous output, the LTC6952 reserves 1 channel to be directly output as a differential signal. The remaining 7 channels of the LTC6952 all adopt a low-frequency balun and a power dividing circuit to realize 14 paths of synchronous clock output with the maximum frequency of 450MHz, and the 14 paths can also be divided into 7 groups for delay adjustment. Therefore, the single board can output 11 signals with different frequencies and different phases, and output 24 single-channel LVDS or COMS signals and 1 double-channel differential signals. The 4 paths of the differential channels can output differential signals with the highest frequency of 3.4GHz, the 6 paths of the differential channels can output differential signals with the highest frequency of 3.4GHz, and the 14 paths of the differential channels can output synchronous signals with the highest frequency of 450MHz in a fixed delay configuration. The 4-path single channel capable of outputting the highest 3.4GHz signal can be divided into two groups, so that the signal output with phase difference is realized.
Further, a configuration instruction is generated in the upper computer and transmitted to the configuration unit. Because the number of chip registers is large, each register needs to be configured independently through the SPI, and the complexity is high. The system configuration process comprises the following steps: and parameters are input on an interface of the upper computer, the upper computer software automatically performs code conversion, a configuration signal frame is formed at the same time, and configuration information is transmitted to the clock generation hardware part through the USB cable and the interface. The clock generation hardware part acquires a signal frame transmitted by the upper computer, analyzes a command, performs hardware configuration work according to a set program and realizes clock signal output. When the system has a fault, the hardware board can carry out time delay self-checking and simultaneously send a fault code to the upper computer. And the upper computer analyzes possible faults according to the fault codes and displays the faults through an interface.
The upper computer part mainly realizes the input of user data, code conversion, the acquisition and analysis of data frames forming communication and fault codes, and displays the data frames and the fault codes through a human-computer interface. When the system output needs to change the frequency or the system has faults, an upper computer needs to be used for carrying out relevant operations. The upper computer software has the functions of parameter conversion, data generation, communication framing, interface display, fault diagnosis and the like, is relatively simple to use, can be automatically converted into a code format recognized by hardware by inputting required clock frequency, phase, time delay and the like in the interface to form a transmitted frame structure, and can realize signal output through the clock generation hardware part by configuring keys through one key. When the clock generation hardware part has faults, signals are not accurately output, after one-key configuration signals sent by the upper computer are received, error codes can be directly sent to the upper computer, and the upper computer analyzes the error codes and displays the faults possibly occurring through an interface. If the power supply is not connected and the like, the upper computer interface directly prompts a clock hardware system to start the power supply and other notifications after the button is configured by pressing one key.
In actual configuration, the output frequency is used or changed for the first time, and data configuration needs to be performed by using upper computer software, and the main process is as follows: firstly, software of an upper computer is opened, and a USB cable is connected. And (3) switching on a power supply of a hardware part of the clock, displaying the installation of a driver by an upper computer, selecting a proper port on a software interface after the installation is successful, and prompting that the system is correctly connected by the interface after the configuration is correct. And then, setting related parameters such as frequency, phase, time delay and the like on an interface of the upper computer, clicking a one-key configuration button after the setting is finished, and transmitting information to be configured to an MCU chip of a clock hardware part by the USB cable through a USB component.
And after receiving the configuration information, the MCU chip starts to configure the hardware system to work according to a preset time sequence.
By adopting the technical scheme of the invention, the high-precision working mode or the common working mode can be configured according to application requirements, so that the method comprises the two ways of setting the use or shielding of the high-frequency crystal oscillator, when the clock generation device is configured to be the high-precision working mode, the LTC6952 exclusively uses the low-frequency crystal oscillator and simultaneously supplies the 8 th channel output clock to the ADF4355 as the REF input clock thereof. The specific hardware configuration procedure is different in the two modes. The method comprises the following specific steps:
1) the ordinary operation mode setting process is as follows:
the method comprises the following steps: the MCU controls a relay switch of the switching circuit to enable the low-frequency 100MHz crystal oscillator to output to the ADF4355, and simultaneously, a high-frequency 2500MHz crystal oscillator power supply is cut off;
step two: the MCU configures the ADF4355 through the SPI, and after the stable working state of the ADF4355 is obtained, the next step is carried out;
step three: the MCU configures the LTC6952 through the SPI, and after the stable working state of the LTC6952 is obtained, a configuration completion instruction is replied to the upper computer;
step four: and if the external trigger state exists, outputting the synchronous signal under the trigger synchronous instruction.
2) The high-precision working mode setting process is as follows:
the method comprises the following steps: the MCU firstly configures a low-frequency 100MHz clock through a relay switch of a switching circuit, disconnects the low-frequency 100MHz clock from the ADF4355 (the state at this time is that a No. 8 output channel of the LTC6952 is connected with a clock input REF port of the ADF 4355), then configures a high-frequency 2500MHz clock to work, and carries out the next step after certain time delay;
step two: the MCU configures the LTC6952 through the SPI, so that a No. 8 channel outputs 100MHz frequency, other channels configure information such as frequency, phase, time delay and the like according to requirements, and after the stable working state of the LTC6952 is obtained, the next step is carried out;
step three: the MCU configures the ADF4355 through the SPI, and returns a configuration completion instruction to the upper computer after acquiring the stable working state of the ADF 4355;
step four: and if the external trigger state exists, outputting the synchronous signal under the trigger synchronous instruction.
When a clock generation hardware part has a fault, a hardware system can carry out self-checking, and the method mainly comprises the following steps: after the two chips are configured by the SPI, the MCU can carry out delay waiting for about 3000ms, and if a stable working state replied by the configuration chip is received in the period, the MCU stops waiting. When the two chips both send out a stable working state, the configuration is completed by the upper computer. If the stable working state is not received within 3000ms, a command for reading the chip state register is sent after the time elapses, and the fault code is sent to the upper computer through the USB after the chip fault code is obtained.
Referring to fig. 4, the crystal oscillator group provides a detailed connection diagram of different input clock configurations for the main chip. The crystal oscillator group mainly comprises 100MHz and 2500MHz crystal oscillators, wherein 100MHz is connected to a REF input port of the LTC6952 and an A port of the single-pole double-throw relay switch, and the 2500MHz crystal oscillator is directly connected to a VCO port of the LTC 6952. The magnetic control port of the single-pole double-throw relay switch is directly connected to the I/O port of the MCU. The C port of the single-pole double-throw relay switch is connected to the REF port of the ADF4355, and the B port is connected to the out8 output port of the LTC 6952. The HMC361 is a frequency divider with a signal input terminal connected to the a output port of the ADF4355 and a signal output terminal connected to the VCO port of the LTC6952, and a VCC port connected to the collector of the transistor Q1. The VCC port of the 2500MHz crystal oscillator is connected to the collector of the transistor Q2. The emitters of the transistors Q1 and Q2 are connected to a VCC power supply, and the bases are respectively sent to different I/O ports of the MCU. The design structure can realize two clock frequency supply methods, the use condition of the high-frequency crystal oscillator of 2500MHz can be divided into the clock supply of a shielding high-frequency crystal oscillator and the clock supply of a using high-frequency crystal oscillator, and different gain effects can be obtained under different use environments. Under the condition of small temperature drift of the high-frequency crystal oscillator, the high-frequency crystal oscillator can be used for obtaining high-quality clock signals with extremely small time delay, phase shift, frequency offset and the like. The detailed configuration method has been specifically described above. The illustration of MCUI/O1-3 means three different input/output interfaces connected to the MCU.
Fig. 5 is a schematic diagram of connection of 1-path differential signal to 4-path single-end signal output. Since the signal outputs of the ADF4355 and the LTC6952 are both differential signals, the connection of 1-path differential signal to 4-path single-ended signal is drawn in this figure by taking the ADF4355 as an example, and the LTC6955 outputs 2 or 4 paths similarly. The B output interface of ADF4355 is connected to pins No. 1 and No. 2 of balun NCS2-83+, respectively. Pins No. 4 and No. 5 of the balun NCS2-83+ are connected to a common ground, a Pin No. 6 is connected to a Pin2 of a PD4859J5050S2HF, pins 4 and 6 of the PD4859J5050S2HF are respectively connected to a Pin2 of the next two PD4859J5050S2HF chips, and pins 4 and 6 of the second two PD4859J5050S2HF are sent to an SMA interface to form 4-path single-end output. When the signal is output from the port B of the ADF4355, the signal is a differential signal, the differential signal is converted into a single-ended signal after passing through the balun, the single-ended signal is expanded to 2 paths of output through the first-stage power division chip, and the 2 paths of output are expanded to 4 paths of output through the second-stage common division chip. The process of outputting 2 paths or 4 paths by the LTC6952 is basically similar to that of the LTC6952, wherein the balun connection scheme is basically the same, the scheme of outputting 2 paths is expanded only by adopting a mode of one-stage power divider or power dividing circuit, and the scheme of outputting 4 paths is the same as that of fig. 4.
The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. Multichannel clock generation device, characterized in that the clock generation device comprises at least a configuration unit, a high frequency clock generator, a synchronous clock generator and a multichannel output unit, wherein,
the configuration unit is connected with the high-frequency clock generator and the synchronous clock generator and is used for receiving a configuration instruction to configure the operation parameters and the working mode of the clock generation device;
the high-frequency clock generator is connected with the high-frequency crystal oscillator and the synchronous clock generator and is used for generating a high-frequency clock;
the synchronous clock generator is connected with the high-frequency crystal oscillator, the low-frequency crystal oscillator and the high-frequency clock generator and used for generating a synchronous clock according to a high-frequency clock output by the high-frequency clock generator as a frequency multiplication source;
the multi-channel output unit is used for performing channel expansion on the high-frequency clock and the synchronous clock and outputting the high-frequency clock and the synchronous clock to target equipment;
the high-frequency clock generator adopts an ADF4355 chip, and the synchronous clock generator adopts an LTC6952 chip.
2. The multi-channel clock generation device of claim 1, wherein the multi-channel output unit comprises at least a plurality of baluns, a high-frequency power divider and a power dividing circuit, and the high-frequency power divider is used for channel expansion of a high-frequency clock; the power dividing circuit is used for channel expansion of a low-frequency clock.
3. The multi-channel clock generation apparatus of claim 1 or 2, wherein the clock generation apparatus is configured at least in a high-precision mode of operation or in a normal mode of operation.
4. The multi-channel clock generating device of claim 3, further comprising a switching circuit for switching the input REF clock of the ADF4355 chip to select whether to turn on the low frequency crystal oscillator of the crystal oscillator group or the output clock of the 8 th channel of the LTC6952 chip according to a control instruction; when the clock generating device is configured to be in a high-precision working mode, the LTC6952 chip uses a high-frequency crystal oscillator and monopolizes a low-frequency crystal oscillator, and the switching circuit switches on a REF input of the ADF4355 chip and an output clock of an 8 th channel of the LTC6952 chip; when the clock generation device is configured to be in a normal operation mode, the switching circuit controls the input REF clock of the ADF4355 chip to selectively switch on the low-frequency crystal oscillator.
5. The multi-channel clock generation device of claim 1 or 2, wherein the clock generation device further comprises an MCU, and the configuration unit is integrally arranged in the MCU.
6. The multi-channel clock generation apparatus of claim 1 or 2, wherein the configuration instructions are generated in an upper computer and transmitted to a configuration unit.
7. The multi-channel clock generation apparatus of claim 2, wherein the balun includes NCS2-83X, ADT2-1T, TCM2-43X chips.
8. The multi-channel clock generation apparatus of claim 2, wherein the high frequency power divider comprises a PD4859J5050S2HF, PD3150J5050S2HF chip; the power dividing circuit is a PCB direct design type double semi-circle circuit structure.
9. The multi-channel clock generation apparatus of claim 4, wherein the switching circuit is a single-pole double-throw relay switch.
10. The multi-channel clock generation apparatus according to claim 1 or 2, wherein the frequency of the low-frequency crystal oscillator is 100M; the frequency of the high-frequency crystal oscillator is 2500M.
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| CN114461008A (en) * | 2021-12-21 | 2022-05-10 | 天津光电通信技术有限公司 | Method for realizing multi-path adjustable homologous clock |
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