CN106982098B

CN106982098B - Wireless communication signal high-performance test module and test method thereof

Info

Publication number: CN106982098B
Application number: CN201710236444.9A
Authority: CN
Inventors: 熊志坚; 刘新宇; 刘亚洲
Original assignee: SUZHOU CAS IC DESIGN CENTER
Current assignee: SUZHOU CAS IC DESIGN CENTER
Priority date: 2017-04-12
Filing date: 2017-04-12
Publication date: 2023-06-30
Anticipated expiration: 2037-04-12
Also published as: CN106982098A

Abstract

The invention discloses a wireless communication signal high-performance test module and a test method thereof, wherein the test module is provided with a reference clock, and the accurate synchronization time of an initialization unit and a chip AD9361 is provided; the initialization unit configures the chip AD9361 to operate in a transceiving state, and sets an auxdc_control mode, a port_control port mode, a ctrl_outer_control control mode, a gain mode of gain_control, a rsi_control test mode, an elna_control external gain mode, a tx_monitor_control input power control mode, and an auxiliary auxdc_control control mode, and the chip AD9361 processes signals of each antenna receiving port into a data stream of zero intermediate frequency and outputs the data stream to the field programmable gate array for digital processing. By applying the test system scheme of the invention, the radio frequency transceiving of 12-bit analog-to-digital and digital-to-analog conversion is supported, the transmitting frequency band is from 47MHz to 6GHz, and the receiving frequency band is from 70MHz to 6GHz, so that the test sensitivity, noise response and comprehensive precision are improved. And has the capability of multi-chip synchronization, supporting CMOS/LVDS digital interfaces.

Description

Wireless communication signal high-performance test module and test method thereof

Technical Field

The invention relates to the field of wireless communication, in particular to a novel module capable of realizing multichannel high-performance radio frequency and intermediate frequency test processing and a test method thereof.

Background

With the development of wireless communication, various wireless communication modules have been developed; generally, before a wireless communication module is put on the market, electrical performance test and functional test, and initialization configuration are required to be performed on the wireless communication module. If the wireless communication module is directly welded to equipment for use without test, once the module has a problem, the equipment is caused to fail, so that the reject ratio of products is greatly increased, and meanwhile, great difficulty is brought to maintenance and production; in addition, as the factory settings of the wireless communication modules of different factories are different, the main control equipment is compatible with the initialization configuration of the wireless communication modules of different factories, thereby greatly reducing the resource utilization rate of the main control equipment and bringing a certain difficulty to development. Therefore, the wireless communication testing device plays a vital role in the normal application of the wireless communication module.

However, with the continuous improvement of the design level of the chip to be tested, the existing wireless communication module has stronger functions, and the number and form of interfaces break through the original limitation to become diversified. Therefore, higher performance and integration requirements are also put forward for the test equipment of the wireless communication signals.

Disclosure of Invention

Aiming at the embarrassment of the prior art, the invention provides a wireless communication signal high-performance test module and a test method thereof, so as to provide a test solution with higher performance, low energy consumption and duty cycle.

The first object of the present invention is achieved by the following technical solutions: the wireless communication signal high-performance test module is oriented to the participation of a chip to be tested and a field programmable gate array to form a full-frequency-band radio frequency test platform, and is characterized in that: the test module is provided with a chip AD9361 and an LNA, an active mixer, an amplifier, a DAC and an ADC which are integrated with the chip AD9361, wherein the chip AD9361 is connected with two paths of independent antenna receiving ports through the LNA, two paths of independent antenna emitting ports are connected with the amplifier, and the chip AD9361 is interconnected with a programmable gate array in a bidirectional signal manner.

Further, the chip AD9361 is connected with a reference clock and an initialization unit for configuring the chip to work in a receiving and transmitting state and in a plurality of working modes, and the reference clock is connected with the initialization unit in an associated mode.

Further, the chip AD9361 is equipped with a control unit in the form of information input, output data.

Further, the chip AD9361 is equipped with an interface function unit for fast locking a given frequency and power consumption.

Further, the chip AD9361 further integrates an RF front-end device comprising at least an IQ modulator and a radio frequency phase locked loop.

Further, the amplifier is a power amplifier driving amplifier.

The second object of the present invention is achieved by the following technical solutions: the high-performance test method of the wireless communication signal is realized based on a test platform formed by a test module and a field programmable gate array, wherein the test module is provided with a chip AD9361 and an LNA, an active mixer, an amplifier, a DAC and an ADC which are integrated with the chip AD9361, wherein the chip AD9361 is connected with two independent antenna receiving ports through the LNA, and is connected with two independent antenna transmitting ports through the amplifier; moreover, the chip AD9361 is connected with an initialization unit, a reference clock, a control unit, an interface function unit for rapidly locking the set frequency and the power consumption and RF front-end equipment, and is characterized in that: the test method comprises the steps of configuring a reference clock for a test module, and providing accurate synchronization time of an initialization unit and a chip AD 9361; the initialization unit configures the chip AD9361 to operate in a transceiving state, and sets an auxdc_control mode, a port_control port mode, a ctrl_outer_control control mode, a gain mode of gain_control, a rsi_control test mode, an elna_control external gain mode, a tx_monitor_control input power control mode, and an auxiliary auxdc_control control mode, and the chip AD9361 processes signals of each antenna receiving port into a data stream of zero intermediate frequency and outputs the data stream to the field programmable gate array for digital processing.

Further, the control module is used for controlling the signal input and the signal output to be in different data forms.

By applying the technical scheme related to the test platform, the remarkable technical effects are as follows: the test module supports the radio frequency transceiving of 12-bit analog-to-digital and digital-to-analog conversion, the transmitting frequency band is from 47MHz to 6GHz, the receiving frequency band is from 70MHz to 6GHz, and the test sensitivity, noise response and comprehensive precision are improved. And has the capability of multi-chip synchronization, supporting CMOS/LVDS digital interfaces.

Drawings

FIG. 1 is a block diagram of an application system architecture of a test module according to the present invention.

FIG. 2 is a schematic diagram of an interface circuit between a test module and a field programmable gate array according to the present invention.

FIG. 3 is a flow chart of the test software of the present invention.

Detailed Description

Aiming at the test requirement of the chip or the board of the existing communication platform, the invention innovatively provides a high-performance test module for wireless communication signals, which can be used for reliably testing various currently mainstream and newly designed wireless communication systems.

As shown in fig. 1 and fig. 2, the wireless communication signal high-performance testing module is oriented to the chip to be tested and the field programmable gate array to participate in forming a full-band radio frequency testing platform when in application and implementation. From the illustration, the programmable full-band radio frequency platform adopts a single-chip transducer solution, and the RF chip adopts the latest AD936X series of ADI (the proposal takes AD9361 as the dominant one). The series of chips integrate LNA, active Mixer, power amplifier driving amplifier, ADC and DAC, two independent antenna receiving ports are connected through LNA, two independent antenna transmitting ports are connected through amplifier, and a single chip can complete radio frequency and intermediate frequency processing of 1T1R or 2T2R channels, and provides zero intermediate frequency data flow for FPGA to do digital signal processing. RF1-OUT, RF2-OUT, RF1-IN, RF2-IN and their left-hand associated series of digital circuit devices as shown IN the figures are important bases upon which the test module is designed to perform its functions.

As can be seen from the illustration, the chip AD9361 is coupled with an initialization unit configured to operate in a transceiving state and in a plurality of modes, and can control various port modes, control, gain, test modes, and the like required by the chip. The chip AD9361 is connected with a reference clock in an matching mode, and the reference clock is connected with an initialization unit in an associated mode to provide accurate clocks for the reference clock and the initialization unit. In addition, the chip AD9361 is also connected with a control unit in the form of information input and output data, an interface function unit for rapidly locking the set frequency and power consumption, and RF front-end equipment at least comprising an IQ modulator, a radio frequency phase-locked loop and the like.

The FPGA on the left side of fig. 2 adopts the latest Zynq series FPGA (including dual-core ARM processor and high-capacity FPGA logic resource) of Xilinx corporation to cover the system-level wireless communication solution of the radio frequency circuit, and has the functions of completing radio frequency signal receiving and transmitting, baseband signal processing and protocol stack analysis on a single board, so that a single board communication system solution can be provided. A single board card is used to realize a complete communication system.

As shown in the flow chart of the test software in fig. 3, the test method includes configuring a reference clock for a test module, and providing accurate synchronization time between an initialization unit and a chip AD 9361; the initialization unit configures the chip AD9361 to operate in a transceiving state, and sets an auxdc_control mode, a port_control port mode, a ctrl_outer_control control mode, a gain mode of gain_control, a rsi_control test mode, an elna_control external gain mode, a tx_monitor_control input power control mode, and an auxiliary auxdc_control control mode, and the chip AD9361 processes signals of each antenna receiving port into a data stream of zero intermediate frequency and outputs the data stream to the field programmable gate array for digital processing.

Also, as can be seen from the illustration, the clk signal is a clock that has an external crystal oscillator providing clk_onecell_data with a data clock providing ad9361_rf_phy with a modulation signal. The ad9361_fasklock_entry is an interface function module that controls fast lock-out of a given frequency and power consumption to the module ad9361_fastlock of the chip ad 9361. rx_gain_info is a power test interface function module that tests the input chip signal. The attached chip information module axiadd_chip_info is the intrinsic information of the module that reads axiadd_controller. The internal information is implemented by the encapsulated data structure of the ad9361 rf phy. The module of axiadd_state is to control whether the information input and output are in different data forms, such as single ended input or differential input. Under the regulation and control of a reference clock and a data clock provided by an external crystal oscillator, each device orderly performs signal conversion and transmission according to the arrow in the figure, and high-precision and low-loss testing is realized.

In summary, the technical scheme of the test module has obvious technical effects: the test module supports radio frequency transceiving of 12-bit analog-to-digital conversion and digital-to-analog conversion, the transmitting frequency band is from 47MHz to 6GHz, the receiving frequency band is from 70MHz to 6GHz, the two operation modes of TDD and RDD are supported, the bandwidth of a tunable channel is less than 200KHz to 56MHz, and the test sensitivity, noise response and comprehensive precision are improved. And has the capability of multi-chip synchronization, supporting CMOS/LVDS digital interfaces.

Claims

1. The high-performance test method of the wireless communication signal is realized based on a test platform formed by a test module and a field programmable gate array, wherein the test module is provided with a chip AD9361 and an LNA, an active mixer, an amplifier, a DAC and an ADC which are integrated with the chip AD9361, wherein the chip AD9361 is connected with two independent antenna receiving ports through the LNA, and is connected with two independent antenna transmitting ports through the amplifier; moreover, the chip AD9361 is connected with an initialization unit, a reference clock, a control unit, an interface function unit for rapidly locking the set frequency and the power consumption and RF front-end equipment, and is characterized in that: the test method comprises the steps of configuring a reference clock for a test module, and providing accurate synchronization time of an initialization unit and a chip AD 9361; the initialization unit configures the chip AD9361 to operate in a transceiving state, and sets an auxdc_control mode, a port_control port mode, a ctrl_outer_control control mode, a gain mode of gain_control, a rsi_control test mode, an elna_control external gain mode, a tx_monitor_control input power control mode, and an auxiliary auxdc_control control mode, and the chip AD9361 processes signals of each antenna receiving port into a data stream of zero intermediate frequency and outputs the data stream to the field programmable gate array for digital processing.

2. The method for testing high performance of wireless communication signals according to claim 1, wherein: the chip AD9361 is connected with a control unit in a matching mode, and the control unit is used for controlling signal input and signal output in different data forms.