CN106603090B

CN106603090B - 12-channel receiving-transmitting frequency conversion channel device

Info

Publication number: CN106603090B
Application number: CN201710041658.0A
Authority: CN
Inventors: 章圣长; 王劲松
Original assignee: Chengdu Rdw Tech Co ltd
Current assignee: Chengdu Rdw Tech Co ltd
Priority date: 2017-01-20
Filing date: 2017-01-20
Publication date: 2022-10-11
Anticipated expiration: 2037-01-20
Also published as: CN106603090A

Abstract

The invention belongs to the field of frequency conversion channels, and particularly relates to a multi-channel transceiving component for realizing microminiaturization design. The 12-channel frequency conversion transceiver realized by the invention is in a radio frequency band, and has the characteristics of small volume, light weight and high reliability in similar design.

Description

12-channel receiving-transmitting frequency conversion channel device

Technical Field

The invention belongs to the field of frequency conversion channels, and particularly relates to a multichannel transceiving component for realizing microminiaturization design.

Background

The frequency converted channel is located between the antenna and the processor. In the wireless communication link is a critical module. The method mainly completes the conversion of radio frequency signals to intermediate frequency signals required for receiving and the conversion of intermediate frequency transmission signals to radio frequency output signals. Usually, the frequency conversion channel design is implemented by a hybrid integration method. When the multi-channel frequency conversion channel is designed by adopting the mode, the parts are various, the product volume is larger, the weight is large, and the reliability is low. Both of these problems have severely impacted the development of modern wireless communications.

Prior patents are as follows: the invention patent of CN201320269285.X, filed as 2013.05.17, entitled "a multichannel frequency conversion processor in DTMB system", has the following technical contents: the utility model relates to a multichannel frequency conversion treater among DTMB system, the structure includes: signal input port, broadband filter, low noise amplifier, six distributors, multichannel frequency conversion treater, six blenders, signal output port, its characterized in that: the multi-channel frequency conversion processor is composed of six channel frequency conversion processing units with the same specification, and the signal input port is sequentially connected with the broadband filter, the low noise amplifier, the six distributors, the multi-channel frequency conversion processor, the six mixers and the signal output port.

For another example, the patent application No. CN201520947674.2, application date 2015.11.24, and the name "an eight-channel transmitter based on digital up converter", includes the following technical contents: the utility model discloses an eight channel transmitters based on digital up converter, it includes DSP digital signal processor, DSP digital signal processor connects the MCU controller respectively, CPLD programmable logic device, ADC ADC, DUC1 digital up converter and DUC2 digital up converter, the MCU controller is external to have serial ports RS232, TCXO is connected respectively to CPLD programmable logic device, two port RAM, ADC, DSP, DUC1, DUC2, flash and DAC, still be connected with level converter between ADC ADC and the DSP digital signal processor, the external Flash of DSP digital signal processor, the external DAC of DUC1 digital up converter.

Although the two patent problem parts realize multi-channel signal frequency conversion, the two patent problem parts belong to the processing of medium and high frequency signals, the dependence degree of a software radio technology is high, and the technology is not suitable for signal frequency conversion processing in a radio frequency microwave band.

Disclosure of Invention

In order to overcome the design defects of the traditional multipath frequency conversion channel and improve the product reliability, the invention provides a 12-channel transceiving frequency conversion channel.

A12-channel transceiving frequency conversion channel device is characterized in that: the frequency conversion receiving module, the transmitting excitation module, the frequency synthesis module and the power module are integrally divided into an upper layer structure and a lower layer structure, wherein the upper layer structure comprises the power module, the frequency synthesis module and the transmitting excitation module, and the lower layer structure is the frequency conversion receiving module.

The power module comprises a DC-DC and an LDO.

The frequency synthesizer module comprises a clock unit, an S local oscillator, an X local oscillator and an FPGA unit; the clock unit comprises a constant temperature crystal oscillator, an amplifying circuit and a power dividing circuit, wherein the constant temperature crystal oscillator generates a 100MHz clock signal, the clock signal is output to enter a post-stage amplifying circuit to amplify the signal level, the amplified clock signal enters the input end of the power dividing circuit, is output in three paths after passing through the power dividing circuit and is respectively supplied to an S local oscillator, an X local oscillator and an FPGA unit as clock reference signals, and the clock unit mainly provides basic clock signals for the local oscillator and the FPGA. The S local oscillator comprises a phase detector, an operational amplifier and a VCO (voltage controlled oscillator), phase detection voltage output by the phase detector passes through a loop filter formed by the operational amplifier and then is output to enter a voltage tuning end of the VCO, the VCO outputs an S local oscillator signal according to a tuning voltage value, and meanwhile, the output local oscillator signal is divided into a branch circuit and fed back to the phase detector to form a phase-locked loop, so that the output of the S local oscillator signal is realized; the X local oscillator comprises a phase discriminator, an operational amplifier, a VCO (voltage controlled oscillator) and a frequency multiplier, the phase discrimination voltage output by the phase discriminator is output after passing through a loop filter formed by the operational amplifier as an S local oscillator unit and enters a voltage tuning end of the VCO, the VCO outputs an X local oscillator signal according to a tuning voltage value, and the output local oscillator signal is divided into a branch and fed back to the phase discriminator to form a phase-locked loop, so that the output of the X local oscillator signal is realized; the FPGA unit comprises an FPGA chip, a configuration chip and a reset chip, wherein the configuration chip and the reset chip are connected with the FPGA chip through an SPI interface, and the FPGA unit mainly provides data commands for two local oscillators.

The frequency conversion receiving module comprises a radio frequency unit and an intermediate frequency unit, the frequency conversion receiving module consists of four 3-channel sub-modules to form a 12-channel module, three paths of transceiving realized by an LTCC process are included in each sub-module, the radio frequency unit is a transceiving common branch and comprises a first amplifier, a second amplifier, a first filter, a second filter, a first attenuator and a first mixer which are sequentially connected in series through a 50-ohm impedance strip line, and the first mixer realizes the first frequency conversion of a received signal and the second frequency conversion of a transmitted signal; the intermediate frequency unit of the microwave multilayer board process is used for realizing the second frequency conversion of 12 paths of received signals, and comprises a first switch, a third amplifier, a fourth amplifier, a fifth amplifier, a sixth amplifier, a third filter, a fourth filter, a second mixer and a first temperature compensation attenuator which are connected in series sequentially through a 50-ohm impedance strip line. Wherein the second mixer effects a second frequency conversion of the received signal.

The transmitting excitation module mainly realizes transmitting a first-time frequency conversion part circuit and comprises a seventh amplifier, a second attenuator, an eighth amplifier, a fifth filter, a sixth filter, a third mixer and a first power divider which are sequentially connected in series through a 50-ohm impedance strip line, wherein the third mixer realizes transmitting signal first-time frequency conversion, the output of the path is divided into 12 paths by the 12-path power divider and then is connected with a rear-stage radio frequency transceiving common branch.

The invention has the beneficial effects that:

1. the 12-channel frequency conversion transceiver realized by the invention is in a radio frequency band, and has the characteristics of small volume, light weight and high reliability in similar design.

2. The invention comprises an upper layer power module, a frequency synthesis module, a transmitting excitation module and a lower layer frequency conversion receiving module. And the two layers of structures are combined, and the insulators penetrate through the wall to realize upper and lower interconnection, so that the integral structure is more compact, and the integral volume is only 265mm 275mm 41mm.

3. The radio frequency unit part is a transmitting-receiving common branch, so that the space structure and the number of devices can be greatly saved, and the dual compression of the volume and the cost can be realized.

4. The radio frequency unit uses the LTCC process, high integration and miniaturization are further realized, and the reliability of the product is improved.

Drawings

FIG. 1 is an overall schematic view of the present invention.

Fig. 2 is a schematic diagram of 12-channel transceiving channels according to the present invention.

In the drawings: the device comprises a frequency conversion receiving module 1, a transmitting excitation module 2, a frequency synthesis module 3 and a power supply module 4; a radio frequency unit 11, an intermediate frequency unit 12; a clock unit 31, an S local oscillator 32, an X local oscillator 33, and an FPGA unit 34.

In fig. 2, A1 is a first amplifier, A2 is a second amplifier, A3 is a third amplifier, A4 is a fourth amplifier, A5 is a fifth amplifier, A6 is a sixth amplifier, A7 is a seventh amplifier, A8 is an eighth amplifier, BPF1 is a first filter, BPF2 is a second filter, BPF3 is a third filter, BPF4 is a fourth filter, BPF5 is a fifth filter, BPF6 is a sixth filter, MTVA1 is a first temperature-compensated attenuator, MTVA2 is a second temperature-compensated attenuator, MIX1 is a first mixer, MIX2 is a second mixer, MIX3 is a third mixer, KG1 is a first switch, DIV1 is a first power divider, and ATT1 is a first attenuator.

Detailed Description

Example 1

The 12-channel receiving and transmitting frequency conversion channel device comprises a frequency conversion receiving module 1, a transmitting excitation module 2, a frequency synthesis module 3 and a power module 4, and is integrally divided into an upper layer structure and a lower layer structure, wherein the upper layer structure comprises the power module 4, the frequency synthesis module 3 and the transmitting excitation module 2, and the lower layer structure is the frequency conversion receiving module 1. The 12-channel frequency conversion transceiver realized by the invention is in a radio frequency band, and has the characteristics of small volume, light weight and high reliability in similar design.

Example 2

The 12-channel receiving and transmitting frequency conversion channel device comprises a frequency conversion receiving module 1, a transmitting excitation module 2, a frequency synthesis module 3 and a power module 4, and is integrally divided into an upper layer structure and a lower layer structure, wherein the upper layer comprises the power module 4, the frequency synthesis module 3 and the transmitting excitation module 2, and the lower layer is the frequency conversion receiving module 1.

The power module 4 includes a DC-DC and LDO.

The frequency synthesizer module 3 comprises a clock unit 31, an S local oscillator 32, an X local oscillator 33 and an FPGA unit 34; the clock unit 31 includes a constant temperature crystal oscillator, an amplifying circuit and a power dividing circuit, the constant temperature crystal oscillator generates a 100MHz clock signal, and then outputs the clock signal to a post-amplifying circuit for signal level amplification, the amplified clock signal enters an input end of the power dividing circuit, is output in three paths after passing through the power dividing circuit, and is respectively supplied to an S local oscillator 32, an X local oscillator 33 and an FPGA unit 34 as clock reference signals, and the clock unit 31 mainly provides a basic clock signal for the local oscillator and the FPGA. The S local oscillator 32 comprises a phase detector, an operational amplifier and a VCO, a phase detection voltage output by the phase detector is output after passing through a loop filter formed by the operational amplifier, and enters a voltage tuning end of the VCO, the VCO outputs an S local oscillator 32 signal according to a tuning voltage value, and the output local oscillator signal is divided into a branch and fed back to the phase detector to form a phase-locked loop, so that the output of the S local oscillator 32 signal is realized; the X local oscillator 33 comprises a phase detector, an operational amplifier, a VCO (voltage controlled oscillator) and a frequency multiplier, the phase detection voltage output by the phase detector as the S local oscillator 32 unit passes through a loop filter formed by the operational amplifier and then is output to enter a voltage tuning end of the VCO, the VCO outputs an X local oscillator 33 signal according to a tuning voltage value, and the output local oscillator signal is divided into a branch and fed back to the phase detector to form a phase-locked loop, so that the output of the X local oscillator 33 signal is realized; the FPGA unit 34 comprises an FPGA chip, a configuration chip and a reset chip, the configuration chip and the reset chip are connected with the FPGA chip through an SPI interface, and the FPGA unit 34 mainly provides data commands for two local oscillators.

The variable-frequency receiving module 1 comprises a radio frequency unit 11 and an intermediate frequency unit 12, the variable-frequency receiving module 1 comprises a 12-channel module consisting of four 3-channel sub-modules, three-channel transceiving realized by an LTCC process is arranged in each sub-module, the radio frequency unit 11 is a transceiving common branch and comprises a first amplifier, a second amplifier, a first filter, a second filter, a first attenuator and a first mixer which are sequentially connected in series through a 50-ohm impedance strip line, wherein the first mixer realizes first frequency conversion of a received signal and second frequency conversion of a transmitted signal; the intermediate frequency unit 12 is used for realizing secondary frequency conversion of 12 paths of received signals by adopting a microwave multilayer board process, and the intermediate frequency unit 12 comprises a first switch, a third amplifier, a fourth amplifier, a fifth amplifier, a sixth amplifier, a third filter, a fourth filter, a second mixer and a first temperature compensation attenuator which are connected in series sequentially through a 50-ohm impedance strip line. Wherein the second mixer effects a second frequency conversion of the received signal.

The transmitting excitation module 2 mainly realizes transmitting a first frequency conversion part circuit, and comprises a seventh amplifier, a second attenuator, an eighth amplifier, a fifth filter, a sixth filter, a third mixer and a first power divider, which are connected in series sequentially through a 50-ohm impedance strip line, wherein the third mixer realizes transmitting signal first frequency conversion, the output of the path is divided into 12 paths by the 12-path power divider, and then is connected with a rear-stage radio frequency transceiving common branch.

The 12-channel frequency conversion transceiver realized by the invention is in a radio frequency band, and has the characteristics of small volume, light weight and high reliability in similar design. The invention comprises an upper layer power module 4, a frequency synthesis module 3, a transmitting excitation module 2 and a lower layer frequency conversion receiving module 1. And the two layers of structures are combined, and penetrate through the wall through the insulator to realize upper and lower interconnection and intercommunication, so that the integral structure is more compact, and the integral volume is only 265mm 275mm 41mm. The radio frequency unit 11 is a receiving and transmitting common branch, so that the space structure and the number of devices can be greatly saved, and the dual compression of the volume and the cost is realized. The radio frequency unit 11 uses the LTCC process, so that high integration and miniaturization are further realized, and the reliability of the product is improved.

Example 3

On the basis of the

embodiments

1 and 2, as shown in fig. 1, 12 channels transmit and receive the frequency conversion channel, which includes a frequency conversion receiving module 1, a transmission excitation module 2, a frequency synthesis module 3 and a power supply module 4. The frequency conversion receiving module 1 includes two parts, namely a radio frequency unit 11 and an intermediate frequency unit 12, and the frequency synthesis module 3 includes four parts, namely an S local oscillator 32, an X local oscillator 33, an FPGA unit 34 and a clock unit 31.

Fig. 2 is a schematic diagram of a transmitting/receiving channel, in which a transmitting portion is subjected to primary up-conversion, then respectively supplied to 12 transmitting/receiving common branches through 12 power dividers, and finally led out to an antenna end through a waveguide interface after secondary frequency conversion. And the receiving part is used for receiving the signals from the antenna, then reaching the mixer through the 12-path receiving and transmitting common branch to carry out first down-conversion, and then carrying out second down-conversion output through the rear stage.

And the power module 4 adopts DC-DC and LDO to convert the input voltage into the voltage required by each module, and then supplies power to each module respectively. The DC-DC and the LDO are used for supplying power, so that the power supply ripple is extremely small, and the noise resistance is higher.

The clock unit 31 adopts a 100MHz constant temperature crystal oscillator to realize high precision and high stability. The power in the frequency synthesizer module 3 is divided into three paths, and the three paths are respectively provided for a PLL of a local oscillator X33 and a PLL of a local oscillator S32 as reference signals, and provide clock reference signals for the FPGA.

The local oscillator X33, the frequency hopping local oscillator source ring output frequency is 11-11.5 GHz, and the frequency is stepped by 10MHz. A mature single-ring phase-locked loop circuit is adopted, and in order to improve phase noise indexes, the phase-locked loop adopts fractional frequency division and 50MHz phase discrimination. The VCO is selected by adopting a small-volume MMIC VCO, the interior of the VCO is provided with a preposed frequency divider, an independent external preposed frequency divider does not need to be designed, the frequency band of an output signal is wide, and the voltage-controlled voltage of the VCO exceeds the highest voltage which can be output by the phase discriminator, so that the loop filter of the phase-locked loop needs to be realized by adopting an active circuit design, the direct-current amplification is realized by an operational amplifier circuit, and the voltage-controlled range of the VCO is covered.

The two local oscillators S local oscillator 32 adopt a single-loop phase-locked loop circuit, a low-phase noise digital PLL chip, a rail-to-rail operational amplifier and an MMIC VCO are selected, the miniaturized design is achieved, and the output frequency is 4.7GHz.

The FPGA unit 34 mainly comprises an FPGA chip, a crystal, a configuration chip, a reset chip, a download interface, an LDO module and a connector, wherein the power supply of the module unit is supplied with +6V by a PCB through a plug connector, and the LDO with small package is transferred to the FPGA and other chips. The module mainly configures data for two ways of local oscillators PLL, and realizes S local oscillator 32 frequency output and X local oscillator 33 frequency hopping output.

The frequency conversion receiving module 1 comprises a radio frequency unit 11 and an intermediate frequency unit 12. The radio frequency unit 11 is a transmitting and receiving common part, and the intermediate frequency unit 12 is a receiving double-conversion part.

The first amplifier is a low noise amplifier, amplifies input signals, inputs the input signals with the frequency of 18500 +/-500 MHz and the power of-90 dBm, and outputs-72 dBm after amplification.

The first filter is a thin film filter and has a low loss characteristic. The first amplified output is filtered, the output frequency is 18500MHz with bandwidth of 1000MHz and power of-76 dBm.

The second amplifier is a low noise amplifier and amplifies the output signal of the first filter, wherein the frequency is 18500 +/-500 MHz, and the power is-59 dBm.

The first attenuator is a numerical control attenuator, and can realize control of different attenuation amounts by controlling the attenuation of the first attenuator through the FPGA. The attenuator is used for attenuating the signal of the second amplifier, the output frequency is unchanged, and the power is-63 dBm.

And the first frequency mixer is used for mixing the output signal of the first attenuator with the output frequency signal of the X local oscillator 33 to generate a 4000MHz frequency signal. The output power was-73 dBm.

And the second filter filters the output signal of the first mixer, the output center frequency of the second filter is 4000MHz, and the output power of the second filter is-75 dBm.

The first switch, which is a single pole double throw switch, switches between transmit and receive. In the transmitting state, the switch points to the transmitting path, and in the receiving state, the switch points to the receiving path. The switch is controlled by the FPGA.

And the third amplifier is positioned in an intermediate frequency receiving part and is used for amplifying the received signal output by the first switch, the signal output frequency is 4000MHz, and the output power is-61 dBm.

And the fourth amplifier amplifies the output signal of the third amplifier, wherein the output frequency is 4000MHz, and the power is-46 dBm.

And the third filter is used for filtering the fourth amplified output signal, so that interference signals are prevented from entering the second mixer to generate stray signals. The frequency of the output signal is 4000MHz, and the power is-53 dBm.

And the second frequency mixer mixes the output signal of the third filter and the output frequency signal of the S local oscillator 32 to generate a 700MHz frequency signal. The output power was-68 dBm.

And the fourth filter is used for filtering the output signal of the second mixer, the output center frequency of the fourth filter is 700MHz, and the output power of the fourth filter is-71 dBm.

And the fifth amplifier amplifies the output signal of the fourth filter, wherein the output frequency is 700MHz, and the power is-37 dBm.

The first attenuator is a temperature compensation attenuator and compensates the gain of the receiving link under different environments of high and low temperatures, so that the gain fluctuation is reduced. The output signal frequency is 700MHz and the power is-44 dBm.

And the sixth amplifier amplifies the output signal of the first temperature-compensation attenuator, wherein the output frequency is 700MHz, and the power is-11 dBm.

The seventh amplifier is a transmitting link amplifier, amplifies an intermediate frequency transmitting signal 700MHz, and outputs an input signal of-15 dBm and 0 dBm.

The second attenuator is a temperature compensation attenuator and compensates the gain of the transmitting link under different environments of high and low temperatures, so that the gain fluctuation is reduced. The output signal frequency is 700MHz and the power is 6 dBm.

And the fifth filter is used for filtering the output signal of the seventh amplifier, the output center frequency of the fifth filter is 700MHz, and the output power of the fifth filter is 4 dBm.

And the third mixer mixes the output signal of the fifth filter and the output frequency signal of the S local oscillator 32 to generate a 4000MHz frequency signal. The output power was-6 dBm.

And the sixth filter is used for filtering the output of the third mixer and suppressing stray signals, and the output frequency of the sixth filter is 4000MHz and the power of the sixth filter is-9 dBm.

And the eighth amplifier amplifies the output of the sixth filter, wherein the output center frequency of the eighth amplifier is 700MHz, and the output power of the eighth amplifier is 9 dBm.

The first power divider is a 12-path power divider, and divides the output of the eighth amplifier into 12 paths to supply to 12 transmit-receive common branches. The output frequency of the first power divider is 4000MHz, and the power is-3 dBm.

Claims

1. A12-channel transceiving frequency conversion channel device is characterized in that: the device comprises a variable frequency receiving module (1), a transmitting excitation module (2), a frequency synthesis module (3) and a power module (4), the whole device is divided into an upper layer structure and a lower layer structure, wherein the upper layer comprises the power module (4), the frequency synthesis module (3) and the transmitting excitation module (2), and the lower layer is the variable frequency receiving module (1);

the frequency synthesis module (3) comprises a clock unit (31), an S local oscillator (32), an X local oscillator (33) and an FPGA unit (34); the clock unit (31) comprises a constant temperature crystal oscillator, an amplifying circuit and a power dividing circuit, the constant temperature crystal oscillator generates a clock signal of 100MHz, the clock signal is output to a post-stage amplifying circuit to amplify the signal level, the amplified clock signal enters the input end of the power dividing circuit, is output in three paths after the power dividing circuit, and is respectively supplied to an S local oscillator (32), an X local oscillator (33) and an FPGA unit (34) as clock reference signals, the clock unit (31) provides basic clock signals for the local oscillator and the FPGA, the S local oscillator (32) comprises a phase discriminator, an operational amplifier and a VCO, phase discrimination voltage output by the phase discriminator is output after passing through a loop filter formed by the operational amplifier and enters a voltage tuning end of the VCO, the S local oscillator (32) signal is output according to a tuning voltage value, and a branch is divided by the output local oscillator signal and is fed back to the phase discriminator to form a phase-locked loop, so that the output of the S local oscillator (32) signal is realized; the X local oscillator (33) comprises a phase detector, an operational amplifier, a VCO (voltage controlled oscillator) and a frequency multiplier, phase detection voltage output by the phase detector as an S local oscillator (32) unit passes through a loop filter formed by the operational amplifier and then is output to enter a voltage tuning end of the VCO, the VCO outputs an X local oscillator (33) signal according to a tuning voltage value, and meanwhile, the output local oscillator signal is divided into a branch circuit and fed back to the phase detector to form a phase-locked loop, so that the output of the X local oscillator (33) signal is realized; the FPGA unit (34) comprises an FPGA chip, a configuration chip and a reset chip, the configuration chip and the reset chip are connected with the FPGA chip through an SPI (serial peripheral interface), and the FPGA unit (34) mainly provides data commands for two local oscillators;

the frequency conversion receiving module (1) comprises a radio frequency unit (11) and an intermediate frequency unit (12), the frequency conversion receiving module (1) is a 12-channel module consisting of four 3-channel sub-modules, three-channel transceiving realized by adopting an LTCC process is arranged in each sub-module, the radio frequency unit (11) is a transceiving common branch and comprises a first amplifier, a second amplifier, a first filter, a second filter, a first attenuator and a first mixer, wherein the first mixer realizes the first frequency conversion of a received signal and the second frequency conversion of a transmitted signal; the intermediate frequency unit (12) of the microwave multilayer board process is used for realizing secondary frequency conversion of 12 paths of received signals, the intermediate frequency unit (12) comprises a first switch, a third amplifier, a fourth amplifier, a fifth amplifier, a sixth amplifier, a third filter, a fourth filter, a second mixer and a first temperature compensation attenuator, and the second mixer is used for realizing secondary frequency conversion of the received signals; the power supply module (4) comprises a DC-DC and an LDO; the transmitting excitation module (2) mainly realizes transmitting a first-time frequency conversion part circuit, and comprises a seventh amplifier, a second attenuator, an eighth amplifier, a fifth filter, a sixth filter, a third mixer and a first power divider, wherein the third mixer realizes transmitting signal first-time frequency conversion, the output of the path is divided into 12 paths by the 12-path power divider, and then the path is connected with a rear-stage radio frequency transmitting and receiving common branch.