CN113556145B - Data processing method and device, electronic equipment and storage medium - Google Patents
Data processing method and device, electronic equipment and storage medium Download PDFInfo
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- CN113556145B CN113556145B CN202010334791.7A CN202010334791A CN113556145B CN 113556145 B CN113556145 B CN 113556145B CN 202010334791 A CN202010334791 A CN 202010334791A CN 113556145 B CN113556145 B CN 113556145B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/401—Circuits for selecting or indicating operating mode
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/08—Access point devices
- H04W88/10—Access point devices adapted for operation in multiple networks, e.g. multi-mode access points
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The embodiment of the invention provides a data processing method and device, electronic equipment and a storage medium, which are applied to a dual-mode base station, wherein the dual-mode base station is provided with a communication chip, the communication chip corresponds to a dual-mode working mode through preset configuration, and the method comprises the following steps: the method comprises the steps of presetting a plurality of channel information, establishing a corresponding relation between the plurality of channel information and a dual-mode working mode, acquiring first communication data when a dual-mode base station receives and transmits signals, determining a target working mode corresponding to the first communication data, determining target channel information corresponding to the target working mode, determining target frequency point information corresponding to the target channel information, processing the first communication data by adopting the target frequency point information, and obtaining second communication data. By the embodiment of the invention, the optimal configuration of the dual-mode base station is realized, and one communication chip is adopted to correspond to a plurality of working modes, so that the integration level can be improved, the board card area is reduced, the number of devices is reduced, the power consumption is reduced, and the cost is reduced.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a data processing method and apparatus, an electronic device, and a storage medium.
Background
With the development and application of communication technology entering the 5G era, various supporting devices at the initial stage of 5G commercial are still incomplete, and cannot be completely switched to 5G communication. In order to save capital and manpower for equipment purchase and construction investment and open the conversion from 4G function to 5G without replacing equipment, a large number of 4G base stations currently in use need to be adopted, so that the base stations can be compatible with 4G and 5G, and the transition from 4G to 5G is realized.
Because the 4G and 5G adopt different communication modes, most transceiver chips based on base station applications are limited to single-mode applications, that is, one transceiver chip corresponds to one communication mode, and therefore, for multi-mode applications of base stations, a mainstream base station transceiver will adopt multiple transceiver chips to combine to realize dual-mode or multi-mode functions.
In the prior art, for a dual-mode base station in 4G mode and 5G mode, two ways are generally adopted to implement dual-mode application: firstly, a multi-channel product is built through original discrete elements, and secondly, two transceiver chips are adopted, one chip is used for a 5G mode, and the other chip is used for a 4G mode. However, the above two methods have the disadvantages of large occupied board layout area, high power consumption, high cost and the like.
Disclosure of Invention
In view of the above, it is proposed to provide a method and apparatus, an electronic device, a storage medium for data processing that overcome or at least partially solve the above problems, including:
a data processing method is applied to a dual-mode base station, the dual-mode base station is provided with a communication chip, the communication chip corresponds to a dual-mode working mode through preset configuration, and the method comprises the following steps:
presetting a plurality of channel information, and establishing a corresponding relation between the plurality of channel information and the dual-mode working mode;
when the dual-mode base station receives and sends signals, first communication data are obtained, and a target working mode corresponding to the first communication data is determined;
determining target channel information corresponding to the target working mode;
and determining target frequency point information corresponding to the target channel information, and processing the first communication data by adopting the target frequency point information to obtain second communication data.
Optionally, the communication chip is configured with a processing channel and a local oscillation circuit for each operating mode, where each processing channel corresponds to one channel information, and each local oscillation circuit corresponds to one frequency point information.
Optionally, the communication chip is configured with a clock circuit, and the processing the first communication data by using the target frequency point information to obtain second communication data includes:
acquiring a reference clock provided by the clock circuit aiming at the local oscillator circuit;
and processing the first communication data by adopting the reference clock and the target frequency point information to obtain second communication data.
Optionally, the dual mode operating mode comprises a time division duplex operating mode,
the step of determining the target channel information corresponding to the target working mode includes:
determining first target channel information corresponding to the time division duplex working mode; the first target channel information comprises first receiving channel information, first transmitting channel information and first feedback channel information;
the step of determining the target frequency point information corresponding to the target channel information comprises:
and determining that the first receiving channel information, the first transmitting channel information and the first feedback channel information correspond to first frequency point information.
Optionally, the dual mode operating mode comprises a frequency division duplex operating mode,
the step of determining the target channel information corresponding to the target working mode includes:
determining second target channel information corresponding to the frequency division duplex working mode; the second target channel information comprises second receiving channel information, second transmitting channel information and second feedback channel information;
the step of determining the target frequency point information corresponding to the target channel information comprises:
determining that the second receiving channel information corresponds to second frequency point information;
and determining that the second transmitting channel information and the second feedback channel information correspond to third frequency point information.
Optionally, the communication chip is a zero intermediate frequency transceiver chip.
Optionally, the method further comprises:
and under the time division duplex working mode, a field programmable gate array circuit is adopted for time slot control and radio frequency front end switch control.
A data processing device is applied to a dual-mode base station, the dual-mode base station is provided with a communication chip, the communication chip corresponds to a dual-mode working mode through preset configuration, and the data processing device comprises:
the corresponding relation establishing module is used for presetting a plurality of channel information and establishing the corresponding relation between the plurality of channel information and the dual-mode working mode;
a target working mode determining module, configured to obtain first communication data when the dual-mode base station receives and sends a signal, and determine a target working mode corresponding to the first communication data;
the target channel information determining module is used for determining target channel information corresponding to the target working mode;
and the target frequency point information determining module is used for determining target frequency point information corresponding to the target channel information, and processing the first communication data by adopting the target frequency point information to obtain second communication data.
Optionally, the communication chip is configured with a processing channel and a local oscillation circuit for each operating mode, where each processing channel corresponds to one channel information, and each local oscillation circuit corresponds to one frequency point information.
Optionally, the communication chip is configured with a clock circuit, and the target frequency point information determining module includes:
providing a reference clock submodule for acquiring a reference clock provided by the clock circuit for the local oscillator circuit;
and the target frequency point information determining submodule is used for processing the first communication data by adopting the reference clock and the target frequency point information to obtain second communication data.
Optionally, the dual mode operating mode comprises a time division duplex operating mode,
the target channel information determination module comprises:
a first target channel information determining submodule, configured to determine first target channel information corresponding to the time division duplex operating mode; the first target channel information comprises first receiving channel information, first transmitting channel information and first feedback channel information;
the target frequency point information determining module comprises:
and the first target frequency point information determining submodule is used for determining that the first receiving channel information, the first transmitting channel information and the first feedback channel information correspond to first frequency point information.
Optionally, the dual mode operating mode comprises a frequency division duplex operating mode,
the target channel information determination module comprises:
a second target channel information determining submodule, configured to determine second target channel information corresponding to the fdd working mode; the second target channel information comprises second receiving channel information, second transmitting channel information and second feedback channel information;
the target frequency point information determining module comprises:
a second target frequency point information determining submodule, configured to determine that the second receiving channel information corresponds to second frequency point information;
and the third target frequency point information determining submodule is used for determining the second transmitting channel information and the second feedback channel information corresponding to third frequency point information.
Optionally, the communication chip is a zero intermediate frequency transceiver chip.
Optionally, the apparatus further comprises:
and the circuit control module is used for carrying out time slot control and radio frequency front end switch control by adopting a field programmable gate array circuit in the time division duplex working mode.
The embodiment of the invention has the following advantages:
in the embodiment of the invention, the dual-mode base station is provided with a communication chip, the communication chip corresponds to a dual-mode working mode through preset configuration, a plurality of channel information is preset, the corresponding relation between the plurality of channel information and the dual-mode working mode is established, then when the dual-mode base station receives and sends signals, first communication data is obtained, a target working mode corresponding to the first communication data is determined, target channel information corresponding to the target working mode is determined, further target frequency point information corresponding to the target channel information is determined, the first communication data is processed by adopting the target frequency point information, second communication data is obtained, optimal configuration aiming at the dual-mode base station is realized, and the integration level can be improved, the board card area is reduced, the number of devices is reduced, the power consumption is reduced, and the cost is reduced by adopting the communication chip to correspond to the plurality of working modes.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a flow chart illustrating steps of a method for data processing according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an internal structure of a transceiver chip according to an embodiment of the present invention;
FIG. 3 is a flow chart of steps in another method of data processing according to an embodiment of the invention;
fig. 4 is a schematic diagram of an internal structure of a dual-mode (TDD and FDD) transceiver chip according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a flowchart illustrating steps of a method for data processing according to an embodiment of the present invention is shown, where the method may be applied to a dual-mode base station, and the dual-mode base station may have a communication chip, and the communication chip may correspond to a dual-mode operating mode according to a preset configuration.
The communication chip can be a zero intermediate frequency radio transceiver chip, the communication chip can be configured with a processing channel and a local oscillator circuit for each working mode, each processing channel corresponds to channel information, and each local oscillator circuit corresponds to frequency point information.
Specifically, the method can comprise the following steps:
the channel information may include receiving channel information, transmitting channel information, and feedback channel information, and each of the dual-mode operating modes may correspond to one of the receiving channel information, the transmitting channel information, and the feedback channel information.
In the process of configuring the communication chip, a plurality of pieces of receiving channel information, a plurality of pieces of transmitting channel information and a plurality of pieces of feedback channel information can be preset, and the corresponding receiving channel information, transmitting channel information and feedback channel information are established for the dual-mode working mode.
In practical application, the communication chip can simultaneously support the dual-mode working mode through special setting aiming at the inside of the communication chip, for example, a zero intermediate frequency transceiver chip (i.e. a zero intermediate frequency transceiver chip) with more than four channels can be adopted to carry out special setting aiming at the inside of the chip, and then the chip can be applied to a dual-mode base station and can simultaneously support the dual-mode working mode, and the dual-mode transceiver frequency band of the dual-mode base station can be 650MHz-6000MHz.
the transceiver chip can process signals in the dual-mode working mode, configure processing channels for each working mode in the dual-mode working mode, and establish a corresponding relationship between a plurality of channel information and the dual-mode working mode because each processing channel corresponds to one channel information, for example, one working mode can correspond to one receiving channel, one transmitting channel and one feedback channel. By adopting a plurality of processing channels in a transceiver chip and configuring the corresponding processing channel for each working mode, the dual-mode base station application with the transceiver chip can be realized.
In an example, a plurality of processing channels and a plurality of PLL (Phase Locked Loop) modules may be integrated inside a transceiver chip, and the plurality of PLL modules may be used for an LO (Line out) local oscillator circuit, so that a plurality of independent channels and a plurality of independent PLL modules inside the chip may be adopted to implement dual-mode application of the dual-mode base station.
In yet another example, a phase-locked loop module integrated inside the transceiver chip may generate a local oscillation signal for the quadrature modulator and the quadrature demodulator.
Compared with two chips used by the existing dual-mode base station, the independent zero intermediate frequency transceiver device aiming at a plurality of local oscillator circuits (LO) and a plurality of channels is integrated in one transceiver chip, so that the design of equipment miniaturization, low power consumption and low cost can be fully embodied.
102, when the dual-mode base station receives and transmits signals, acquiring first communication data, and determining a target working mode corresponding to the first communication data;
as an example, the first communication data may be signal data to be processed by the base station, the target operation mode may be a signal processing operation mode corresponding to a signal type of the first communication data, such as a 4G signal in a 4G network or a 5G signal in a 5G network, the 4G signal may correspond to the 4G signal processing operation mode, and the 5G signal may correspond to the 5G signal processing operation mode.
In a specific implementation, when the dual-mode base station receives and transmits a signal, to-be-processed communication data may be acquired, and then a signal processing working mode corresponding to the communication data may be determined according to a signal type of the communication data, so as to perform signal processing on the communication data by using the signal processing working mode.
For example, when the dual-mode base station transmits and receives a 4G signal, an FDD (Frequency-division Duplex) mode for 4G may be adopted, so as to further perform signal processing on the 4G signal; when the dual-mode base station receives and transmits a 5G signal, a Time-division Duplex (TDD) mode for the 5G signal may be used to further perform signal processing on a 4G signal.
In an example, the dual-mode base station transceiving signal may be configured to process a signal received by the base station, and may obtain to-be-processed communication data by receiving the signal, and then may determine a signal processing working mode corresponding to the communication data according to a signal type of the communication data, so as to perform signal processing on the communication data in the signal processing working mode.
In another example, the dual-mode base transceiver station may process a signal to be transmitted by the base station, and may determine a signal processing operation mode corresponding to the communication data according to a signal type of the communication data by acquiring the signal to be transmitted by the base station as the communication data to be processed, so as to perform signal processing on the communication data in the signal processing operation mode.
as an example, the target channel information may be channel information corresponding to a channel for signal data to be processed in a signal processing operating mode, such as receiving channel information, transmitting channel information, or feedback channel information in a 4G FDD mode, and receiving channel information, transmitting channel information, or feedback channel information in a 5G TDD mode.
After determining the target operating mode, target channel information for the communication data to be processed in the operating mode may be determined, so as to further process the communication data by using the target channel information.
Specifically, in the 4G FDD mode, TRX channel information (i.e., receive channel information and transmit channel information) and FB channel information (i.e., feedback channel information) may exist; there may be TRX channel information and FB channel information in the TDD mode of 5G.
And 104, determining target frequency point information corresponding to the target channel information, and processing the first communication data by adopting the target frequency point information to obtain second communication data.
As an example, the target frequency point information may be frequency point information for target channel information, such as a local oscillator circuit LO frequency point corresponding to the target channel; the second communication data may be signal data to be sent by the base station, such as a signal sent to a UE (user Equipment).
After the target channel information is determined, the local oscillator circuit LO frequency point of the target channel may be determined, and the first communication data may be processed by using the corresponding local oscillator circuit LO, so that the communication data to be sent may be obtained to send to the UE.
In practical application, when a dual-mode base station receives and transmits signals, local oscillation signals can be generated by the obtained signal data to be processed through a local oscillation circuit LO in the processing channel, signal conversion can be performed through the quadrature demodulator or the quadrature modulator, the processed signals are sent to subsequent devices of the processing channel to further process the signals, and the processed signals can be sent to the UE through the base station.
In an embodiment of the present invention, the communication chip may be configured with a clock circuit, and the step of processing the first communication data by using the target frequency point information to obtain the second communication data may include the following sub-steps:
acquiring a reference clock provided by the clock circuit aiming at the local oscillator circuit; and processing the first communication data by adopting the reference clock and the target frequency point information to obtain second communication data.
In specific implementation, a clock circuit may be configured on the communication chip, and then a reference clock provided by the clock circuit for the local oscillator circuit may be obtained, so that the first communication data may be processed by using the reference clock and the target frequency point information, and then the communication data to be sent may be obtained to send to the UE.
In one example, the transceiver chip may have a clock circuit integrated therein, the clock circuit may provide a reference clock and a sampling clock for the phase-locked loop, the analog-to-digital converter, and the digital-to-analog converter, and the reference clock of the clock circuit itself may be provided by an external circuit.
In order to enable those skilled in the art to better understand the above steps, the following is an example to illustrate the embodiments of the present invention, but it should be understood that the embodiments of the present invention are not limited thereto.
As shown in fig. 2, the radio frequency transceiver chip is a core device for the dual-mode base station transceiver, and 3 independent local oscillator circuits LO and 2 independent FB channels are integrated inside the radio frequency transceiver chip. the circuit adopts highly integrated receiving and dispatching passageway in the transmitter chip, and its chip inner structure includes: a receiving adjustable attenuator, a quadrature demodulator, a receiving amplifier, an anti-aliasing filter and an analog-digital converter (ADC) in an RX channel (namely a receiving channel); a digital-to-analog converter DAC, a reconstruction filter, a transmission amplifier, a quadrature modulator and a VGA module in a TX channel (namely a transmission channel); a demodulator, an anti-aliasing filter and an analog-to-digital converter in the FB channel (namely a feedback channel); and devices such as a clock circuit, a local oscillation circuit LO1, a local oscillation circuit LO2, a local oscillation circuit LO3, a data interface RX _204B, TX _204B, FB _204B, SPI interface, a GPIO interface and the like.
Compared with a traditional dual-mode transceiver built by using two transceiver chips or discrete devices, the dual-mode base station transceiver applying the radio frequency transceiver chip has the advantages that the board card area is reduced, the number of the devices is reduced, the power consumption is reduced, and the cost is reduced.
A circuit in the transceiver chip implements receiving, transmitting and feedback receiving of signals through a zero intermediate frequency scheme, and for an RX channel (i.e., a receiving channel), a single-ended radio frequency signal (i.e., first communication data) sent by a radio frequency front end circuit is received, the single-ended radio frequency signal can be processed by an adjustable attenuator and then sent to a quadrature demodulator, the demodulator converts the single-ended radio frequency signal into an analog IQ signal of zero frequency by using a local oscillation signal (provided by a clock circuit) generated by a local oscillation circuit LO, the analog IQ signal can be sent to an analog-to-digital converter after signal amplification and filtering processing is performed by using a receiving amplifier and an anti-aliasing filter, sampling for the analog IQ signal (provided by the clock circuit) is completed, and then a digital IQ signal can be generated, and the digital IQ signal is sent to an FPGA (Field Programmable Gate Array) circuit through a serial high-speed data interface RX _204B to perform signal receiving.
For a TX channel (i.e., a transmission channel), a baseband signal sent by the FPGA circuit may be sent to a digital-to-analog converter through a data interface TX _204B, and the digital-to-analog converter generates an analog IQ signal (a sampling clock is provided by a clock circuit), and then the analog IQ signal may be sent to a quadrature modulator after signal amplification and filtering processing is performed by using a reconstruction filter and a transmission amplifier, and the modulator converts the analog IQ signal of zero frequency into a single-ended radio frequency signal (i.e., second communication data) by using a local oscillation signal (a reference clock is provided by the clock circuit) generated by a local oscillation circuit LO, and then the single-ended radio frequency signal may be sent to a power amplifier input port through a VGA module for signal transmission.
For an FB channel (namely a feedback channel), a single-ended radio frequency signal coupled with a power amplifier circuit is sent to a quadrature demodulator, the demodulator converts the single-ended radio frequency signal into a zero-frequency analog IQ signal by using a local oscillation signal (a reference clock is provided by a clock circuit) generated by a local oscillation circuit LO, and then after filtering processing is performed by using an anti-aliasing filter, the analog IQ signal can be sent to an analog-to-digital converter to complete sampling for the analog IQ signal (a sampling clock is provided by the clock circuit), so that a digital IQ signal can be generated, and the digital IQ signal is sent to an FPGA circuit through a serial high-speed data interface FB _204B to perform feedback receiving on a transmitting signal.
the transceiver chip is internally integrated with a phase-locked loop module and can generate local oscillation signals aiming at the quadrature modulator and the quadrature demodulator.
the transceiver chip is integrated with a clock circuit, which can provide a reference clock and a sampling clock for the phase-locked loop module, the analog-to-digital converter and the digital-to-analog converter, the clock circuit can correspond to a local oscillator circuit LO1, a local oscillator circuit LO2 and a local oscillator circuit LO3, and each local oscillator circuit has a corresponding frequency point (i.e. frequency point information).
In the embodiment of the invention, the dual-mode base station is provided with the communication chip, the communication chip corresponds to the dual-mode working mode through preset configuration, a plurality of channel information is preset, the corresponding relation between the plurality of channel information and the dual-mode working mode is established, then when the dual-mode base station receives and sends signals, the first communication data is obtained, the target working mode corresponding to the first communication data is determined, the target channel information corresponding to the target working mode is determined, the target frequency point information corresponding to the target channel information is further determined, the first communication data is processed by adopting the target frequency point information, the second communication data is obtained, the optimal configuration aiming at the dual-mode base station is realized, and the integration level can be improved, the board area is reduced, the number of devices is reduced, the power consumption is reduced, and the cost is reduced by adopting the communication chip corresponding to the plurality of working modes.
Referring to fig. 3, a flowchart illustrating steps of another data processing method according to an embodiment of the present invention is shown, where the method may be applied to a dual-mode base station, and the dual-mode base station may have a communication chip, and the communication chip may correspond to a dual-mode operating mode according to a preset configuration.
The communication chip can be a zero intermediate frequency radio transceiver chip, the communication chip can be configured with a processing channel and a local oscillator circuit for each working mode, each processing channel corresponds to channel information, and each local oscillator circuit corresponds to frequency point information.
Specifically, the method can comprise the following steps:
in the process of configuring the communication chip, a plurality of receiving channel information, a plurality of transmitting channel information and a plurality of feedback channel information can be preset, and the corresponding receiving channel information, transmitting channel information and feedback channel information are established aiming at the dual-mode working mode.
in a specific implementation, when the dual-mode base station receives and transmits a signal, and when communication data to be processed can be acquired, a signal processing working mode corresponding to the communication data can be determined according to a signal type of the communication data, so that the signal processing working mode is adopted to perform signal processing on the communication data.
after determining the target operating mode, target channel information for the communication data to be processed in the operating mode may be determined, so as to further process the communication data by using the target channel information.
In an embodiment of the present invention, the dual mode operation mode includes a time division duplex operation mode, and step 303 may include the following sub-steps:
determining first target channel information corresponding to the time division duplex working mode; the first target channel information includes first receiving channel information, first transmitting channel information, and first feedback channel information.
After the target working mode is determined to be the time division duplex working mode, the first receiving channel information, the first transmitting channel information and the first feedback channel information corresponding to the time division duplex working mode can be determined, so that the communication data is further processed by adopting the first receiving channel information, the first transmitting channel information or the first feedback channel information.
In practical application, when the dual-mode base station receives and transmits a 5G signal, the target channel information may be determined according to the corresponding processing channel information (the first receiving channel information, the first transmitting channel information, and the first feedback channel information) in the TDD mode (i.e., time division duplex operating mode) of 5G, so as to process the 5G signal by using the target processing channel.
For example, the processing channel information corresponding to the 5G TDD mode may be first receiving channel information, first transmitting channel information, and first feedback channel information, and it is determined that the first target channel information corresponding to the TDD mode may be one of the processing channel information, and then the 5G signal may be processed by using a target processing channel (e.g., a receiving channel, a transmitting channel, and a feedback channel).
In an embodiment of the present invention, the dual mode operation mode includes a frequency division duplex operation mode, and step 303 may further include the following sub-steps:
determining second target channel information corresponding to the frequency division duplex working mode; the second target channel information includes second receiving channel information, second transmitting channel information, and second feedback channel information.
After the target working mode is determined to be the frequency division duplex working mode, second receiving channel information, second transmitting channel information and second feedback channel information corresponding to the frequency division duplex working mode can be determined, so that the communication data is further processed by adopting the second receiving channel information, the second transmitting channel information or the second feedback channel information.
In practical application, when the dual-mode base station receives and transmits a 4G signal, the target channel information may be determined according to the corresponding processing channel information (second receiving channel information, second transmitting channel information, and second feedback channel information) in the FDD mode (instant frequency division multiplexing operation mode) of 4G, so as to process the 4G signal by using the target processing channel.
For example, the processing channel information corresponding to the 4G FDD mode may be second receiving channel information, second transmitting channel information, and second feedback channel information, and it is determined that the second target channel information corresponding to the FDD mode may be one of the processing channel information, and then the target processing channel (e.g., the receiving channel, the transmitting channel, and the feedback channel) may be used to process the 4G signal.
after the target channel information is determined, the local oscillator circuit LO frequency point of the target channel may be determined, so as to process the first communication data by using the corresponding local oscillator circuit LO.
In an embodiment of the present invention, the dual-mode operating mode includes a time division duplex operating mode, and the step of determining the target frequency point information corresponding to the target channel information may include the following sub-steps:
and determining that the first receiving channel information, the first transmitting channel information and the first feedback channel information correspond to first frequency point information.
After the target channel information in the time division duplex working mode is determined, the local oscillator circuit LO frequency point of the target channel may be determined according to the target channel information, and if the first receiving channel information, the first transmitting channel information, and the first feedback channel information correspond to the first frequency point information, that is, the same frequency point, and then the same local oscillator circuit LO, such as local oscillator circuit LO1, may be adopted for the first receiving channel, the first transmitting channel, and the first feedback channel.
In practical application, after determining the target channel information in the 5G TDD mode (i.e., the TDD operating mode), it may be determined that the first receiving channel, the first transmitting channel, and the first feedback channel are the same frequency point according to that the first receiving channel information, the first transmitting channel information, and the first feedback channel information correspond to the first frequency point information, and the same local oscillator circuit LO1 may be used.
In an embodiment of the present invention, the dual mode operating mode includes a frequency division duplex operating mode, and the step of determining the target frequency point information corresponding to the target channel information may include the following sub-steps:
determining that the second receiving channel information corresponds to second frequency point information; and determining that the second transmitting channel information and the second feedback channel information correspond to third frequency point information.
After the target channel information in the frequency division duplex working mode is determined, the LO frequency point of the local oscillator circuit of the target channel may be determined according to the target channel information, if the second receiving channel information corresponds to the second frequency point information, the second transmitting channel information and the second feedback channel information correspond to the third frequency point information, that is, the second transmitting channel and the second feedback channel are the same frequency point, the frequency point of the second receiving channel is different from the second transmitting channel and the second feedback channel, and then an individual LO circuit LO may be adopted for the second receiving channel, if the LO circuit LO2, the same LO circuit LO may be adopted for the second transmitting channel and the second feedback channel, if the LO circuit LO3.
In practical application, after determining the target channel information in the 4G FDD mode (i.e., the frequency division duplex operating mode), it may be determined that the second receiving channel adopts an individual local oscillation circuit LO2, and the second transmitting channel and the second feedback channel are at the same frequency point, and may adopt the same local oscillation circuit LO3, according to that the second receiving channel information corresponds to the second frequency point information, and the second transmitting channel information and the second feedback channel information correspond to the third frequency point information.
as an example, the communication chip may be configured with a clock circuit that may provide a reference clock and a sampling clock for the phase locked loop, the analog-to-digital converter, the digital-to-analog converter, and the digital-to-analog converter.
In a specific implementation, a reference clock provided by the clock circuit for the local oscillator circuit may be obtained, for example, the reference clock for the local oscillator circuit LO1, the local oscillator circuit LO2, and the local oscillator circuit LO3 may be obtained by the clock circuit.
In an example, for the 5G TDD mode, the clock circuit may obtain a reference clock of the TDD local oscillator using the local oscillator circuit LO1.
In yet another example, for the FDD mode of 4G, a reference clock of the FDD RX local oscillator using the local oscillator circuit LO2 and a reference clock of the FDD TX/FB local oscillator using the local oscillator circuit LO3 may be obtained by the clock circuit.
And step 306, processing the first communication data by using the reference clock and the target frequency point information to obtain second communication data.
After the reference clock is obtained, the first communication data can be processed by adopting the reference clock and the target frequency point information, and then the communication data to be sent can be obtained to be sent to the UE.
In practical application, a reference clock provided by a clock circuit for a local oscillator circuit can be obtained, the local oscillator circuit LO can be determined for a target processing channel according to target frequency point information, then the reference clock and the local oscillator circuit LO can be adopted to generate a local oscillation signal, signal conversion can be performed through an orthogonal demodulator or an orthogonal modulator, and the processed signal is sent to a subsequent device of the processing channel to be further processed, so that a signal to be sent is obtained and sent to the UE.
In an example, in a 5G TDD mode, a clock circuit may obtain a reference clock of a TDD local oscillator using a local oscillator circuit LO1, and then the reference clock of the TDD local oscillator and the local oscillator circuit LO1 may be used to generate a local oscillator signal, so that signal conversion may be performed by an orthogonal demodulator or an orthogonal modulator, and the processed signal is sent to a subsequent device of a processing channel to further process the signal, so as to obtain a signal to be sent, and send the signal to the UE.
In yet another example, for the 4G FDD mode, a reference clock of an FDD RX local oscillator using the local oscillator circuit LO2 and a reference clock of an FDD TX/FB local oscillator using the local oscillator circuit LO3 may be obtained by the clock circuit, and then the reference clock of the FDD RX local oscillator and the local oscillator circuit LO2 may be used to generate a local oscillator signal, and the reference clock of the FDD TX/FB local oscillator and the local oscillator circuit LO3 generate another local oscillator signal, so that signal conversion may be performed by the orthogonal demodulator or the orthogonal modulator, and the processed signal is sent to a subsequent device of the processing channel to further process the signal, so as to obtain a signal to be sent to the UE.
In an embodiment of the present invention, the method may further include:
and under the time division duplex working mode, a field programmable gate array circuit is adopted to carry out time slot control and radio frequency front end switch control.
In a specific implementation, an FPGA circuit (i.e., a field programmable gate array circuit) may be used to perform timeslot control and rf front-end switch control for a TDD mode (i.e., a time division duplex operating mode). For example, rf front-end control and timeslot control for TDD mode may be implemented inside the FPGA.
In order to enable those skilled in the art to better understand the above steps by TDD and FDD, the following describes an embodiment of the present invention by way of an example, but it should be understood that the embodiment of the present invention is not limited thereto.
As shown in fig. 4, a dual-mode (TDD and FDD) radio frequency transceiver chip is a core device for a dual-mode base transceiver station, and 4 TRX channels, 4 FB channels, and 3 independent local oscillation circuits LO are integrated in the transceiver chip. It is configured for further application of the chip shown in fig. 2, where RX is a receiving channel, TX is a transmitting channel, and FB is a feedback channel.
For the application configuration of the TDD operating mode, the TX1, TX2, RX1, RX2, FB 1-2 channels and the LO1 configuration may be applied to the TDD operating mode, and since the transmit-receive channel and the feedback channel are the same frequency point, the LO1 may be shared. During configuration, the transceiving channel can be configured to be in a normal working state according to an FDD mode, then the frequency points of the transceiving channel and the feedback channel are configured to be the same frequency point, and then the local oscillator circuit LO1 can be commonly adopted. And for the radio frequency front end control and the time slot control in the TDD mode, the control can be realized through an FPGA circuit.
After the dual-mode base station receives a signal, in a TDD operating mode, a local oscillation signal generated by the local oscillation circuit LO1 may be used to perform signal conversion through the receiving channels RX1 and RX2, the transmitting channels TX1 and TX2, and the orthogonal demodulator or the orthogonal modulator in the feedback channels FB 1-2, and the processed signal may be sent to a subsequent device of the processing channel to further process the signal, and may be sent to the UE through the base station.
For the application configuration of the FDD working mode, the TX3, TX4, RX3, RX4, FB3 to 4 channels, the LO2 circuit and the LO3 circuit may be configured to be applied to the FDD working mode, and since the transmission channel and the feedback channel are the same frequency point, the LO3 circuit may be shared, and the frequency point of the reception channel is different from the transmission channel and the feedback channel, and a separate LO2 circuit may be used.
After the dual-mode base station receives a signal, in an FDD operating mode, a local oscillation signal generated by the local oscillation circuit LO2 and the local oscillation circuit LO3 may be used to perform signal conversion through the receiving channels RX3 and RX4, the transmitting channels TX3 and TX4, and the orthogonal demodulator or the orthogonal modulator in the feedback channels FB3 to FB 4, and the processed signal may be sent to a subsequent device of the processing channel to further process the signal, and may be sent to the UE through the base station.
In an example, a transceiver chip may be configured in an FDD mode, and the timeslot control and the radio frequency front end switch control of the TDD mode are implemented by the FPGA, so that a dual-mode operating mode in which 1 transceiver simultaneously supports the TDD mode and the FDD mode may be implemented.
Through the specific internal configuration of the radio frequency transceiver chips aiming at the double modes (TDD and FDD), the 1 transceiver chip can simultaneously support two working modes of TDD and FDD, and compared with a traditional double-mode transceiver built by using two transceiver chips or discrete devices, the area of a board card is reduced, the number of devices is reduced, the power consumption is reduced, and the cost is reduced.
In the embodiment of the invention, the dual-mode base station is provided with a communication chip, the communication chip corresponds to a dual-mode working mode through preset configuration, a plurality of channel information is preset, the corresponding relation between the plurality of channel information and the plurality of working modes is established, then when the dual-mode base station receives and sends signals, first communication data is obtained, a target working mode corresponding to the first communication data is determined, target channel information corresponding to the target working mode is determined, target frequency point information corresponding to the target channel information is further determined, a reference clock provided by a clock circuit aiming at a local oscillator circuit is obtained, the first communication data is processed by adopting the reference clock and the target frequency point information, and second communication data is obtained.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those of skill in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the embodiments of the invention.
Referring to fig. 5, a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention is shown, where the apparatus may be applied to a dual-mode base station, and the dual-mode base station may have a communication chip, and the communication chip may correspond to a dual-mode operating mode through a preset configuration, and specifically includes the following modules:
a correspondence establishing module 501, configured to preset multiple pieces of channel information, and establish a correspondence between the multiple pieces of channel information and the dual-mode working mode;
a target working mode determining module 502, configured to obtain first communication data when the dual-mode base station receives and sends a signal, and determine a target working mode corresponding to the first communication data;
a target channel information determining module 503, configured to determine target channel information corresponding to the target working mode;
a target frequency point information determining module 504, configured to determine target frequency point information corresponding to the target channel information, and process the first communication data by using the target frequency point information to obtain second communication data.
In an embodiment of the present invention, the communication chip is configured with a processing channel and a local oscillation circuit for each operating mode, where each processing channel corresponds to one channel information, and each local oscillation circuit corresponds to one frequency point information.
In an embodiment of the present invention, the communication chip is configured with a clock circuit, and the target frequency point information determining module 504 includes:
providing a reference clock submodule for acquiring a reference clock provided by the clock circuit for the local oscillator circuit;
and the target frequency point information determining submodule is used for processing the first communication data by adopting the reference clock and the target frequency point information to obtain second communication data.
In one embodiment of the present invention, the dual mode operating mode comprises a time division duplex operating mode,
the target channel information determining module 503 includes:
a first target channel information determining submodule, configured to determine first target channel information corresponding to the time division duplex operating mode; the first target channel information comprises first receiving channel information, first transmitting channel information and first feedback channel information;
the target frequency point information determining module 504 includes:
and the first target frequency point information determining submodule is used for determining that the first receiving channel information, the first transmitting channel information and the first feedback channel information correspond to first frequency point information.
In one embodiment of the present invention, the dual mode operating mode comprises a frequency division duplex operating mode,
the target channel information determining module 503 includes:
a second target channel information determining submodule, configured to determine second target channel information corresponding to the frequency division duplex operating mode; the second target channel information comprises second receiving channel information, second transmitting channel information and second feedback channel information;
the target frequency point information determining module 504 includes:
a second target frequency point information determining submodule, configured to determine that the second receiving channel information corresponds to second frequency point information;
and the third target frequency point information determining submodule is used for determining the second transmitting channel information and the second feedback channel information corresponding to third frequency point information.
In an embodiment of the present invention, the communication chip is a zero intermediate frequency transceiver chip.
In an embodiment of the present invention, the apparatus further includes:
and the circuit control module is used for carrying out time slot control and radio frequency front end switch control by adopting a field programmable gate array circuit in the time division duplex working mode.
In the embodiment of the invention, the dual-mode base station is provided with a communication chip, the communication chip corresponds to a dual-mode working mode through preset configuration, a plurality of channel information is preset, the corresponding relation between the plurality of channel information and the dual-mode working mode is established, then when the dual-mode base station receives and sends signals, first communication data is obtained, a target working mode corresponding to the first communication data is determined, target channel information corresponding to the target working mode is determined, further target frequency point information corresponding to the target channel information is determined, the first communication data is processed by adopting the target frequency point information, second communication data is obtained, optimal configuration aiming at the dual-mode base station is realized, and the integration level can be improved, the board card area is reduced, the number of devices is reduced, the power consumption is reduced, and the cost is reduced by adopting the communication chip to correspond to the plurality of working modes.
An embodiment of the present invention also provides an electronic device, which may include a processor, a memory, and a computer program stored on the memory and capable of running on the processor, and when executed by the processor, the computer program implements the steps of the method for processing data as described above.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the above data processing method.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or terminal apparatus that comprises the element.
The method and apparatus for data processing, the electronic device, and the storage medium provided above are introduced in detail, and a specific example is applied in this document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (14)
1. A method for processing data is applied to a dual-mode base station, the dual-mode base station is provided with a communication chip, the communication chip corresponds to a dual-mode working mode through preset configuration, the dual-mode working mode comprises a time division duplex working mode and a frequency division duplex working mode, the communication chip is configured with a processing channel and a local oscillator circuit aiming at each working mode, each processing channel corresponds to channel information, and each local oscillator circuit corresponds to frequency point information, and the method comprises the following steps:
presetting a plurality of channel information, and establishing a corresponding relation between the plurality of channel information and the dual-mode working mode;
when the dual-mode base station receives and sends signals, first communication data are obtained, and a target working mode corresponding to the first communication data is determined;
determining target channel information corresponding to the target working mode;
and determining target frequency point information corresponding to the target channel information, and processing the first communication data by adopting the target frequency point information to obtain second communication data.
2. The method according to claim 1, wherein the communication chip is configured with a clock circuit, and the step of processing the first communication data by using the target frequency point information to obtain the second communication data comprises:
acquiring a reference clock provided by the clock circuit aiming at the local oscillator circuit;
and processing the first communication data by adopting the reference clock and the target frequency point information to obtain second communication data.
3. The method according to claim 1 or 2, wherein the step of determining the target channel information corresponding to the target operating mode comprises:
determining first target channel information corresponding to the time division duplex working mode; the first target channel information comprises first receiving channel information, first transmitting channel information and first feedback channel information;
the step of determining the target frequency point information corresponding to the target channel information comprises the following steps:
and determining that the first receiving channel information, the first transmitting channel information and the first feedback channel information correspond to first frequency point information.
4. The method according to claim 1, wherein the step of determining the target channel information corresponding to the target operating mode comprises:
determining second target channel information corresponding to the frequency division duplex working mode; the second target channel information comprises second receiving channel information, second transmitting channel information and second feedback channel information;
the step of determining the target frequency point information corresponding to the target channel information comprises:
determining that the second receiving channel information corresponds to second frequency point information;
and determining that the second transmitting channel information and the second feedback channel information correspond to third frequency point information.
5. The method of claim 1, wherein the communication chip is a zero intermediate frequency radio transceiver chip.
6. The method of claim 3, further comprising:
and under the time division duplex working mode, a field programmable gate array circuit is adopted for time slot control and radio frequency front end switch control.
7. A data processing device is applied to a dual-mode base station, the dual-mode base station is provided with a communication chip, the communication chip corresponds to a dual-mode working mode through preset configuration, the dual-mode working mode comprises a time division duplex working mode and a frequency division duplex working mode, the communication chip is configured with a processing channel and a local oscillator circuit aiming at each working mode, each processing channel corresponds to channel information, and each local oscillator circuit corresponds to frequency point information, and the data processing device comprises:
the corresponding relation establishing module is used for presetting a plurality of channel information and establishing the corresponding relation between the plurality of channel information and the dual-mode working mode;
a target working mode determining module, configured to obtain first communication data when the dual-mode base station receives and sends a signal, and determine a target working mode corresponding to the first communication data;
the target channel information determining module is used for determining target channel information corresponding to the target working mode;
and the target frequency point information determining module is used for determining target frequency point information corresponding to the target channel information, and processing the first communication data by adopting the target frequency point information to obtain second communication data.
8. The device according to claim 7, wherein the communication chip is configured with a clock circuit, and the target frequency point information determining module includes:
providing a reference clock submodule for acquiring a reference clock provided by the clock circuit for the local oscillator circuit;
and the target frequency point information determining submodule is used for processing the first communication data by adopting the reference clock and the target frequency point information to obtain second communication data.
9. The apparatus of claim 7 or 8, wherein the target channel information determining module comprises:
a first target channel information determining submodule, configured to determine first target channel information corresponding to the time division duplex operating mode; the first target channel information comprises first receiving channel information, first transmitting channel information and first feedback channel information;
the target frequency point information determining module comprises:
and the first target frequency point information determining submodule is used for determining that the first receiving channel information, the first transmitting channel information and the first feedback channel information correspond to first frequency point information.
10. The apparatus of claim 7, wherein the target channel information determining module comprises:
a second target channel information determining submodule, configured to determine second target channel information corresponding to the fdd working mode; the second target channel information comprises second receiving channel information, second transmitting channel information and second feedback channel information;
the target frequency point information determining module comprises:
a second target frequency point information determining submodule, configured to determine that the second receiving channel information corresponds to second frequency point information;
and the third target frequency point information determining submodule is used for determining the second transmitting channel information and the second feedback channel information corresponding to third frequency point information.
11. The apparatus of claim 7, wherein the communication chip is a zero intermediate frequency radio transceiver chip.
12. The apparatus of claim 9, further comprising:
and the circuit control module is used for carrying out time slot control and radio frequency front end switch control by adopting a field programmable gate array circuit in the time division duplex working mode.
13. An electronic device, comprising a processor, a memory and a computer program stored on the memory and capable of running on the processor, the computer program, when executed by the processor, implementing the steps of the method of data processing according to any one of claims 1 to 6.
14. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of a method of data processing according to any one of claims 1 to 6.
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