CN114665872B - Analog time delay alignment device and method based on phase discriminator and charge pump - Google Patents

Abstract

The purpose of the present invention is to provide an analog delay alignment device and method based on a phase detector and a charge pump, which belongs to the field of communication technology. The present invention takes the phase detector and the charge pump as the core, and realizes the delay alignment of multi-channel analog signals through the feedback loop, specifically: the two-way differential limiter signal is input to the phase detection module, and the phase detection module takes out two signals through the D flip-flop. The phase difference of the two-way signal, the phase detection module stops the phase detection function after the phase detection is completed; then, the high level obtained after the phase detection is transmitted to the charge pump unit, and the two current signals are combined in the charge pump unit; the current signal passes through The low-pass filter filters and integrates to a certain voltage range; the logic judgment unit judges the access state of the delay module according to the voltage signal; finally, the delay module realizes a certain delay and feeds back to the input terminal to realize dynamic balance. Compared with digital time delay alignment, it can avoid the complex down-conversion technology of digital time delay alignment, and can better suppress errors caused by temperature drift of radio frequency signals.

Description

An analog delay alignment device and method based on a phase detector and a charge pump

technical field

The invention belongs to the technical field of communication, and in particular relates to an analog delay alignment device and method based on a phase detector and a charge pump.

Background technique

In a communication system, there is always a time delay after the output signal is processed by detection, amplification, filtering, etc., and the time delay of the signal will cause the phase difference of the two signals; especially when the power amplifier is used for digital pre-distortion, it is necessary to collect input and The output data is correlated. If the signal is delayed, the collected data will not correspond, which will bring extremely large errors to the pre-distortion stage.

Since there is always a time delay after the signal passes through the circuit, it is of great application value and engineering significance to realize the delay alignment in the communication system. In specific engineering applications, most solutions are realized through "digital delay alignment". For example, in the uplink transmitter, "digital alignment" first down-converts the signal output by the power amplifier, then converts it into a digital signal, and finally uses an algorithm for alignment ; but as the frequency of the signal increases from IF to RF, digital predistortion is difficult to overcome the influence of temperature drift, and the manufacturing cost and circuit structure gradually become more expensive and complicated as the frequency increases (Peng Jun. Multiband Research on Linearization Technology of RF Transmitter [D]. University of Electronic Science and Technology of China, 2019.). At present, some scholars have conducted in-depth research on "analog delay alignment". Commonly used analog delay alignment methods include switched transmission line networks, switched LC networks, and all-pass filter structures. The former two can provide a larger delay range, but The larger circuit design area is not conducive to integration; the latter has a larger delay range and an integrated circuit structure, but generates greater power consumption (E.Zolkov, R.Weiss, A.Madjar and E.Cohen, " A Low Power Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving2ps Delay Resolution," 2020 15th European Microwave Integrated Circuits Conference (EuMIC), 2021, pp.197-200.).

Therefore, how to design an analog delay alignment device so that it can provide a large delay range while having the advantages of low cost, small size, simple structure, and low power consumption has become a research hotspot.

Contents of the invention

In view of the problems existing in the background technology, the object of the present invention is to provide an analog delay alignment device and method based on a phase detector and a charge pump. The invention takes the phase detector and the charge pump as the core, realizes the time delay alignment of multi-channel analog signals through the feedback loop, and lays the foundation for the subsequent signal processing; compared with the digital time delay alignment, it can avoid the complex downside of the digital time delay alignment Frequency conversion technology can better suppress the error caused by the temperature drift of the radio frequency signal. At the same time, the technical solution of the present invention has a certain degree of universality, and is not only applicable to the time delay alignment of radio frequency power amplifiers, but also suitable for time delay alignment of other circuits such as antenna arrays and radar signals.

To achieve the above object, the technical scheme of the present invention is as follows:

An analog delay alignment device based on a phase detector and a charge pump, including a signal input module, a phase detector module, a charge pump module, a filter, a logic judgment module and a delay module;

The signal input module is used to limit the two input signals, and then input them to the phase detection module;

The phase detection module includes a phase detection unit and a control unit; the phase detection unit is composed of two clocked D flip-flops, and each clocked D flip-flop extracts two-way limiter input signals from the rising edge to the two-way signal The time difference when rising to a high level at the same time, the time difference corresponds to the duty cycle of the high or low level maintenance after the circuit is combined, and the duty cycle is related to the amount of time delay; the control unit is used to control the phase detection unit to stop the phase detection;

The charge pump module includes an attenuator, a charge pump and a combiner; the attenuator is used to attenuate the voltage signal output by the phase detector module to a certain amplitude, and the charge pump is used to convert the attenuated voltage signal into a current signal, and the combiner The device is used to combine two current signals into one current signal;

The filter is used to filter the harmonics and noise of the current signal output by the charge pump module, and integrate the current signal to convert it into a voltage signal;

The logic judgment module is used to detect the amplitude of the voltage signal filtered by the filter, and judge which signal is delayed and the amount of delay based on the amplitude value;

The delay module includes a multi-port selection switch and a delay unit, and the delay unit is composed of m transistors; the multi-port selection switch selects the number of transistors that turn on the access circuit according to the result of the logic decision module, and performs signal The selection of the delay amount, and then the feedback of the delay amount acts on the input signal, so as to complete the delay alignment.

Further, the control unit is used to control the phase detection unit to stop the phase detection, including normal stop phase detection and abnormal stop phase detection; the normal stop phase detection is realized by a NAND gate, when the control unit detects that the two signals are simultaneously high Turn off the clocked D flip-flop at ordinary times; abnormal stop phase detection includes XOR gate, XNOR gate and NAND gate, and turn off the clocked D flip-flop when the control unit judges that there is an error in the input signal.

Further, the attenuator includes a forward attenuator and a reverse attenuator; after the forward attenuator is attenuated by K times, the charge pump is charged, and the voltage is positive; the reverse attenuator is attenuated by -K times, and the charge pump discharges, and the voltage is negative.

Further, if the output current of the charge pump is positive, it means that one input signal is leading, and if the output current of the charge pump is negative, it means that the other input signal is leading.

Further, the filter is a passive low-pass filter.

Further, the multi-port selection switch has a total of m+2 channels, and the first input channel is a control input terminal, which is used to select the number of transistors connected to the system by the delay unit; the last channel is grounded, and the remaining m channels is a data input terminal; the data input terminal is connected to m transistors.

Further, m≥8.

A kind of time delay alignment method based on phase detector and charge pump simulation, comprises the following steps:

Step 1. After performing limiting and differential processing on the two input signals, extract the phase difference of the two signals;

Step 2. Obtain the time delay result based on the phase difference, and then convert the time delay signal into a voltage signal;

Step 3. After filtering the voltage signal obtained in step 2, determine the delay amount, and then determine which signal to perform delay compensation processing according to the delay amount.

In summary, owing to adopting above-mentioned technical scheme, the beneficial effect of the present invention is:

1. The phase detection module proposed by the present invention records the lead or lag time of different road signals through the high level of the D flip-flop, that is, from the rising edge to the time when both roads are high level, and then the high level The signal is transmitted to the charge pump and the logic judgment unit; the time delay of the analog signal is converted into a voltage signal, which is simple and responsive.

2. The phase detection control module proposed by the present invention can not only save power consumption when the phase detector is turned off immediately under normal conditions, but also eliminate several error signals, greatly improving the accuracy of analog delay alignment.

3. The logical judgment module proposed by the present invention uses logical judgment to convert the voltage signal into a specific delay amount, and then selects the amount of time to be compensated by the delay unit through a multi-port selection switch, and then feeds back to the input terminal to achieve dynamic balance and operate Simple and low cost.

Description of drawings

FIG. 1 is an overall block diagram of an analog delay alignment device of the present invention.

FIG. 2 is a structural block diagram of a phase detector module in Embodiment 1 of the present invention.

FIG. 3 is a timing diagram of normal operation of the phase detector module in Embodiment 1 of the present invention.

FIG. 4 is a timing diagram of the operation of the phase detector module in Embodiment 1 of the present invention when two types of errors occur.

Fig. 5 is a logic block diagram of a logic judgment module in Embodiment 1 of the present invention.

FIG. 6 is an example diagram of two input signals in Embodiment 1 of the present invention.

FIG. 7 is an example diagram of a time delay alignment result of two input signals in Embodiment 1 of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the implementation methods and accompanying drawings.

An analog delay alignment device based on a phase detector and a charge pump, including a signal input module, a phase detector module, a charge pump module, a filter, a logic judgment module and a delay module;

The signal input module is used to limit the two input signals, and then input them to the phase detection module; the main component of the signal input module is a limiter, and the limiter is a differential input mode, and the signal is differentially amplified and then limited. amplitude output

The phase detection module includes a phase detection unit and a control unit; the phase detection unit is composed of two clocked D flip-flops, and each clocked D flip-flop extracts two-way limit input signals from the rising edge to the two-way Simultaneously rising to the time between the high-level moments, that is, to extract the phase difference of the two signals, the time difference corresponds to the duty ratio of the high or low level maintenance after the combination, and the duty ratio is related to the amount of delay; the control The unit is used to control the phase detection unit to stop phase detection, including normal stop of phase detection and abnormal stop of phase detection;

The charge pump module includes an attenuator, a charge pump and a combiner; the attenuator is used to attenuate the high-amplitude voltage signal output by the phase detector module to a certain amplitude; the charge pump is used to convert the attenuated voltage signal into a detectable The current signal of the current signal, and distinguish the role of a certain signal leading or lagging the signal through the positive and negative of the current signal; the combiner is used to combine the two current signals into one current signal, and realize the conversion of "time-delayed signal" into "current signal" ;

The filter module is a low-pass filter composed of resistors and capacitors, which is used to filter out the harmonics and noise in the current signal output by the charge pump module, and integrate the current signal to convert it into a voltage signal;

The logic judgment module is used to detect the amplitude of the voltage signal filtered by the filter, and judge which signal delay and delay amount based on the amplitude value, and select the conduction condition of the multi-port switch;

The delay module includes a multi-port selector switch and a delay unit, each delay unit is composed of m transistors, and the delay module is used to convert the "voltage signal" into a "delay signal"; the multi-port selector switch is used Based on the selection of the number of transistors that are turned on and connected to the circuit according to the results of the logic decision module, the signal delay amount is selected, and the delay amount is fed back to the input signal, so that the delay alignment system achieves a dynamic balance.

At the beginning, the delay module did not work, and the two differential limiter signals were input to the phase detection module, and the phase detection module took out the phase difference of the two signals through the D flip-flop, and the phase detection module stopped the phase detection function after the phase detection was completed. ; Then, the high level obtained after phase discrimination is transmitted to the charge pump unit, and the two current signals are combined in the charge pump unit; then, the current signal is filtered by a low-pass filter and integrated to a certain voltage range; secondly, the logic judgment The unit judges the connection state of the delay module according to the voltage signal; finally, the delay module realizes a certain delay and feeds back to the input terminal to realize dynamic balance.

Example 1

When there are two analog input signals, one is the first detection signal and the other is the second detection signal. The overall implementation block diagram of the analog delay alignment device of the present invention is shown in FIG. 1 .

The input module performs differential amplification on the two detection signals. The differential amplification can effectively amplify the differential mode signal and suppress the common mode signal, which reduces the noise caused by factors such as temperature drift and voltage instability to a certain extent. After the differential amplification of the two signals, , the signal is smaller than E, the limiter is turned on, and the signal is greater than E, the limiter is not turned on; the limited signal is input to the phase detector module.

The phase detector module includes a phase detector unit and a control unit. The structure flow chart of this module is shown in Figure 2. The phase detection unit is composed of two clocked D flip-flops. The input terminal of the clocked D flip-flop is always set to high level, and the limited signal is input to the CLK end of the D flip-flop. When the rising edge of the limiter output signal comes , the D flip-flop outputs a high level, and according to the time difference between the high levels of the two signals, the phase difference between the two signals is obtained after the combination. At this time, the specific working sequence of the phase detector is shown in Figure 3, where V ₁ is the detection signal, V ₂ is the reference signal, V' ₁ is the output signal of the first D flip-flop, and V' ₂ is the second output signal. D flip-flop output signal. The control unit closes the D flip-flop when it detects that the output of the two D flip-flops is at a high level at the same time; in addition, when the input signal has Type 2 errors, it also turns off the D flip-flop in time. When the first type of error occurs, the working sequence of the phase detection module is shown in (a) in Figure 4; when the second type of error occurs, the working sequence of the phase detection module is shown in Figure 4 (b). According to the timing diagram, the situation of error can be summarized as that the levels of V ₁ and V ₂ are the same, and the levels of V' ₁ and V' ₂ are different. Therefore, V ₁ and V ₂ are connected to an XNOR gate at the same time, Connect V' ₁ and V' ₂ to the XOR gate at the same time to achieve the purpose of avoiding the impact of error signals on the delay alignment.

The charge pump module, the principle of the charge pump is to use the charge and discharge of the capacitor to realize the charge transfer. Before the two-way voltage signal output by the phase detector module officially enters the charge pump, it is first attenuated to a certain amplitude by the attenuator, and then converted into a current signal by the charge pump unit, and finally the two-way signals are merged into the combiner to detect the combined circuit. The output current of the device is positive or negative, and judges the lead or lag of the detection signal according to the positive or negative.

The filter module, preferably a second-order passive filter, is used to filter out the residual noise and interference of the previous stage, and has the following three functions: one is that the signal output by the charge pump may jitter, and the signal can be processed by the filter Smoother; the second is the integral effect, the longer the charge pump output voltage lasts, the larger the integral amplitude; the third is to filter out the "inconsistent" error of the two channels, because the temperature drift, thermal noise and structure of the two detection signal channels may be inconsistent, So there may be such errors. In addition, the second-order passive filter is only composed of two capacitors and one resistor, which has a simple structure and low cost, and does not need to introduce other active devices.

The specific logic judgment flow chart of the logic judgment module is shown in Fig. 5 . Because the amplitude corresponds to the corresponding delay, the logic judgment unit judges the channel that the multi-port selection switch conducts by detecting the amplitude of the voltage signal integrated by the low-pass filter. The logic judgment unit is followed by two multi-port selection switches, and the selection switch is followed by two delay units, which respectively feed back to the two detection signal input terminals. The multi-port selection switch has a total of 10 channels, of which channel 10 is the control The input terminal, 1 channel is ground, and the other channels are data input terminals. The detected voltage signal is U, the logic judges that the minimum voltage scale is K, and the channel Y of the selection switch is Y1, Y2, Y3, Y4..., the specific implementation logic is as follows: if the detected voltage signal U>0, open channel 2, If U<1k, then Y2=1, otherwise judge whether U is less than 2k, and then recursively step by step and the value of U is within 8k; if the detected voltage signal U<0, open channel 1, if U>-1k, then Y1 = 1, otherwise judge whether U is greater than -2k, recursively step by step and the value of U is within -8k.

The delay module is composed of a multi-port selection switch and a delay unit. If the voltage signal input to the delay alignment module is greater than 0, it means that the first detection signal is ahead of the second detection signal, and the upper channel selection switch is set to the input signal state; if The voltage signal input to the delay alignment module is less than 0, indicating that the first detection signal lags behind the second detection signal, and the drop selection switch is set to the input signal state. The result generated by the logic judge will determine the number of transistors in the delay unit connected to the circuit, introduce a delay amount, and achieve delay alignment.

Example 2

When applied to the time delay alignment scheme of the power amplifier, when two signals, one is a reference signal and the other is a detection signal, only one delay module is needed, and the U value detected by the logic judgment module is always greater than 0.

For Example 1, the Matlab2018 simulation platform is used to verify the technical solution. The comparison between the input original signal and the simulated delay alignment signal of the present invention is shown in Figure 6 and Figure 7 . It can be seen from the figure that there is a certain delay between the two input signals, and the delay amount is 3ms; after the device of the present invention performs an analog delay alignment operation, the alignment of the two signals can be completed.

The above is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless specifically stated, can be replaced by other equivalent or alternative features with similar purposes; all the disclosed features, or All method or process steps may be combined in any way, except for mutually exclusive features and/or steps.

Claims (8)

1. An analog time delay alignment device based on a phase discriminator and a charge pump is characterized by comprising a signal input module, a phase discriminator module, a charge pump module, a filter, a logic decision module and a time delay module;

the signal input module is used for carrying out amplitude limiting processing on the two paths of input signals and then inputting the two paths of input signals to the phase discrimination module;

the phase discrimination module comprises a phase discrimination unit and a control unit; the phase discrimination unit consists of two clock-controlled D triggers, each clock-controlled D trigger extracts the time difference from the beginning of the rising edge of two amplitude limiting input signals to the time when the two signals simultaneously rise to a high level, and the time difference corresponds to the duty ratio maintained by the high or low level after the combination; the control unit is used for controlling the phase discrimination unit to stop phase discrimination;

the charge pump module comprises an attenuator, a charge pump and a combiner; the attenuator is used for attenuating the voltage signal output by the phase discrimination module to a certain amplitude, the charge pump is used for converting the attenuated voltage signal into a current signal, and the combiner is used for combining two paths of current signals into one path of current signal;

the filter is used for filtering harmonic waves and noise of current signals output by the charge pump module, integrating the current signals and converting the current signals into voltage signals;

the logic judgment module is used for detecting the amplitude of the voltage signal filtered by the filter and judging which path of signal is delayed and delayed based on the amplitude value;

the delay module comprises a multi-port selection switch and a delay unit, wherein the delay unit consists of m transistors; the multiport selection switch selects the number of the transistors which are connected with the access circuit according to the result of the logic judgment module, selects the signal delay amount, and feeds back the delay amount to the input signal, thereby completing delay alignment.

2. The analog delay alignment device of claim 1, wherein the control unit is configured to control the phase detection unit to stop phase detection, including normal stop phase detection and abnormal stop phase detection; the normal stop phase demodulation is realized through a NAND gate, and when the control unit detects that two paths of signals are high level at the same time, the clock control D trigger is closed; the abnormal stop phase detection comprises an exclusive-OR gate, an exclusive-NOR gate and a NAND gate, and the clocked D flip-flop is closed when the control unit judges that the input signal has an error.

3. The analog delay alignment device of claim 1, wherein the attenuator comprises a forward attenuator and a reverse attenuator; after the attenuation of the forward attenuator is K times, the charge pump is charged, and the voltage is positive; the attenuation of the reverse attenuator is-K times, the charge pump discharges, and the voltage is negative.

4. The analog delay alignment device of claim 1, wherein a positive charge pump output current indicates a lead in one input signal and a negative charge pump output current indicates a lead in the other input signal.

5. The analog delay alignment device of claim 1, wherein the filter is a passive low pass filter.

6. The analog delay alignment device of claim 1, wherein the multi-port selector switch has m +2 channels, the first input channel being a control input for selecting the number of transistors of the delay cell that are connected to the system; the last channel is grounded, and the other m channels are data input ends; the data input terminal is connected with the m transistors.

7. The analog delay alignment device of claim 6, wherein m ≧ 8.

8. A method for aligning analog delay based on the analog delay aligning device of any one of claims 1 to 7, comprising the steps of:

step 1, after amplitude limiting differential processing is carried out on two paths of input signals, phase difference of the two paths of signals is extracted;

step 2, obtaining a time delay result based on the phase difference, and then converting the time delay signal into a voltage signal;

and 3, filtering the voltage signal obtained in the step 2, judging the delay amount, and judging which path of signal is subjected to delay compensation processing according to the delay amount.

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