CN114665872B - Analog time delay alignment device and method based on phase discriminator and charge pump - Google Patents
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Abstract
The invention aims to provide a device and a method for simulating time delay alignment based on a phase discriminator and a charge pump, belonging to the technical field of communication. The invention takes a phase discriminator and a charge pump as cores, realizes the time delay alignment of a plurality of paths of analog signals through a feedback loop, and specifically comprises the following steps: the two paths of differential amplitude limiting signals are input to a phase discrimination module, the phase discrimination module extracts the phase difference of the two paths of signals through a D trigger, and the phase discrimination module stops the phase discrimination function after the phase discrimination is finished; then, the high level obtained after phase discrimination is transmitted to a charge pump unit, and two paths of current signals are combined in the charge pump unit; filtering and integrating the current signal to a certain voltage amplitude through a low-pass filter; the logic judgment unit judges the access state of the delay module according to the voltage signal; and finally, the delay module realizes certain delay and feeds the delay back to the input end to realize dynamic balance. Compared with digital time delay alignment, the method can avoid a down-conversion technology with complex digital time delay alignment and can better inhibit errors caused by temperature drift of the radio-frequency signals.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a device and a method for aligning analog time delay based on a phase discriminator and a charge pump.
Background
In a communication system, time delay always exists after output signals are subjected to detection, amplification, filtering and other processing, and the time delay of the signals can cause phase difference of two paths of signals; especially, when the power amplifier performs digital pre-distortion, input and output data need to be collected for correlation, and if the signal is delayed, the collected data will not correspond to each other, which brings a very large error to pre-distortion of a preceding stage.
Because time delay always exists after signals pass through the circuit, the realization of delay alignment in a communication system has important application value and engineering significance. In specific engineering application, most schemes are realized through digital delay alignment, for example, in an uplink transmitter, the digital alignment firstly carries out down-conversion on signals output by a power amplifier, then the signals are converted into digital signals, and finally, the alignment is carried out by utilizing an algorithm; however, as the frequency of the signal increases from the intermediate frequency to the radio frequency, the digital predistortion is difficult to overcome the influence of temperature drift, and the manufacturing cost and the circuit structure become more and more expensive and complicated with the increase of the frequency (Peng Jun. Multi-band radio frequency transmitter linearization technology research [ D ]. University of electronic technology, 2019.). At present, some scholars deeply research on analog delay alignment, and common analog delay alignment methods comprise a switch transmission line network, a switch LC network, an all-pass filter structure and the like, wherein the switch transmission line network, the switch LC network, the all-pass filter structure and the like can provide a larger delay range, but the circuit design area is larger, so that the integration is not facilitated; the latter has a larger Delay range and an integratable Circuit structure, but generates a larger power Consumption (E.Zolkov, R.Weiss, A.Madjar and E.Cohen, "A Low Powe Consumption 65-nm CMOS True Time Delay N-path Circuit Achieving 2ps Delay resolution," 2020 1 th European Microwave Integrated Circuits Conference (EuMIC), 2021, pp.197-200.).
Therefore, how to design the analog delay alignment device to provide a larger delay range and have the advantages of low cost, small volume, simple structure, low power consumption and the like becomes a research hotspot.
Disclosure of Invention
In view of the problems in the background art, an object of the present invention is to provide an analog delay alignment apparatus and method based on a phase detector and a charge pump. The phase discriminator and the charge pump are taken as cores, and the time delay alignment of the multi-channel analog signals is realized through the feedback loop, so that the foundation is laid for the subsequent signal processing; compared with digital time delay alignment, the method can avoid a down-conversion technology with complex digital time delay alignment and can better inhibit errors caused by temperature drift of the radio-frequency signals. Meanwhile, the technical scheme of the invention has certain universality, is not only suitable for time delay alignment of the radio frequency power amplifier, but also suitable for time delay alignment of other circuits such as an antenna array, a radar signal and the like.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a simulation time delay alignment device based on a phase discriminator and a charge pump comprises a signal input module, a phase discrimination module, a charge pump module, a filter, a logic judgment module and a time delay module;
the signal input module is used for carrying out amplitude limiting processing on the two paths of input signals and then inputting the two paths of input signals to the phase discrimination module;
the phase discrimination module comprises a phase discrimination unit and a control unit; the phase demodulation unit consists of two clock-controlled D triggers, each clock-controlled D trigger extracts the time difference from the beginning of the rising edge of two amplitude limiting input signals to the time when the two signals simultaneously rise to high level, the time difference corresponds to the duty ratio maintained by the high or low level after the combination, and the duty ratio is related to the time delay amount; the control unit is used for controlling the phase discrimination unit to stop phase discrimination;
the charge pump module comprises an attenuator, a charge pump and a combiner; the attenuator is used for attenuating the voltage signal output by the phase discrimination module to a certain amplitude, the charge pump is used for converting the attenuated voltage signal into a current signal, and the combiner is used for combining two paths of current signals into one path of current signal;
the filter is used for filtering harmonic waves and noise of current signals output by the charge pump module, integrating the current signals and converting the current signals into voltage signals;
the logic judgment module is used for detecting the amplitude of the voltage signal filtered by the filter and judging which path of signal is delayed and delayed based on the amplitude value;
the delay module comprises a multi-port selection switch and a delay unit, wherein the delay unit consists of m transistors; the multi-port selection switch selects the number of transistors for switching on the access circuit according to the result of the logic decision module, selects the signal delay amount, and feeds back the delay amount to the input signal, thereby completing delay alignment.
Furthermore, the control unit is used for controlling the phase discrimination unit to stop phase discrimination, and the phase discrimination unit comprises a normal stop phase discrimination unit and an abnormal stop phase discrimination unit; the normal stop phase discrimination is realized by a NAND gate, and the clock-controlled D trigger is closed when the control unit detects that two paths of signals are high level simultaneously; the abnormal stop phase detection comprises an exclusive-OR gate, an exclusive-NOR gate and a NAND gate, and the clock control D trigger is closed when the control unit judges that the input signal has errors.
Further, the attenuator comprises a forward attenuator and a reverse attenuator; after the attenuation of the forward attenuator is K times, the charge pump is charged, and the voltage is positive; the attenuation of the reverse attenuator is-K times, the charge pump discharges, and the voltage is negative.
Furthermore, the output current of the charge pump is positive to represent that one input signal leads, and the output current of the charge pump is negative to represent that the other input signal leads.
Further, the filter is a passive low pass filter.
Furthermore, the multi-port selection switch has m +2 channels, and the first input channel is a control input end and is used for selecting the number of transistors of the delay unit access system; the last channel is grounded, and the other m channels are data input ends; the data input terminal is connected with the m transistors.
Further, m is more than or equal to 8.
A phase discriminator and charge pump based analog time delay alignment method comprises the following steps:
and 3, filtering the voltage signal obtained in the step 2, judging the delay amount, and judging which path of signal is subjected to delay compensation processing according to the delay amount.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. the phase discrimination module records the lead time or lag time of different paths of signals through the high level of the D trigger, namely the time from the rising edge to the time when two paths of signals are both high levels, and then transmits the high level signals to the charge pump and the logic judgment unit; the time delay of the analog signal is converted into the voltage signal, the realization is simple, and the response is sensitive.
2. The phase discrimination control module provided by the invention not only can save power consumption when the phase discriminator is immediately closed under normal conditions, but also can eliminate a plurality of error signals, thereby greatly improving the accuracy of analog delay alignment.
3. The logic judgment module provided by the invention converts the voltage signal into a specific time delay amount by using logic judgment, then selects the time amount to be compensated by the time delay unit through the multi-port selection switch, and feeds the time amount back to the input end, so that dynamic balance is achieved, the operation is simple and convenient, and the cost is low.
Drawings
Fig. 1 is a general block diagram of the analog delay alignment apparatus of the present invention.
Fig. 2 is a block diagram of a phase detector module in embodiment 1 of the present invention.
Fig. 3 is a timing diagram illustrating normal operation of a phase detector module in embodiment 1 of the present invention.
Fig. 4 is a timing diagram of an operation of the phase detector module in embodiment 1 of the present invention when two types of errors occur.
Fig. 5 is a logic block diagram of a logic determination module in embodiment 1 of the present invention.
Fig. 6 is an exemplary diagram of two input signals in embodiment 1 of the present invention.
Fig. 7 is an exemplary diagram of the two input signal delay alignment results in embodiment 1 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings.
A simulation time delay alignment device based on a phase discriminator and a charge pump comprises a signal input module, a phase discrimination module, a charge pump module, a filter, a logic judgment module and a time delay module;
the signal input module is used for carrying out amplitude limiting processing on the two paths of input signals and then inputting the two paths of input signals to the phase discrimination module; the signal input module mainly comprises an amplitude limiter which is in a differential input mode and is used for carrying out differential amplification on signals and then outputting the signals after amplitude limiting
The phase demodulation module comprises a phase demodulation unit and a control unit; the phase demodulation unit consists of two clock-controlled D triggers, each clock-controlled D trigger extracts the time from the arrival time of the rising edge of two amplitude-limiting input signals to the time when the two amplitude-limiting input signals simultaneously rise to high level, namely extracts the phase difference of the two signals, the time difference corresponds to the duty ratio maintained by high or low level after the combination, and the duty ratio is related to the time delay; the control unit is used for controlling the phase discrimination unit to stop phase discrimination, and the phase discrimination unit comprises a normal stop phase discrimination unit and an abnormal stop phase discrimination unit;
the charge pump module comprises an attenuator, a charge pump and a combiner; the attenuator is used for attenuating the high-amplitude voltage signal output by the phase discriminator module to a certain amplitude; the charge pump is used for converting the attenuated voltage signal into a detectable current signal and distinguishing the effect of a leading signal or a lagging signal of a certain path of signal through the positive and negative of the current signal; the combiner is used for combining the two paths of current signals into one path of current signal to convert the time delay signal into a current signal;
the filter module is a low-pass filter consisting of a resistor and a capacitor and is used for filtering harmonic waves and noise existing in a current signal output by the charge pump module, integrating the current signal and converting the current signal into a voltage signal;
the logic judgment module is used for detecting the amplitude of the voltage signal filtered by the filter, judging which path of signal is delayed and the delay amount based on the amplitude value, and selecting the conduction condition of the multi-port switch;
the delay module comprises a multi-port selection switch and delay units, each delay unit consists of m transistors, and the delay module is used for converting a voltage signal into a delay signal; the multi-port selection switch is used for selecting the number of the transistors which are connected with the access circuit to select the signal delay amount according to the result of the logic decision module, and feeding back the delay amount to act on the input signal, so that the delay alignment system achieves dynamic balance.
When the phase discrimination system starts, the delay module does not act, the two paths of differential amplitude limiting signals are input to the phase discrimination module, the phase discrimination module extracts the phase difference of the two paths of signals through the D trigger, and the phase discrimination module stops the phase discrimination function after the phase discrimination is finished; then, the high level obtained after phase discrimination is transmitted to a charge pump unit, and two paths of current signals are combined in the charge pump unit; then, the current signal is filtered by a low-pass filter and integrated to a certain voltage amplitude; secondly, the logic judgment unit judges the access state of the delay module according to the voltage signal; and finally, the delay module realizes certain delay and feeds the delay back to the input end to realize dynamic balance.
Example 1
When the analog input signal is 2 paths, one path is the first detection signal, and the other path is the second detection signal, the general implementation block diagram of the analog delay alignment device of the present invention is shown in fig. 1.
The input module carries out differential amplification on the two paths of detection signals, the differential amplification can effectively amplify differential mode signals and inhibit common mode signals, and noise caused by factors such as temperature drift, voltage instability and the like is reduced to a certain extent; after the two paths of signals are differentially amplified, the signal is smaller than the conduction of the E amplitude limiter, and the signal is larger than the conduction of the E amplitude limiter; and inputting the signal after amplitude limiting to a phase discriminator module.
The phase discriminator module comprises a phase discriminating unit and a control unit, and the structural flow chart of the module is shown in figure 2. The phase discrimination unit is composed of two paths of clock-controlled D triggers, the input end of the clock-controlled D trigger is always set to be a high level, the signal after amplitude limiting is input to the CLK end of the D trigger, when the rising edge of the output signal of the amplitude limiter arrives, the D trigger outputs the high level, and the phase difference of the two signals is obtained after the combination according to the time difference maintained by the high levels of the two paths of signals. At this time, the specific operation timing sequence of the phase detector is shown in fig. 3, where V is 1 For detecting signal, V 2 Is a reference signal, V' 1 Is the first D flip-flop outputs a signal V' 2 And outputting signals for the second D trigger. The control unit is used for closing the D triggers when detecting that the outputs of the two paths of D triggers are high levels at the same time; in addition, when the input signal has 2 types of errors, the D flip-flop is also closed in time. When the first type of error occurs, the working time sequence of the phase detection module is shown as (a) in fig. 4; when the second type of error occurs, the operation timing of the phase detection module is shown as (b) in fig. 4. From the timing chart, the occurrence of an error can be summarized as V 1 And V 2 Are of the same level, V' 1 And V' 2 Is different, then V is 1 And V 2 Simultaneously connecting an exclusive NOR gate and V' 1 And V' 2 And meanwhile, the exclusive-OR gate is accessed, so that the aim of avoiding the influence of error signals on time delay alignment is fulfilled.
The charge pump module adopts the principle that charge and discharge of a capacitor are utilized to realize charge transfer. Before two paths of voltage signals output by the phase discriminator module formally enter a charge pump, the voltage signals are attenuated to a certain amplitude through an attenuator, then the voltage signals are converted into current signals through a charge pump unit, finally the two paths of signals are converged into a combiner, the positive and negative of the output current of the combiner are detected, and the lead or lag of the detection signals is judged according to the positive and negative.
The filter module, preferably a second-order passive filter, is used for filtering the preceding-stage residual noise and interference, and has the following three functions: firstly, the signal output by the charge pump may have jitter, and the signal can be processed to be smoother by using a filter; secondly, the integration function is realized, and the longer the output voltage time of the charge pump is, the larger the integration amplitude is; and thirdly, filtering out the 'inconsistency' error of the two channels, wherein the error may exist because the temperature drift, the thermal noise and the structure of the two detection signal channels may be inconsistent. In addition, the second-order passive filter is composed of only two capacitors and one resistor, is simple in structure and low in cost, and does not need to introduce other active devices.
Fig. 5 is a block diagram of a specific logic judgment flow of the logic decision module. Because the amplitude corresponds to the corresponding delay amount, the logic judgment unit judges the channel which is conducted by the multiport selection switch by detecting the amplitude of the voltage signal after the low-pass filter integrates. The logic judgment unit is connected with two paths of multiport selector switches, the selector switch is connected with two paths of delay units, the delay units respectively feed back to the two paths of detection signal input ends, the multiport selector switch has 10 channels, wherein the channel 10 is a control input end, the channel 1 is a ground, and the rest channels are data input ends. The detected voltage signal is U, the logic judgment minimum voltage scale is K, the channels Y of the selection switch are Y1, Y2, Y3 and Y4 … … respectively, and the specific implementation logic is as follows: if the detected voltage signal U is greater than 0, opening a channel 2, if U <1k, then Y2=1, otherwise, judging whether U is smaller than 2k, and sequentially recurrently level by level with the U value within 8 k; if the detected voltage signal U <0, opening the channel 1, if U > -1k, then Y1=1, otherwise, judging whether U is larger than-2 k, and gradually recurrently and sequentially, wherein the value of U is within-8 k.
The delay module consists of a multi-port selection switch and a delay unit, and if the voltage signal input into the delay alignment module is greater than 0, the first detection signal is advanced to the second detection signal, and the upper path selection switch is set to be in an input signal state; and if the voltage signal input into the delay alignment module is less than 0, which indicates that the first detection signal lags the second detection signal, setting the down-route selection switch to be in an input signal state. The result generated by the logic judger determines the number of the transistor access circuits of the delay unit, introduces delay amount and realizes delay alignment.
Example 2
When the method is applied to a time delay alignment scheme of a power amplifier, when one path of two paths of signals is a reference signal and the other path of the two paths of signals is a detection signal, only one time delay module is needed, and a U value detected by a logic judgment module is always greater than 0.
For example 1, a Matlab2018 simulation platform is used to verify the technical scheme, and the comparison between the input original signal and the analog delay alignment signal obtained by the method of the present invention is shown in fig. 6 and 7. It can be seen from the figure that there is a certain delay between the two input signals, the delay amount is 3ms; after the device is used for simulating the time delay alignment operation, the alignment of two paths of signals can be realized.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.
Claims (8)
1. An analog time delay alignment device based on a phase discriminator and a charge pump is characterized by comprising a signal input module, a phase discriminator module, a charge pump module, a filter, a logic decision module and a time delay module;
the signal input module is used for carrying out amplitude limiting processing on the two paths of input signals and then inputting the two paths of input signals to the phase discrimination module;
the phase discrimination module comprises a phase discrimination unit and a control unit; the phase discrimination unit consists of two clock-controlled D triggers, each clock-controlled D trigger extracts the time difference from the beginning of the rising edge of two amplitude limiting input signals to the time when the two signals simultaneously rise to a high level, and the time difference corresponds to the duty ratio maintained by the high or low level after the combination; the control unit is used for controlling the phase discrimination unit to stop phase discrimination;
the charge pump module comprises an attenuator, a charge pump and a combiner; the attenuator is used for attenuating the voltage signal output by the phase discrimination module to a certain amplitude, the charge pump is used for converting the attenuated voltage signal into a current signal, and the combiner is used for combining two paths of current signals into one path of current signal;
the filter is used for filtering harmonic waves and noise of current signals output by the charge pump module, integrating the current signals and converting the current signals into voltage signals;
the logic judgment module is used for detecting the amplitude of the voltage signal filtered by the filter and judging which path of signal is delayed and delayed based on the amplitude value;
the delay module comprises a multi-port selection switch and a delay unit, wherein the delay unit consists of m transistors; the multiport selection switch selects the number of the transistors which are connected with the access circuit according to the result of the logic judgment module, selects the signal delay amount, and feeds back the delay amount to the input signal, thereby completing delay alignment.
2. The analog delay alignment device of claim 1, wherein the control unit is configured to control the phase detection unit to stop phase detection, including normal stop phase detection and abnormal stop phase detection; the normal stop phase demodulation is realized through a NAND gate, and when the control unit detects that two paths of signals are high level at the same time, the clock control D trigger is closed; the abnormal stop phase detection comprises an exclusive-OR gate, an exclusive-NOR gate and a NAND gate, and the clocked D flip-flop is closed when the control unit judges that the input signal has an error.
3. The analog delay alignment device of claim 1, wherein the attenuator comprises a forward attenuator and a reverse attenuator; after the attenuation of the forward attenuator is K times, the charge pump is charged, and the voltage is positive; the attenuation of the reverse attenuator is-K times, the charge pump discharges, and the voltage is negative.
4. The analog delay alignment device of claim 1, wherein a positive charge pump output current indicates a lead in one input signal and a negative charge pump output current indicates a lead in the other input signal.
5. The analog delay alignment device of claim 1, wherein the filter is a passive low pass filter.
6. The analog delay alignment device of claim 1, wherein the multi-port selector switch has m +2 channels, the first input channel being a control input for selecting the number of transistors of the delay cell that are connected to the system; the last channel is grounded, and the other m channels are data input ends; the data input terminal is connected with the m transistors.
7. The analog delay alignment device of claim 6, wherein m ≧ 8.
8. A method for aligning analog delay based on the analog delay aligning device of any one of claims 1 to 7, comprising the steps of:
step 1, after amplitude limiting differential processing is carried out on two paths of input signals, phase difference of the two paths of signals is extracted;
step 2, obtaining a time delay result based on the phase difference, and then converting the time delay signal into a voltage signal;
and 3, filtering the voltage signal obtained in the step 2, judging the delay amount, and judging which path of signal is subjected to delay compensation processing according to the delay amount.
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| G.C.T.Leung等.a 1v 13mw 2.5ghz double rate phase locked loop with phase alignment for zero delay.esscirc 2004 29th European solid state circuits conference.2004,109-112. * |
| 朱曼子 ; 刘伯安 ; .一种新型混合信号时钟延时锁定环电路设计.微电子学与计算机.2018,(第03期),50-53. * |
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