CN105322965A - Digital analog converter with delay deviation detection and calibration functions - Google Patents
Digital analog converter with delay deviation detection and calibration functions Download PDFInfo
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Abstract
The invention provides a digital analog converter with delay deviation detection and calibration functions. The digital analog converter with the delay deviation detection and calibration functions is added with a redundant access with structure the same as a normal data access, and in calibration of a to-be-calibrated access, the redundant access is used for processing a signal flowing through the to-be-calibrated access, so that normal operation of the digital analog converter does not need to be interrupted, and calibration of a digital analog converter access is greatly facilitated; besides, the digital analog converter adopts a feedback regulation manner, has low requirement on linearity of a delay deviation detection circuit, is easy to realize and also can calibrate delay deviation change caused by temperature drift or working environmental change and delay deviation caused by inconsistency of lengths of interconnected wires, thereby having strong practical value and popularization and application prospects.
Description
Technical field
The present invention relates to electronic circuit technology field, particularly relate to a kind of digital to analog converter with delay distortion monitoring and testing function.
Background technology
Digital to analog converter (DAC) is circuit digital signal being converted to analog signal.In communication system applications, employing high speed, high-performance DAC chip not only make system configuration greatly simplify, and improve flexibility and the portability of system simultaneously.This reason just, in a lot of fields, at a high speed, high-performance DAC chip just progressively replaces conventional analog circuits, becomes study hotspot new in system scheme.These applications comprise broadband wireless communications, wire cable broadband data services, optical fiber communication etc.In above-mentioned application, the performance of high-speed DAC chip, especially dynamic property are the key factors of decision systems performance.
The Frequency spectrum quality of chip signal output that what the dynamic property (dynamicperformance) of DAC was weighed is, leading indicator comprises Spurious Free Dynamic Range (SFDR), third order intermodulation (IM3), signal and noise distortion ratio (SNDR) etc.
In recent years, along with the development of microelectronic technique and the progress of circuit design technique, sampling rate receives more and more concern to high speed current steer type (highspeedcurrentsteering) DAC chip of GSps (Sample-per-second).
For high speed current steer type DAC chip, usually its dynamic property is subject to the impact of the following aspects factor, comprising: current source mismatch (mismatch-of-current-sources), output impedance associated with the data change (data-dependent-output-resistance-variation), delay distortion associated with the data (data-dependent-delay-variation) etc.In above-mentioned influencing factor, first factor (current source mismatch) and second factor (output impedance change associated with the data), had ripe solution.For the 3rd factor, there is no good solution at present.Delay distortion refers to, due to domain or transistor switch speed inconsistent, each current switch cell of the DAC caused arrives the different phenomenon of the delay of output contact.
For the delay distortion that data are relevant, mainly contain following several resolving ideas at present:
1, in DAC output signal path and clock path, adopt tree structure, make clock arrive the moment of afterbody d type flip flop unanimously, and each current switch is consistent to the delay of output contact.The shortcoming of this method is the complexity significantly increasing domain, and parasitic capacitance increases, and may limit the raising of clock frequency, and cause the reduction of the high frequency performance of DAC; In addition, this method can not be eliminated in afterbody d type flip flop and current switch, delay distortion caused by transistor threshold voltage mismatch;
2, adopt digital random return zero technique, this technique eliminates the correlation that various non-ideal effects and DAC input data, thus raising SFDR.The major defect of this method is, output signal can only be NRZ, limits application; Secondly, this method essence converts harmonic distortion to noise, and signal to noise ratio can't be improved.
Summary of the invention
(1) technical problem that will solve
In view of above-mentioned technical problem, the invention provides a kind of digital to analog converter with delay distortion monitoring and testing function.
(2) technical scheme
The digital to analog converter that the present invention has delay distortion monitoring and testing function comprises: switch matrix 4, channel module, delay distortion testing circuit 7 and state machine 8.Wherein: switch matrix 4 comprises: N+1 input port and N+1 output port, the input port of one of them is communicated with the output port of one of them, N >=1 by it under the control of gating signal.Channel module, comprise N bar data path and 1 redundant via, data path is identical with the structure of redundant via, include a delay control unit, and for each path, and its input is connected to the output port in switch matrix, two output is connected to the input of delay distortion testing circuit and the output of digital to analog converter respectively.The signal input port to be compared of delay distortion testing circuit 7 front end is connected to the common calibrating signal output of N+1 bar path, and reference signal entrance inputs the second reference signal, for obtaining the delay distortion between signal to be compared and reference signal.State machine 8 rear end is connected to delay distortion testing circuit, and its front end is connected to switch matrix and channel module, for: export gating signal to switch matrix and channel module; And the delay utilizing delay distortion testing circuit to export is poor, generate delay control signal, and this delay control signal is sent to the delay control unit in path to be calibrated, fed back by successive ignition, finally make the output signal of this path to be calibrated aim on a timeline with the second reference signal.
(3) beneficial effect
As can be seen from technique scheme, the digital to analog converter that the present invention has delay distortion monitoring and testing function has following beneficial effect:
(1) redundant via that a line structure is identical with normal data path is added, when calibrating path to be calibrated, by redundant via, the signal that path to be calibrated carries out is processed, thus do not need the normal work interrupting digital to analog converter, greatly facilitate the calibration of digital to analog converter path;
(2) change by temperature drift or operational environment the delay distortion caused to change, also can be calibrated in time, thus make the maintenance high performance operation of DAC long-term stability;
(3) also can be detected and calibrate by the inconsistent delay distortion caused of the length of interconnection line, therefore, when layout design, according to the interconnected principle of shortest path, thus parasitic capacitance can be reduced, contribute to improving clock frequency, realize higher DAC sample rate;
(4) adopt the mode of feedback regulation, delay distortion testing circuit only needs to obtain delay information bigger than normal or less than normal, and the linearity for delay distortion testing circuit is lower, is easy to circuit realiration.
Accompanying drawing explanation
Fig. 1 is the structural representation of the digital to analog converter according to the embodiment of the present invention with delay distortion monitoring and testing function;
Fig. 2 is the structural representation of current switch cell in digital to analog converter shown in Fig. 1;
Fig. 3 is the structural representation of delay distortion testing circuit in digital to analog converter shown in Fig. 1.
[symbol description]
1-current switch cell; 2-numerical control delay line;
3-resampling d type flip flop; 4-switch matrix;
5-first buffer amplifier; 6-second buffer amplifier;
7-delay distortion testing circuit 8-state machine;
9-time difference amplifier; 10-time data transducer.
Embodiment
The present invention adopts the mode of feedback regulation, adds a road redundant via, thus achieves the delay distortion monitoring and testing of digital to analog converter.
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
In one exemplary embodiment of the present invention, provide a kind of digital to analog converter with delay distortion monitoring and testing function.Please refer to Fig. 1, the digital to analog converter that the present embodiment has delay distortion monitoring and testing function comprises:
Switch matrix (MUXArray) 4, comprising: N+1 input port, a N+1 output port, and it is under the control of gating signal, the input port of one of them can be communicated with the output port of one of them, N >=1;
Channel module, comprise N bar data path and 1 redundant via, data path is identical with the structure of redundant via, include a delay control unit, for each path, its input is connected to the output port in switch matrix, and two output is connected to the output of delay distortion testing circuit and the output of digital to analog converter;
Delay distortion testing circuit 7, the signal input port to be compared of its front end is connected to the common calibrating signal output (CalP/CalN) of N+1 bar path, and reference signal entrance inputs the second reference signal REF
2, for obtaining signal to be compared and the second reference signal REF
2between delay distortion;
State machine 8, its rear end is connected to delay distortion testing circuit, and its front end is connected to switch matrix and N+1 bar path, for:
(1) gating signal Cal<N-1:0, REF> is exported to switch matrix and N+1 bar path, wherein,
In switch matrix, by signal corresponding for path to be calibrated input redundant via, Reference Signal inputs path to be calibrated,
At the output of N+1 bar path, the signal that redundant via exports exports the output of digital to analog converter to as the output signal of data path to be calibrated, and the signal that path to be calibrated exports is output to delay distortion testing circuit;
(2) delay utilizing delay distortion testing circuit to export is poor, generate delay control signal, and this delay control signal is sent to the delay control unit in path to be calibrated, fed back by successive ignition, finally make the output signal of this path to be calibrated aim on a timeline with the second reference signal;
(3) after the calibration completing this path to be calibrated, the calibration of next path to be calibrated is carried out.
Visible, in the present invention, add a road redundant via at channel module, this redundant via has identical circuit structure with other data path; In a calibration process, the input of path to be calibrated is connected to reference signal by switch matrix, and output signal and the reference signal of this path compare, and the delay obtained between the two is poor, and completes calibration; The input of redundant channel is connected to input signal corresponding to path to be calibrated by switch matrix, and the output of this path is connected to the output of digital to analog converter; Other paths keep normal work in the process; Afterwards, path to be calibrated and former data path Zhong mono-tunnel exchange, and the output signal of new path to be calibrated and reference signal are compared calibration, replaces this closed-circuit working by redundant via.Similar, can calibrate data switch ways successively, until all channel delays all align with reference signal.In a calibration process, the current switch total number being connected to output node remains unchanged, and digital to analog converter output signal keeps normal work, can not interrupt because of calibration process.
It should be noted that, the delay distortion of redundant channel self also can be calibrated in a calibration process.When carrying out redundant channel self-aligning, this passage is passage to be calibrated, and its input is connected to reference signal by switch matrix, and output signal is output to delay distortion testing circuit and reference signal compares, the delay obtained between the two is poor, and completes calibration; Other paths keep normal work in the process.
As the above analysis, the present embodiment digital to analog converter is by adding the line structure redundant via identical with normal data path, when calibrating path to be calibrated, by redundant via, the signal that path to be calibrated carries out is processed, thus do not need the normal work interrupting digital to analog converter, greatly facilitate the calibration of digital to analog converter path.
Please refer to Fig. 1, switch matrix 4 one has (N+1) individual input port I
rEF, I
0~ I
n-1; And (N+1) individual output port O
rEF, O
0~ O
n-1, switch matrix.Wherein, the first reference signal REF
1input to input port I
rEF, data-signal B
0~ B
n-1input to input port I
0~ I
n-1; Redundant via is connected to output port O
rEF, N bar data path is connected to output port O
0~ O
n-1.At the gating signal Cal<N-1:0 of control port input, REF>, under the control of this signal, can the signal of an input port input be exported to the arbitrary output port do not conflicted.
In the present embodiment, for simplicity, when calibrating, by input port I
rEFwith output port O
rEFcorrespondence, by input port I
0~ I
n-1respectively with output port O
0~ O
n-1in corresponding port corresponding.When calibrating n-th path, under the control of gating signal Cal<N-1:0, REF>, by input port I
nwith output port O
rEFbe connected, make data-signal B
nprocessed by redundant via; By input port I
rEFwith output port O
nbe connected, reference signal REF1 processed via calibration path, enters follow-up delay distortion testing circuit.
Be understandable that, the present embodiment only gives a kind of easy, is easy to the switch matrix implementation realized.Those skilled in the art also can adopt other switch matrix control mode, are not limited herein.
In channel module, comprise N bar data path and 1 redundant via.Wherein, although the function of data path and redundant via is different, its structure is identical.
Please refer to Fig. 1, each path comprises: resampling d type flip flop (Re-SamplingDFF) 3, numerical control delay line (Digital-controlledDelay-line) 2 and current switch cell (CurrentSwitch) 1.For whole channel module, it comprises: N+1 resampling d type flip flop (DFF
rEF, DFF
0, DFF
1, DFF
2..., DFF
n..., DFF
n-3, DFF
n-2, DFF
n-1); N+1 numerical control delay line (Td
rEF, Td
0, Td
1, Td
2..., Td
n..., Td
n-3, Td
n-2, Td
n-1); And N+1 current switch cell (CS
rEF, CS
0, CS
1, CS
2..., CS
n..., CS
n-3, CS
n-2, CS
n-1).
For the path of n-th in described channel module, it comprises: resampling d type flip flop 3, and it is for by corresponding output port (O on switch matrix
n) signal alignment that exports is to sampling clock; Numerical control delay line 2, the delay control signal (Dly that the signal for being exported by resampling d type flip flop 3 inputs according to state machine 8
n) carry out time delay; Current switch cell 1, its input connects the output of numerical control delay line, and output is connected to digital to analog converter output or delay distortion testing circuit input respectively, and it is at gating signal (Cal corresponding to this path
n) control under, export the current signal that unit current source produces the input port of digital to analog converter output port or delay distortion detection module to.Wherein, n=0,1 ..., N-1.
In a path, the signal that corresponding output port on switch matrix exports mainly is snapped to sampling clock by the effect of resampling d type flip flop 3 again.Except adopting except d type flip flop, other the alignment circuit such as latch, rest-set flip-flop can also be adopted.
In the present embodiment, adopt numerical control delay line 2 to control, at the length of delay of the delay distortion large the least dominating number control delay line provided according to delay distortion testing circuit 7 by state machine 8, delay is carried out to the signal by path and regulates.
It should be noted that, the function of numerical control delay line also can adopt analogue delay unit (AnalogDelayCell) to realize, regulate although analogue delay unit can realize continuous print, the fluctuation of control voltage (or electric current) will increase the shake (jitter) of output signal.The benefit adopting numerical control delay line to obtain less shake, avoids the deterioration of DAC signal to noise ratio (SNR).Wherein, N+1 numerical control delay line-Td
rEF, Td
0, Td
1, Td
2..., Td
n..., Td
n-3, Td
n-2, Td
n-1the corresponding delayed control signal Dly exported by state machine respectively
rEF, Dly
0, Dly
1, Dly
2..., Dly
n..., Dly
n-3, Dly
n-2, Dly
n-1, namely Dly<N-1:0, REF> control.
In a path, the Main Function of current switch cell 1 is according to supplied with digital signal and calibration control signal, and the current signal that unit current source produces is outputted to corresponding node.In the present embodiment, current switch cell adopts NMOS current switch structure, and compared to PMOS current switch structure, it has switching speed faster, and its circuit theory schematic diagram please refer to Fig. 2.
It should be noted that, in order to improve the anti-interference of circuit, differential logic is adopted at each contactor unit, namely contactor unit exports digital to analog converter output to is two paths of differential signals-OP, ON, equally, that it exports delay distortion testing circuit to is also two paths of differential signals-CP, CN.
Please refer to Fig. 2, for the current switch cell in n-th path, it comprises:
First NMOS tube N1 and the second NMOS tube N2, both source electrodes connect current source jointly, and both grids are connected respectively to input differential signal-DP
nand DN
n;
3rd NMOS tube N3 and the 4th NMOS tube N4, both source electrodes are connected to the drain electrode of the first NMOS tube N1 jointly, and both grids are connected to Cal respectively
nwith
the drain electrode output signal ON of drain electrode output signal CN, the 4th NMOS tube N4 of the 3rd NMOS tube N3;
5th NMOS tube N5 and the 6th NMOS tube N6, both source electrodes are connected to the drain electrode of the second NMOS tube N2 jointly, and both grids are connected to Cal respectively
nwith
6th NMOS tube N6 outputs signal the drain electrode output signal OP of CP, the 5th NMOS tube N5;
Wherein, Cal
nwith
to be respectively in channel module gating signal corresponding to n-th path and negative signal thereof.P-OP and ON of differential signal is output to digital to analog converter output, and p-CP and CN of differential signal is output to delay distortion testing circuit.
In the design of calibration circuit, Major Difficulties is and highly sensitive delay distortion measurement circuit design.Differentiate two square-wave signals that there is phase difference, traditional solution adopts phase discriminator.But it is sub-ps magnitude that two input signals carrying out in the present invention detecting postpone difference, traditional phase discriminator unit is difficult to realize.Such as, for the DAC chip of sampling rate to 4GSps, in order to reach the resolution accuracy of 12bit, its delay distortion should be less than 0.1ps.Reach to reach higher degree of regulation, the resolution of delay distortion testing circuit needs to be less than 0.1ps.In order to overcome above-mentioned difficulties, a feasible scheme adopts time difference amplifier (TDA) and time data transducer (TDC) to realize the detection of highly sensitive delay distortion.By means of time difference amplifier (TDA), first by delay distortion td
ibe amplified to K*td
i, wherein K is time difference amplifier gain, then again in time of delivery (TOD) data converter (TDC), quantizes, thus reduce the requirement to TDC resolution to the delay distortion after amplifying.
It should be noted that, in order to improve the accuracy of detection of delay distortion testing circuit 7, isolation front stage circuit, need to carry out Hyblid Buffer Amplifier to input signal, p-CP and CN of differential signal is access in the signal input port to be compared of delay distortion testing circuit 7 after the first buffer amplifier 5, and the second reference signal REF
2the reference signal entrance of delay distortion testing circuit 7 is access in after the second buffer amplifier 6.About the first buffer amplifier 5 and the second buffer amplifier 6, it should be apparent to those skilled in the art that its function and set-up mode, no longer describe in detail herein.
Please refer to Fig. 3, delay distortion testing circuit 7 comprises: time difference amplifier (TDA) 9 and time data transducer (TDC) 10.Wherein, the input of signal to be compared and the second reference signal difference difference input time amplifier, the output of time difference amplifier is communicated to the input of time data transducer, and the output of time data transducer is connected to state machine.Time difference amplifier is for amplifying the delay distortion of signal to be compared and the second reference signal.Time data transducer 10 is for realizing the quantification of delay distortion.
Time difference amplifier is for amplifying the delay distortion of signal to be compared and reference signal.Continue referring to giving a kind of time difference amplifier concrete methods of realizing based on rest-set flip-flop and XOR gate in Fig. 3, figure.
NAND gate NAND1/NAND2 and NAND3/NAND4 forms first, second rest-set flip-flop respectively;
Set end ~ the S1 of the first rest-set flip-flop is connected with the output of the first inverter INV1, second input of reset terminal ~ R1 connect hours difference amplifier, the positive-negative output end of this trigger connects two inputs of the first XOR gate XOR1 respectively, this port is connected to capacity cell simultaneously, the gain of the size influence time difference amplifier of capacitance;
Set end ~ the S2 of the second rest-set flip-flop is connected with second input of time difference amplifier, reset terminal ~ R1 connects the output of the second inverter INV2, the positive-negative output end of this trigger connects two inputs of the second XOR gate XOR2 respectively, this port is connected to capacity cell simultaneously, the gain of the size influence time difference amplifier of capacitance;
First input of the input connect hours difference amplifier of the first inverter INV1, inputs signal to be compared; Second input of the input connect hours difference amplifier of the second inverter INV2, inputs the second reference signal;
The input of the first XOR gate XOR1/XOR2 is connected with the positive-negative output end of first, second rest-set flip-flop respectively, and its output is the output of time difference amplifier.
For this time difference amplifier, if the time difference of input signal is very little, when the rising edge of signal arrives, trigger will enter metastable state, and trigger exits the metastable time and depends on input signal time extent.The output signal of TDA overturns successively exiting the metastable moment, realizes the amplification of delay distortion.The distinguishable delay lower than 0.1ps of this time difference amplifier is poor, meets the requirement of native system.
Time data transducer 10, for being quantized by the delay distortion of analog signal form, obtains the delay distortion (T of digital signal form
0~ T
i).Continue referring to the basic implementation method giving a kind of time data transducer in Fig. 3, figure.In the implementation case, because calibration system adopts the method for feedback regulation, not high to the requirement of quantization digit, take into account the complexity of circuit and the convergence rate of calibration algorithm, the quantizer of 4bit can be adopted.
State machine 8, its rear end is connected to delay distortion testing circuit, and its front end is connected to switch matrix and N+1 bar path, for:
(1) gating signal Cal<N-1:0 is exported, REF> is to switch matrix and N+1 bar path, wherein, in switch matrix, by signal corresponding for path to be calibrated input redundant via, Reference Signal inputs path to be calibrated, at the output of N+1 bar path, the signal that redundant via exports exports the output of digital to analog converter to as the output signal of data path to be calibrated, and the signal that path to be calibrated exports is output to delay distortion testing circuit;
(2) delay utilizing delay distortion testing circuit to export is poor, generate delay control signal, and this delay control signal is sent to the delay control unit in path to be calibrated, fed back by successive ignition, finally make the output signal of this path to be calibrated aim on a timeline with the second reference signal;
(3) after the calibration completing this path to be calibrated, the calibration of next path to be calibrated is carried out.
As the above analysis, the present embodiment digital to analog converter adopts the mode of feedback regulation, and delay distortion testing circuit only needs to obtain delay information bigger than normal or less than normal, and the linearity for delay distortion testing circuit is lower, be easy to circuit realiration, greatly reduce the difficulty of circuit design.
Below introduce the specific works process of the present embodiment digital to analog converter:
(1) data-signal and the reference signal (square-wave signal) for calibrating are connected to switch matrix (MUXArray) 4 jointly; Switch matrix is at calibration gating signal (Cal < N-1:0, REF >) control under, the order of adjustment output signal, Reference Signal is transported to the passage needing calibration, the input signal of passage to be calibrated is connected to redundant channel simultaneously;
(2) original input signal of path to be calibrated is connected to redundant channel through switch matrix, and its output signal is connected to digital to analog converter output port; In this process, other data channel except passage to be calibrated and redundant channel, keep normal mode of operation, its output signal is all connected to digital to analog converter output port;
(3) reference signal REF1 is after the resampling d type flip flop 3 of path to be calibrated, numerical control delay line 2 and current switch cell 1, is connected to an input of delay distortion testing circuit 7, the second reference signal REF by the first buffer amplifier 5
2another input of delay distortion testing circuit is connected to, this second reference signal REF by the second buffer amplifier 6
2by the first reference signal REF
1produce through delay circuit;
(4) delay distortion testing circuit 7 contrasts the delay distortion of two input signals, and quantizes the value of deviation.Afterwards, state machine 8 according to the size adjustment numerical control delay line of delay distortion, and after completing adjustment the inclined extent of testing lag again, repeated multiple times, until testing circuit cannot detect delay distortion or be less than the threshold value of setting;
(5), after calibrate to be detected completes, this path and former data path Zhong mono-tunnel exchange, and calibrate, replace new closed-circuit working to be calibrated by redundant via to new path to be calibrated.Similar, can calibrate data switch ways successively, until all channel delays all with the second reference signal REF
2alignment.After each passage completes calibration successively, the output delay of all current switch cells all with the second reference signal REF
2alignment.The process that calibrated channel switches completes within a clock cycle, and to ensure that DAC normally exports, calibration process does not need interrupt system normally to work.
As the above analysis, the present embodiment digital to analog converter can not only calibrate general delay distortion, and change being changed the delay distortion caused by temperature drift or operational environment, monitoring and testing can be carried out equally by the inconsistent delay distortion caused of the length of interconnection line, thus improve the performance of digital to analog converter greatly.
So far, by reference to the accompanying drawings the present embodiment has been described in detail.Describe according to above, the digital to analog converter that those skilled in the art should have a delay distortion monitoring and testing function to the present invention has had clearly to be familiar with.
It should be noted that, in accompanying drawing or specification text, the implementation not illustrating or describe, is form known to a person of ordinary skill in the art in art, is not described in detail.In addition, the above-mentioned definition to each element and method is not limited in various concrete structures, shape or the mode mentioned in embodiment, and those of ordinary skill in the art can change simply it or replace, such as:
(1) MOS transistor can replace with BJT transistor;
(2) d type flip flop can replace with latch or rest-set flip-flop;
(3) about time difference amplifier and time data transducer, those skilled in the art can select other structure as required;
(4) herein can providing package containing the demonstration of the parameter of particular value, but these parameters are without the need to definitely equaling corresponding value, but can be similar to analog value in acceptable error margin or design constraint.
In sum, the present invention adopts the mode of feedback regulation, linearity for delay distortion testing circuit is lower, be easy to circuit realiration, also can be detected and calibrate by the inconsistent delay distortion caused of the length of interconnection line simultaneously, in addition, invention increases a road redundant via, the normal work interrupting DAC is not needed in the process of calibration, change by temperature drift or operational environment the delay distortion caused to change, also can be calibrated in time, thus make the maintenance high performance operation of DAC long-term stability, there is good popularizing application prospect.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. there is a digital to analog converter for delay distortion monitoring and testing function, it is characterized in that, comprising: switch matrix (4), channel module, delay distortion testing circuit (7) and state machine (8), wherein:
Switch matrix (4) comprising: N+1 input port and N+1 output port, and the input port of one of them is communicated with the output port of one of them, N >=1 by it under the control of gating signal;
Channel module, comprise N bar data path and 1 redundant via, data path is identical with the structure of redundant via, include a delay control unit, and for each path, and its input is connected to the output port in switch matrix, two output is connected to the input of delay distortion testing circuit and the output of digital to analog converter respectively;
Delay distortion testing circuit (7), the signal input port to be compared of its front end is connected to the common calibrating signal output of N+1 bar path, reference signal entrance inputs the second reference signal, for obtaining the delay distortion between signal to be compared and reference signal;
State machine (8), its rear end is connected to delay distortion testing circuit, and its front end is connected to switch matrix and channel module, for: export gating signal to switch matrix and channel module; And the delay utilizing delay distortion testing circuit to export is poor, generate delay control signal, and this delay control signal is sent to the delay control unit in path to be calibrated, fed back by successive ignition, finally make the output signal of this path to be calibrated aim on a timeline with the second reference signal.
2. digital to analog converter according to claim 1, is characterized in that, described state machine exports gating signal to switch matrix and channel module;
First reference signal, under the control of gating signal, by signal corresponding for path to be calibrated input redundant via, is inputted path to be calibrated by described switch matrix;
Described channel module completes following operation under the control of gating signal: replace the output signal of data path to be calibrated to export the output of digital to analog converter to the signal that redundant via exports, the signal that path to be calibrated exports is output to delay distortion testing circuit.
3. digital to analog converter according to claim 2, is characterized in that:
Described switch matrix (4) has N+1 input port I
rEF, I
0~ I
n-1; And N+1 output port O
rEF, O
0~ ~ O
n-1, wherein, the first reference signal (REF1) inputs to input port I
rEF, data-signal B
0~ B
n-1input to input port I
0~ I
n-1; Redundant via is connected to output port O
rEF, N bar data path is connected to output port O
0~ O
n-1;
Wherein, at the gating signal Cal<N-1:0 of control port input, under the control of REF>, can the signal of an input port input be exported to the arbitrary output port do not conflicted.
4. digital to analog converter according to claim 3, is characterized in that:
When calibrating, by input port I
rEFwith output port O
rEFcorrespondence, by input port I
0~ I
n-1respectively with output port O
0~ O
n-1in corresponding port corresponding;
When calibrating n-th path, under the control of gating signal Cal<N-1:0, REF>, by input port I
nwith output port O
rEFbe connected, make data-signal B
nprocessed by redundant via, and export the output of digital to analog converter to; By input port I
rEFwith output port O
nbe connected, make the first reference signal (REF1) enter follow-up delay distortion testing circuit via path to be calibrated;
Wherein, n=0,1 ..., N-1.
5. digital to analog converter according to claim 1, is characterized in that, in described channel module, the delays time to control unit in data path and redundant via is numerical control delay line;
For the path of n-th in described channel module, it comprises:
Alignment circuit, for by corresponding output port (O on switch matrix
n) signal alignment that exports is to sampling clock;
Described numerical control delay line, the delay control signal (Dly that the signal for alignment circuit being exported inputs according to state machine (8)
n) carry out time delay;
Current switch cell, its input connects the output of numerical control delay line, and output is connected to digital to analog converter output or delay distortion testing circuit input respectively, and it is at gating signal (Cal corresponding to this path
n) control under, export the current signal that unit current source produces the input port of digital to analog converter output port or delay distortion detection module to;
Wherein, n=0,1 ..., N-1.
6. digital to analog converter according to claim 5, is characterized in that, described alignment circuit is resampling d type flip flop, latch or rest-set flip-flop.
7. digital to analog converter according to claim 5, is characterized in that, described current switch cell comprises:
First NMOS tube (N1) and the second NMOS tube (N2), both source electrodes connect current source jointly, and both grids are connected respectively to input differential signal-DP
nand DN
n;
3rd NMOS tube (N3) and the 4th NMOS tube (N4), both source electrodes are connected to the drain electrode of the first NMOS tube (N1) jointly, and both grids are connected to gating signal-Cal respectively
nwith
the drain electrode output signal CN of the 3rd NMOS tube (N3), the drain electrode output signal ON of the 4th NMOS tube (N4);
5th NMOS tube (N5) and the 6th NMOS tube (N6), both source electrodes are connected to the drain electrode of the second NMOS tube (N2) jointly, and both grids are connected to gating signal-Cal respectively
nwith
6th NMOS tube (N6) outputs signal CP, the drain electrode output signal OP of the 5th NMOS tube (N5);
Wherein, Cal
nwith
to be respectively in channel module gating signal corresponding to n-th path and negative signal thereof, p-OP and ON of differential signal is output to digital to analog converter output, and p-CP and CN of differential signal is output to delay distortion testing circuit.
8. digital to analog converter according to any one of claim 1 to 7, is characterized in that, described delay distortion detection module comprises:
Time difference amplifier (9), the signal input port to be compared of its front end is connected to the common calibrating signal output of N+1 bar path, inputs signal to be compared; Reference signal entrance inputs the second reference signal, for amplifying the delay distortion of signal to be compared and the second reference signal;
Time data transducer (10), its front end is connected to time difference amplifier (9), and its rear end is connected to state machine (8), for realizing the quantification of delay distortion, and the delay distortion after quantizing is sent to state machine;
Wherein, described second reference signal is produced through time delay by the first reference signal.
9. digital to analog converter according to claim 8, is characterized in that, described time difference amplifier (9) comprising:
First inverter (INV1) and the second inverter (INV2), both inputs input signal to be compared and the second reference signal respectively;
First rest-set flip-flop, its set end (~ S1) is connected with the output of the first inverter (INV1), and its reset terminal (~ R1) inputs the second reference signal;
Second rest-set flip-flop, its set end (~ S1) inputs the second reference signal, and its reset terminal (~ R1) is connected with the output of the second inverter (INV2);
First XOR gate (XOR1), its two input is connected with the positive and negative output of the first rest-set flip-flop respectively, and its output is as the first output of time difference amplifier;
Second XOR gate (XOR2), its two input is connected with the positive and negative output of the second rest-set flip-flop respectively, and its output is as the second output of time difference amplifier.
10. digital to analog converter according to any one of claim 1 to 7, is characterized in that,
Described state machine (8), also for after the calibration completing current path to be calibrated, carries out the calibration of next path to be calibrated.
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