CN114422723B - Infrared focal plane pixel level digital reading circuit and method - Google Patents
Infrared focal plane pixel level digital reading circuit and method Download PDFInfo
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- CN114422723B CN114422723B CN202210054811.4A CN202210054811A CN114422723B CN 114422723 B CN114422723 B CN 114422723B CN 202210054811 A CN202210054811 A CN 202210054811A CN 114422723 B CN114422723 B CN 114422723B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Abstract
The invention relates to the technical field of readout circuits of infrared focal plane arrays, and discloses an infrared focal plane pixel level digital readout circuit which comprises a reference detection bridge for providing bias voltage for a reference pixel and a detection bridge matrix for providing bias voltage for a side pixel adjacent to the reference pixel, wherein the detection bridge matrix comprises a plurality of independently arranged detection bridge branches, and any detection bridge branch can respectively form a bridge structure with the reference detection bridge through a switch; the invention also provides an infrared focal plane pixel level digital reading mode and uses the reading circuit. The invention reduces the data volume of analog-to-digital conversion of the reading circuit and relieves the problem of high-speed output of large data volume of the reading circuit.
Description
Technical Field
The invention relates to the technical field of reading circuits of infrared focal plane arrays, in particular to an infrared focal plane pixel-level digital reading circuit and method.
Background
The infrared reading circuit is an important component of the infrared detector, and has the functions of providing bias voltage required by the detection pixels and sequentially outputting information of the detection array row by row and column by column. With the development of the technology of the readout circuit, the integration functions of the readout circuit, such as analog-to-digital conversion on a chip, and on-chip non-uniformity correction, are increasing. The on-chip analog-to-digital conversion is divided into a chip level, a column level and a pixel level, and currently, an infrared reading circuit mostly adopts a column level analog-to-digital conversion channel to perform analog-to-digital conversion on array signals line by line.
With the diversification of the application scenes of the infrared detector, further requirements are put forward on the integration level and the intellectualization of the infrared detector, and the pixel-level digitalization receives much attention. The pixel level is digitalized, namely, analog-to-digital conversion is completed inside the pixel; the pixels directly output the digital code. The pixel level digitization means that all pixels on a focal plane are integrated and converted into analog signals at the same time, and the output frame frequency of the infrared reading circuit can be greatly improved.
Under the development trend of large area array and high frame frequency, a large amount of data can be generated in a short time, however, the output transmission speed of the reading circuit has a bottleneck, and a large amount of data containing detection information cannot be timely output from the pixel-level digitizing reading circuit.
Disclosure of Invention
The invention provides an infrared focal plane pixel level digitization reading circuit and a method, which have a circuit structure capable of compressing data, and fundamentally reduce the data volume generated by pixel level digitization at a detector end.
The invention is realized by the following technical scheme:
an infrared focal plane pixel level digitizing readout circuit comprises a reference detection bridge for providing bias voltage for reference pixels and a detection bridge matrix for providing bias voltage for side pixels adjacent to the reference pixels,
the detection bridge matrix comprises a plurality of detection bridge branches which are independently arranged, and any detection bridge branch can form a bridge structure with the reference detection bridge through a switch;
the reference detection bridge works independently and transmits current containing detection information to the operational amplifier multiplexing circuit; when the reference detection bridge does not work independently, the difference between the currents of the detection bridge branch and the reference detection bridge is transmitted to the operational amplifier multiplexing circuit;
also comprises an operational amplifier multiplexing circuit and a signal latch circuit,
the operational amplifier multiplexing circuit can be switched between a capacitance transconductance amplifier mode and a comparator mode; the capacitive transconductance amplifier mode integrates the current output by the reference detection bridge or the detection bridge matrix; the comparator mode compares the integrated voltage with the ramp voltage and outputs the result to the signal latch circuit as a latch enable signal, the latch signal of which is a BITX signal.
In the technical scheme, the read data of the reference pixel can be obtained according to the detection current of the reference detection bridge, the read data of the side pixel beside the reference pixel is obtained according to the current difference between the detection bridge matrix and the reference detection bridge, and only the difference sequence is transmitted, so that the data transmission is reduced, and the purpose of compressing the data is achieved.
Preferably, the reference detection bridge comprises a first blind pixel element R b A first PMOS transistor MP eb A first NMOS transistor MN sel A second NMOS transistor MN fid A first detection pixel R s A third switch S3 and a fourth switch S4, the first blind pixel element R b Is connected to a first bias voltage Vsk, the first blind pixel element R b And the other end of the first PMOS transistor MP eb Is connected to the source of the first PMOS transistor MP eb And the first NMOS transistor MN sel The drain of the first NMOS transistor MN is connected sel And the second NMOS transistor MN fid The drain of the second NMOS transistor MN is connected fid Through the third switch S3 and the second NMOS transistor MN fid The second NMOS transistor MN fid Through the fourth switch S4 and a second bias voltage V fid Connected, the second NMOS transistor MN fid And the first detection pixel R s Is connected to the first detection pixel R s Is connected to a power ground GND, said first PMOS transistor MP eb And a third bias voltage V eb And (4) connecting.
Preferably, the output end of the reference detection bridge is the first NMOS transistor MN sel When the reference detection bridge works independently, a switch arranged between the reference detection bridge and the detection bridge matrix is switched off, and the value of the input current of the operational amplifier multiplexing circuit is equal to the value of the input current flowing through the first blind pixel R b Current and current flowing through the first probePixel R s The difference between the currents.
As optimization, the detection bridge matrix comprises a plurality of detection bridge branches with the same structure, and the detection bridge branches comprise second blind pixel elements R bi A second PMOS transistor MP ebi A third NMOS transistor MN seli A fourth NMOS transistor MN fidi A second detection pixel R si A first switch S1 i And a second switch S2 i The second blind pixel element R bi Is connected with the first bias voltage Vsk, and the second blind pixel element R bi And the other end of the second PMOS transistor MP ebi The source of the second PMOS transistor MP ebi And the third NMOS transistor MN seli The drain of the third NMOS transistor MN is connected seli And the fourth NMOS transistor MN fidi The drain of the fourth NMOS transistor MN is connected fidi Is connected to the second detection pixel R si Is connected to the second detection pixel R si Is connected to the power ground GND, the second PMOS transistor MP ebi Through the first switch S1 i And the first PMOS transistor MP eb Gate connection of the fourth NMOS transistor MN fidi Through the switch S2 i Is connected to the second NMOS transistor MN fid A gate electrode of (1).
As an optimization, the output end of the detection bridge branch is the third NMOS transistor MN seli When the reference detection bridge does not work independently, a switch arranged between the reference detection bridge and the detection bridge matrix is closed, and the input current value of the operational amplifier multiplexing circuit flows through the second detection pixel R si And flows through the first detection pixel R s The difference in current of (2).
Preferably, the operational amplifier multiplexing circuit comprises an operational amplifier Opamp, an integrating capacitor C, a reset switch RST, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9 and a tenth switch S int1 And an eleventh switchS int2 The output end of the reference detection bridge passes through the tenth switch S int1 Connected to the inverting input of the operational amplifier Opamp, the output of the detection bridge matrix is connected via the eleventh switch S int2 Is connected to the inverting input terminal of the operational amplifier Opamp, and the non-inverting input terminal of the operational amplifier Opamp is connected to the reference voltage V through the eighth switch S8 and the ninth switch S9 Ref And a ramp voltage V Ramp The integrating capacitor C and the reset switch RST are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier Opamp, and the end of the parallel link of the integrating capacitor C and the reset switch RST connected to the output terminal of the operational amplifier Opamp is connected to the reference voltage V through the fifth switch S5 Ref Meanwhile, the sixth switch S6 is arranged between the parallel link of the integrating capacitor C and the reset switch RST and the output end of the operational amplifier Opamp, and the output end of the operational amplifier Opamp is connected with the signal latch circuit through the seventh switch S7.
The invention also provides an infrared focal plane pixel level digital reading mode, and the reading circuit comprises the following steps:
step 1, the operational amplifier multiplexing circuit outputs current I when independently working to the reference detection bridge int (t) integrating, then performing analog-to-digital conversion, and sequentially converting N-bit digital codes through the signal latch circuit;
Preferably, the operational amplifier multiplexing circuit comprises operational amplificationOpamp, integrating capacitor C, reset switch RST, fifth switch S5, sixth switch S6, seventh switch S7, eighth switch S8, ninth switch S9 and tenth switch S int1 And an eleventh switch S int2 The output end of the reference detection bridge passes through the tenth switch S int1 Connected to the inverting input of the operational amplifier Opamp, the output of the detection bridge matrix is connected via the eleventh switch S int2 Connected to the inverting input terminal of the operational amplifier Opamp, the non-inverting input terminal of the operational amplifier Opamp is connected to the reference voltage V through the eighth switch S8 and the ninth switch S9 Ref And a ramp voltage V Ramp The integrating capacitor C and the reset switch RST are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier Opamp, and one end of the parallel link of the integrating capacitor C and the reset switch RST, which is connected with the output terminal of the operational amplifier Opamp, is connected with the reference voltage V through the fifth switch S5 Ref Meanwhile, the sixth switch S6 is arranged between the parallel link of the integrating capacitor C and the reset switch RST and the output end of the operational amplifier Opamp, and the output end of the operational amplifier Opamp is connected with the signal latch circuit through the seventh switch S7.
As optimization, in step 1, the operational amplifier multiplexing circuit outputs current I when the reference detection bridge operates independently int (t) the integration is specifically: the sixth switch S6, the eighth switch S8 and the tenth switch S int1 Close the fifth switch S5, the seventh switch S7, the ninth switch S9 and the eleventh switch S int2 Switching off to enable an integrating capacitor C in the operational amplifier multiplexing circuit to integrate the output current of the reference detection bridge;
in step 2, the operational amplifier multiplexing circuit outputs current I when the reference detection bridge does not work independently inti The integration in (t) is specifically as follows: the sixth switch S6, the eighth switch S8 and the eleventh switch S int2 Closing the fifth switch S5, the seventh switch S7, the ninth switch S9 and the tenth switch S int1 Is disconnected so thatAnd an integrating capacitor C in the operational amplifier multiplexing circuit integrates the difference between the output current of the detection bridge matrix and the output current of the reference detection bridge.
As an optimization, in step 1 and step 2, the analog-to-digital conversion of the integrated current by the operational amplifier multiplexing circuit specifically includes: the sixth switch S6 and the eighth switch S8 are opened, the fifth switch S5, the seventh switch S7, and the ninth switch S9 are closed, and the integrated voltage of the integrating capacitor C is compared with the ramp voltage.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the invention reduces the data volume of the analog-digital conversion of the reading circuit, relieves the problem of high-speed output of large data volume of the reading circuit, and has the advantages of variable comparison times in the analog-digital conversion of difference values based on multi-channel bit serial conversion, namely variable digital code bit number after information compression, flexibility, and capability of effectively avoiding the problems of overflow or compression bit waste caused by overlarge or very small difference of detection signals among pixels and fixed compression bit number.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and that those skilled in the art may also derive other related drawings based on these drawings without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of the overall architecture of a pixel level digitizing readout circuit according to one embodiment of the invention.
FIG. 2 is a circuit schematic of a reference detection bridge and a matrix of detection bridges in accordance with one embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and the accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not used as limiting the present invention.
Examples
In imaging detection, adjacent pixels in the same scene have the characteristics of continuous change and less mutation, and the adjacent pixel values are known to have correlation. The invention firstly selects a pixel at a certain position as a reference pixel (a first detection pixel R) s ) Its detection information is processed and analog-to-digital converted, while other nearby pixels (second detection pixel R) si ) The detected information has correlation, and the difference between the two can be used as an effective signal for processing and conversion. Therefore, the encoding can be carried out by using a small number of bits, only the difference value sequence is transmitted, the transmission of data is reduced, and the purpose of compressing data is achieved.
It should be noted that, in 2008, c.h.hwang proposed the structure of op-amp multiplexing in pixel level analog-to-digital conversion, and an inventive example of the present invention uses the structure to relieve the stress caused by small pixel area.
Fig. 1 is a schematic diagram of the overall architecture of an infrared focal plane pixel level digitizing readout circuit, in accordance with one embodiment of the present invention. In an embodiment of the invention, the readout circuit is configured to receive the analog signal of the detection pixel, perform integration and analog-to-digital conversion on the analog signal, and finally output the analog signal.
Specifically, the infrared focal plane pixel level digital readout circuit of the present invention includes a reference detection bridge 10 and a detection bridge matrix 20, and further includes an operational amplifier multiplexing circuit 30 and a signal latch circuit 40.
In this embodiment, the reference detection bridge 10 and the detection bridge matrix 20 are used to provide the first bias voltage to the detection pixel and output the analog signal containing the detection information, and the reference detection bridge 10 can work independently and pass through the tenth switch S int1 303 outputs (including detection information) a current signal to the operational amplifier multiplexing circuit 30; in addition, the detection bridge matrix 20 includes a plurality of detection bridge branches having the same structure and arranged independently, and any detection bridge branchThe bridge branches can form a bridge structure with the reference detection bridge 10 and pass through the eleventh switch S int2 304 outputs (including the detection information) a current signal to the op-amp multiplexing circuit 30.
Specifically, when the switch disposed between the reference detection bridge 10 and the detection bridge matrix 20 is turned off, the reference detection bridge 10 passes the current containing the detection information through the tenth switch S int1 303 to the operational amplifier multiplexing circuit 30; when the switches arranged between the reference detection bridge 10 and the detection bridge matrix 20 are closed, the difference between the currents of the detection bridge branches and the reference detection bridge 10 (the current signal containing the detection information) is passed through the eleventh switch S int2 304 to the op-amp multiplexing circuit 30.
The operational amplifier multiplexing circuit can be switched between a capacitance transconductance amplifier mode and a comparator mode; the operational amplifier multiplexing circuit in a capacitive transconductance amplifier mode integrates the current output by the reference detection bridge or the detection bridge matrix; the operational amplifier multiplexing circuit in the comparator mode compares the integral voltage with the ramp voltage and outputs the result.
In this embodiment, the operational amplifier multiplexing circuit 30 includes an operational amplifier Opamp 301, an integrating capacitor C302, a reset switch RST 310, a fifth switch S5305, a sixth switch S6, a seventh switch S7307, an eighth switch S8308, a ninth switch S9, and a tenth switch S9 int1 303 and an eleventh switch S int2 304, the output terminal of the reference detection bridge 10 passes through the tenth switch S int1 303 is connected to the inverting input of the operational amplifier Opamp 301 and the output of the detection bridge matrix 20 is passed through the eleventh switch S int2 304 is connected to an inverting input terminal of the operational amplifier Opamp 301, and a non-inverting input terminal of the operational amplifier Opamp 301 is connected to a reference voltage V via the eighth switch S8 and the ninth switch S9309, respectively Ref And a ramp voltage V Ramp The integrating capacitor C302 and the reset switch RST 310 are connected in parallel between the inverting input end and the output end of the operational amplifier Opamp 301, and the integrating capacitor C302 and the reset switch ROne end of the parallel link of ST 310 connected to the output terminal of the operational amplifier Opamp 301 is connected to the reference voltage V through the fifth switch S5305 Ref Meanwhile, the sixth switch S6306 is arranged between the parallel link of the integrating capacitor C302 and the reset switch RST 310 and the output end of the operational amplifier Opamp 301, and the output end of the operational amplifier Opamp 301 is connected to the signal latch circuit 40 through the seventh switch S7307.
Before integrating the current, the reset switch RST 310 is closed, resetting the integrating capacitor C302.
In this embodiment, in the integration stage, the operational amplifier multiplexing circuit 30 is in a capacitive transconductance amplifier mode: the sixth switch S6306 and the eighth switch S8308 are closed, the fifth switch S5305, the seventh switch S7307, and the ninth switch S9309 are opened, and the tenth switch S9309 is opened int1 303 or eleventh switch S int2 304 are closed and the operational amplifier multiplexing circuit 30 integrates the current signal from the reference detection bridge 10 and/or the detection bridge matrix 20. The voltage at the output of the operational amplifier Opamp 301 after integration is:
wherein, t int Representing the integration time, V, of the integrating capacitor C Ref C is the size of the integrating capacitor as a reference voltage.
After the integration is completed, the sixth switch S6 and the eighth switch S8 are opened, the fifth switch S5, the seventh switch S7 and the ninth switch S9 are closed, and since the voltage across the integrating capacitor C does not change suddenly, the voltage at the inverting input terminal of the operational amplifier Opamp 301 is:
V A-D ＝2V Ref -V int (t int ) (2)
wherein, V int (t int ) Is the integral voltage, t int Representing integration time, V Ref As a reference voltage, the integral voltage V int (t int ) Is the output end of the Opamp 301 of the operational amplifier after the integration is finishedA voltage.
The operational amplifier multiplexing circuit is switched in the digital-to-analog conversion stage, and at this time, the operational amplifier multiplexing circuit 30 is in the comparator mode: for the integral voltage V generated by the capacitor transconductance amplifier mode int (t int ) And a ramp voltage V Ramp And comparing and transmitting the comparison result to the signal latch circuit 40, wherein the signal latch circuit 40 receives the 1-bit BITX signal and judges whether to latch the BITX signal according to the comparison result of the operational amplifier multiplexing circuit 30.
The signal latch circuit 40 includes a latch enable signal terminal connected to the output terminal of the operational amplifier Opamp through the seventh switch S7, a latch signal input terminal connected to the BITX signal terminal, and a signal output terminal.
It should be noted that the signal latch circuit 40 may be a latch commonly used in the art, which is a conventional technical means of those skilled in the art and is not the point of the invention, and therefore, the detailed structure thereof will not be described herein.
In this embodiment, some pixels are uniformly selected on the focal plane and placed on the reference detection bridge 10, the detection bridge branches of the detection bridge matrix 20 are placed in 3 pixels in the vicinity of these pixels, and the operational amplifier multiplexing circuit 30 and the signal latch circuit 40 are shared circuits of the reference detection bridge 10 and the detection bridge matrix 20, that is, 2 × 2 pixels share one set of the operational amplifier multiplexing circuit 30 and the signal latch circuit 40.
The embodiment of the invention adopts multi-channel bit serial conversion, for the integral voltage of one pixel, 1bit digital code is obtained and output by each comparison, N times of comparisons are sequentially finished by changing the change rule of a BITX signal, and the digital codes obtained by the N times of comparisons are combined to be used as the final N-bit digital code.
FIG. 2 is a circuit schematic of a reference detection bridge and a matrix of detection bridges in accordance with one embodiment of the present invention.
As shown in FIG. 2, in the present embodiment, the reference detection bridge 10 includes a first blind pixel element R b 101. First PMOS transistor MP eb 102. A first NMOS transistor MN sel 103. Second NMOS transistor MN fid 104. First detection pixel R s 105. A third switch S3106 and a fourth switch S4107, the first blind pixel R b 101 is connected at one end to a first bias voltage Vsk, and the first blind pixel element R b 101 and the first PMOS transistor MP eb 102, the first PMOS transistor MP eb 102 and the first NMOS transistor MN sel 103, the first NMOS transistor MN sel 103 and the second NMOS transistor MN fid 104, the second NMOS transistor MN fid 104 through the third switch S3106 and the second NMOS transistor MN fid 104, the second NMOS transistor MN fid 104 is connected to a second bias voltage V via the fourth switch S4107 fid Connected, the second NMOS transistor MN fid 104 and the first detection pixel R s 105, and the first detection pixel R s 105 is connected to a power ground GND, and the first PMOS transistor MP eb 102 and a third bias voltage V eb And (4) connecting.
In this embodiment, the output terminal of the reference detection bridge 10 is the first NMOS transistor MN sel 103, the magnitude of the output current containing the detection information when the reference detection bridge 10 works independently is the magnitude of the output current flowing through the first blind pixel element R b 101 current and current flowing through the first detection pixel element R s 105 current.
As shown in fig. 2, the third switch S3106 and the first switch S1 i 206. Second switch S2 i 207 is opened, the fourth switch S4107 is closed, the reference detection bridge 10 works independently, and the output current of the reference detection bridge 10 flows through the first blind pixel element R b 101 current and current flowing through the first detection pixel element R s 105 currents, when the currents are:
I int (t)＝I b (t)-I s (t) (3)
wherein, I S (t) denotes the flow through the first detection pixel R s Current of 105, I b (t) denotes a flow through the first blind pixel element R b 101, respectively.
In this embodiment, the detection bridge matrix 20 includes a plurality of detection bridge branches having the same structure, as shown in fig. 2, the detection bridge branches include a second blind pixel element R bi 201. Second PMOS transistor MP ebi 202. Third NMOS transistor MN seli 203. Fourth NMOS transistor MN fidi 204. Second detection pixel R si 205. First switch S1 i 206 and a second switch S2 i 207, the second blind pixel element R bi 201 is connected with the first bias voltage Vsk, and the second blind pixel element R bi 201 and the other end of the second PMOS transistor MP ebi 202, the second PMOS transistor MP ebi 202 and the third NMOS transistor MN seli 203, the third NMOS transistor MN seli 203 and the fourth NMOS transistor MN fidi 204, the fourth NMOS transistor MN fidi 204 is connected to the second detection pixel R si 205, and the second detection pixel R si 205 is connected to the power ground GND, and the second PMOS transistor MP ebi 202 through the first switch S1 i 206 and the first PMOS transistor MP eb 102, the fourth NMOS transistor MN fidi 204 through the switch S2 i 207 is connected to the second NMOS transistor MN fid 104.
In this embodiment, the output end of the detection bridge branch is the third NMOS transistor MN seli 203, and the output current value of the branch of the detection bridge is the current flowing through the second detection pixel R si 205 and flows through the first detection pixel R s 105, respectively.
As shown in fig. 2, the third switch S3106 and the first switch S1 i 206. Second switch S2 i 207 are closed and the fourth switch S4107 is open, the detection bridge of the detection bridge matrix 20 and the reference detection bridge 10 form a bridge. Detecting electricityThe output value of the bridge matrix 20 is the difference between the currents of the two branches, i.e. through the second detection pixel R si 205 and the current flowing through the first detection pixel element R s 105, the output current at this time is:
I inti (t)＝I si (t)-I s (t)
wherein, I S (t) denotes the flow through the first detection pixel element R s Current of 105, I si (t) denotes a second detection cell R flowing through a branch of the detection bridge matrix 20 si 205.
In one embodiment of the present invention, the reference detection bridge 10 operates independently and outputs a current I int (t) to the operational amplifier multiplexing circuit 30, for I int (t) integrating, and sequentially converting 14-bit digital codes to represent the first detection pixel R on the basis of a multi-channel bit serial conversion structure s The probe information of (1); then, a detecting bridge of the detecting bridge matrix 20 is selected to form a bridge with the reference detecting bridge 10, and the difference I between the currents of the two detecting pixels is output inti (t) to the operational amplifier multiplexing circuit 30, for the difference I of the pixel current inti (t) integration is performed due to the correlation of the detected information between adjacent pixels, i.e. I S (t) and I si The difference I between (t) inti (t) is small, and on the basis of a multi-channel bit serial conversion structure, 8-bit digital codes can be converted and converted in sequence to represent detection pixels R si And a detection pixel R s The difference between the detection information of (a) reduces the amount of data that the readout circuit needs to output.
In one embodiment of the invention, because in the multi-channel bit serial conversion, 1bit digital code is output in each comparison, based on the characteristic, the specific compression bit number can be changed according to actual needs. When a certain detection bridge of the detection bridge matrix 20 and the reference detection bridge 10 form a bridge, the difference value I is judged inti (t) whether all the 8-bit digital codes converted out are '1' or not, if all the 8-bit digital codes are '1', the overflow error is determined to exist, i.e. the difference value I inti (t) too large, the range of 8-bit digital code can not cover the value, the expansion of compression bit number is needed in the analog-to-digital conversion of the next frame, the expansion method is to increase the comparison timesThe number of the compressed digital code can be continuously adjusted from 8 bits to 13 bits by changing the transformation rule of the BITX signal. Accordingly, if the difference is I inti (t) is too small, and the value can be expressed without 8-bit digital codes, so that the comparison times can be reduced, and the number of compressed digital codes can be reduced.
In one embodiment of the invention, when the difference value of two pixel signals is subjected to analog-to-digital conversion, the conversion rule of the BITX signal is changed by increasing or reducing the comparison times, the compression bit number can be expanded, the information loss caused by the fixed compression bit number is avoided, and compared with the fixed compression bit number, the compression structure has flexibility.
The embodiment of the invention has a data compression structure, reduces the data volume of analog-to-digital conversion of the readout circuit, relieves the problem of large data volume and high-speed output of the readout circuit, avoids the use of high-speed interfaces such as LVDS (Low Voltage differential Signaling) and the like in the traditional large-area array readout circuit, and has the advantages that the bit number of a compressed digital code is variable by changing the comparison times on the basis of multi-channel bit serial conversion, so that the embodiment has flexibility and avoids the problem of information loss caused by no fixed compression bit number.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. An infrared focal plane pixel level digital reading circuit is characterized by comprising a reference detection bridge for providing bias voltage for a reference pixel and a detection bridge matrix for providing bias voltage for a side pixel adjacent to the reference pixel,
the detection bridge matrix comprises a plurality of detection bridge branches which are independently arranged, and any detection bridge branch can form a bridge structure with the reference detection bridge through a switch;
the reference detection bridge works independently and transmits current containing detection information to the operational amplifier multiplexing circuit; when the reference detection bridge does not work independently, the difference between the currents of the detection bridge branch and the reference detection bridge is transmitted to the operational amplifier multiplexing circuit;
also comprises an operational amplifier multiplexing circuit and a signal latch circuit,
the operational amplifier multiplexing circuit can be switched between a capacitance transconductance amplifier mode and a comparator mode; the capacitive transconductance amplifier mode integrates the current output by the reference detection bridge or the detection bridge matrix; the comparator mode compares the integrated voltage with the ramp voltage and outputs the result to the signal latch circuit as a latch enable signal, the latch signal of which is a BITX signal.
2. The infrared focal plane pixel level digital readout circuit of claim 1, wherein the reference detection bridge comprises a first blind pixel element R b A first PMOS transistor MP eb A first NMOS transistor MN sel A second NMOS transistor MN fid A first detection pixel R s A third switch S3 and a fourth switch S4, the first blind pixel element R b Is connected with a first bias voltage Vsk, the first blind pixel element R b And the other end of the first PMOS transistor MP eb Is connected to the source of the first PMOS transistor MP eb And the first NMOS transistor MN sel Is connected to the drain of the first NMOS transistor MN sel And the second NMOS transistor MN fid Drain electrode of the second NMOS transistor MN fid Through the third switch S3 and the second NMOS transistor MN fid The second NMOS transistor MN fid Through the fourth switch S4 and a second bias voltage V fid Connected, the second NMOS transistor MN fid And the first detection pixel R s Is connected to the first detection pixel R s Is connected to a power ground GND, said first PMOS transistor MP eb And a third bias voltage V eb And (4) connecting.
3. The infrared focal plane pixel level digitizing readout circuit of claim 2, wherein the output of the reference detection bridge is the first NMOS transistor MN sel When the reference detection bridge works independently, a switch arranged between the reference detection bridge and the detection bridge matrix is switched off, and the value of the input current of the operational amplifier multiplexing circuit is equal to the value of the input current flowing through the first blind pixel R b Current and current flowing through the first detection pixel element R s The difference between the currents.
4. An infrared focal plane pixel level digitizing readout circuit according to claim 2 or 3, characterized in that the detection bridge matrix comprises a plurality of detection bridge branches of the same structure, the detection bridge branches comprising the second blind pixel elements R bi A second PMOS transistor MP ebi A third NMOS transistor MN seli A fourth NMOS transistor MN fidi A second detection pixel R si A first switch S1 i And a second switch S2 i The second blind pixel element R bi Is connected with the first bias voltage Vsk, and the second blind pixel element R bi And the other end of the second PMOS transistor MP ebi The source of the second PMOS transistor MP ebi And the third NMOS transistor MN seli The drain of the third NMOS transistor MN is connected seli And the fourth NMOS transistor MN fidi The drain of the fourth NMOS transistor MN is connected fidi Is connected to the second detection pixel R si Is connected to the second detection pixel R si Is connected to the power ground GND, the second PMOS transistor MP ebi Through the first switch S1 i And the first PMOS transistor MP eb Gate connection of the fourth NMOS transistor MN fidi Through the switch S2 i Is connected to the stationThe second NMOS transistor MN fid A gate electrode of (1).
5. The infrared focal plane pixel level digitizing readout circuit of claim 4, wherein the output of the detection bridge branch is the third NMOS transistor MN seli When the reference detection bridge does not work independently, a switch arranged between the reference detection bridge and the detection bridge matrix is closed, and the value of the input current of the operational amplifier multiplexing circuit is equal to the value of the input current flowing through the second detection pixel R si And flows through the first detection pixel R s The difference in current of (2).
6. The infrared focal plane pixel level digital readout circuit of claim 1, wherein the operational amplifier multiplexing circuit comprises an operational amplifier Opamp, an integrating capacitor C, a reset switch RST, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, and a tenth switch S int1 And an eleventh switch S int2 The output end of the reference detection bridge passes through the tenth switch S int1 Connected to the inverting input of the operational amplifier Opamp, the output of the detection bridge matrix is connected via the eleventh switch S int2 Connected to the inverting input terminal of the operational amplifier Opamp, the non-inverting input terminal of the operational amplifier Opamp is connected to the reference voltage V through the eighth switch S8 and the ninth switch S9 Ref And a ramp voltage V Ramp The integrating capacitor C and the reset switch RST are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier Opamp, and the end of the parallel link of the integrating capacitor C and the reset switch RST connected to the output terminal of the operational amplifier Opamp is connected to the reference voltage V through the fifth switch S5 Ref Meanwhile, the sixth switch S6 is arranged between the parallel link of the integrating capacitor C and the reset switch RST and the output end of the operational amplifier Opamp, and the output end of the operational amplifier Opamp is connected with the signal latch circuit through the seventh switch S7.
7. An infrared focal plane pixel level digital readout method using the readout circuit of any of claims 1-6, comprising the steps of:
step 1, the operational amplifier multiplexing circuit outputs current I when independently working to the reference detection bridge int (t) integrating, then performing analog-to-digital conversion, and sequentially converting N-bit digital codes through the signal latch circuit;
step 2, the operational amplifier multiplexing circuit outputs current I when the reference detection bridge does not work independently inti (t) integrating, then performing analog-to-digital conversion, and sequentially converting M-bit digital codes through the signal latch circuit, wherein M, N are positive integers, and M is less than or equal to N;
and 3, adjusting the comparison times of the BITX signal and the analog-to-digital conversion to adjust the value of M, so that the number of each digit of the digital code converted by the integral of the output current Iinti (t) when the reference detection bridge does not work independently is not 1.
8. The infrared focal plane pixel level digital readout method of claim 7, wherein the operational amplifier multiplexing circuit comprises an operational amplifier Opamp, an integrating capacitor C, a reset switch RST, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, and a tenth switch S int1 And an eleventh switch S int2 The output end of the reference detection bridge passes through the tenth switch S int1 Connected to the inverting input of the operational amplifier Opamp, the output of the detection bridge matrix is connected via the eleventh switch S int2 Is connected to the inverting input terminal of the operational amplifier Opamp, and the non-inverting input terminal of the operational amplifier Opamp is connected to the reference voltage V through the eighth switch S8 and the ninth switch S9 Ref And a ramp voltage V Ramp The integrating capacitor C and the reset switch RST are connected in parallel between the inverting input end and the output end of the operational amplifier Opamp, and the parallel link of the integrating capacitor C and the reset switch RST and the operational amplifier OOne end of the pamp connected with the output end is connected with the reference voltage V through the fifth switch S5 Ref Meanwhile, the sixth switch S6 is arranged between the parallel link of the integrating capacitor C and the reset switch RST and the output end of the operational amplifier Opamp, and the output end of the operational amplifier Opamp is connected with the signal latch circuit through the seventh switch S7.
9. The method as claimed in claim 8, wherein in step 1, the operational amplifier multiplexing circuit outputs current I when the reference detection bridge operates independently int (t) the integration is specifically: the sixth switch S6, the eighth switch S8 and the tenth switch S int1 Closed, and the fifth switch S5, the seventh switch S7, the ninth switch S9 and the eleventh switch S are turned on int2 Switching off to enable an integrating capacitor C in the operational amplifier multiplexing circuit to integrate the output current of the reference detection bridge;
in step 2, the operational amplifier multiplexing circuit outputs current I when the reference detection bridge does not work independently inti (t) the integration is specifically: the sixth switch S6, the eighth switch S8 and the eleventh switch S int2 Closing the fifth switch S5, the seventh switch S7, the ninth switch S9 and the tenth switch S int1 And switching off, so that an integrating capacitor C in the operational amplifier multiplexing circuit integrates the difference between the output current of the detection bridge matrix and the output current of the reference detection bridge.
10. The method according to claim 8 or 9, wherein in step 1 and step 2, the performing analog-to-digital conversion on the integrated current by the operational amplifier multiplexing circuit specifically comprises: the sixth switch S6 and the eighth switch S8 are opened, the fifth switch S5, the seventh switch S7, and the ninth switch S9 are closed, and the integrated voltage of the integrating capacitor C is compared with the ramp voltage.
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| CN103776544B (en) * | 2014-01-09 | 2016-07-27 | 电子科技大学 | A kind of reading circuit of un-cooled infrared focal plane array |
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| CN107727243B (en) * | 2017-11-22 | 2019-12-10 | 北方广微科技有限公司 | Uncooled infrared focal plane array readout circuit |
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