CN116437231A - Pixel-level space difference acquisition circuit, method and image sensor array - Google Patents

Pixel-level space difference acquisition circuit, method and image sensor array Download PDF

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CN116437231A
CN116437231A CN202310296074.3A CN202310296074A CN116437231A CN 116437231 A CN116437231 A CN 116437231A CN 202310296074 A CN202310296074 A CN 202310296074A CN 116437231 A CN116437231 A CN 116437231A
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pixel
level
current mirror
spatial differential
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杜刚
任旭
刘力桥
何燕冬
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Peking University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract

The application discloses a pixel-level space difference acquisition circuit, a pixel-level space difference acquisition method and an image sensor array. The pixel-level space differential acquisition circuit provided by the embodiment of the application comprises a comparator and a plurality of current-type multiplication units, wherein the positive current output end of each current-type multiplication unit is connected with the first input end of the comparator, the negative current output end of each current-type multiplication unit is connected with the second input end of the comparator, the space differential calculation of pixel signals can be realized through the pixel-level current reading and column-level current-type space differential calculation circuit, and the pixel-level space differential calculation circuit can be applied to space information compression algorithms such as edge detection and the like, so that the consumption of bandwidth and power consumption caused by unnecessary data movement of an image sensor is reduced.

Description

Pixel-level space difference acquisition circuit, method and image sensor array
Technical Field
The application relates to the technical field of image signal processing, in particular to a pixel-level space difference acquisition circuit, a pixel-level space difference acquisition method and an image sensor array.
Background
In the context of continuous development of internet of things, in-sense computation or proximity computation performed inside a sensor is considered as a development direction of internet of things equipment in the future. The related art image sensing and processing system quantizes and converts the complete image signal into a digital signal and then sends the digital signal to the digital processing chip for calculation, wherein a large amount of redundant data which is unnecessary for calculation exists, and the redundant data occupies extra bandwidth and consumes unnecessary power consumption.
Disclosure of Invention
The invention aims to provide a pixel-level spatial differential acquisition circuit, a pixel-level spatial differential acquisition method and an image sensor array, so as to relieve the conditions that redundant data in the related technology occupy extra bandwidth and consume unnecessary power consumption. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to an aspect of an embodiment of the present application, there is provided a pixel-level spatial difference acquisition circuit including a comparator and a plurality of current-type multiplication units; the positive current output end of each current type multiplication operation unit is connected with the first input end of the comparator; and the negative current output end of each current type multiplication operation unit is connected with the second input end of the comparator.
In some embodiments of the present application, the current-mode multiplication unit includes an operational amplifier, a cascode transistor, a first current mirror, and a second current mirror connected in sequence.
In some embodiments of the present application, the first current mirror includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with each other; the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with each other; the drain electrode of the third PMOS tube is connected with the drain electrode of the cascode transistor; and the drain electrode of the second PMOS tube is connected with the second current mirror.
In some embodiments of the present application, the second current mirror includes a first NMOS transistor and a second NMOS transistor; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube; the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube and the first current mirror.
In some embodiments of the present application, the first current mirror comprises a cascode current mirror or a wilson current mirror, and the second current mirror comprises a cascode current mirror or a wilson current mirror.
In some embodiments of the present application, a switch is connected between the drain and the source of the third PMOS transistor.
In some embodiments of the present application, a switch is connected between the source and the drain of the first NMOS transistor.
According to another aspect of an embodiment of the present application, there is provided an image sensor array including a current-type pixel array, a switch array, a spatial differential calculation unit, and an analog-to-digital conversion unit connected in this order, the spatial differential calculation unit including the pixel-level spatial differential acquisition circuit according to any one of claims 1 to 7; and the positive current output end and the negative current output end of each current type multiplication operation unit are connected with the analog-digital conversion unit.
In some embodiments of the present application, the current-mode pixel array includes a plurality of current-mode pixel units connected in parallel with each other; each current-type pixel unit comprises a photodiode, a reset tube, a source amplifier and a row selection transistor; the positive electrode end of the photodiode and one end of the reset tube are respectively connected with the grid electrode of the source amplifier; the drain of the source amplifier is connected to one end of the row select transistor.
According to another aspect of the embodiments of the present application, a pixel-level spatial differential acquiring method is provided, which is implemented by the pixel-level spatial differential acquiring circuit described in any one of the above; the acquisition method comprises the following steps:
inputting pixel current signals into corresponding current multiplication units, completing 1-bit weight calculation according to weights, shorting output positive current and negative current together, and realizing addition operation of current;
the comparator compares the positive current output end output signal and the negative current output end output signal of the current type multiplication unit to determine a sign bit;
and obtaining a pixel-level space difference calculation result according to the addition operation result and the sign bit.
One of the technical solutions provided in one aspect of the embodiments of the present application may include the following beneficial effects:
the pixel-level space differential acquisition circuit provided by the embodiment of the application comprises a comparator and a plurality of current-type multiplication units, wherein the positive current output end of each current-type multiplication unit is connected with the first input end of the comparator, the negative current output end of each current-type multiplication unit is connected with the second input end of the comparator, the space differential calculation of pixel signals can be realized through the pixel-level current reading and column-level current-type space differential calculation circuit, and the pixel-level space differential calculation circuit can be applied to space information compression algorithms such as edge detection and the like, so that the consumption of bandwidth and power consumption caused by unnecessary data movement of an image sensor is reduced.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a circuit diagram of a current-mode multiplication unit according to an embodiment of the present application.
Fig. 2 shows a block diagram of a pixel-level spatial differential acquisition circuit according to one embodiment of the present application.
Fig. 3 shows a schematic diagram of the relation of weights and control signals in one example of the present application.
FIG. 4 illustrates an array horizontal shift calculation schematic in one example of the present application.
FIG. 5 illustrates a timing diagram of a calculation module and rank control in one example of the present application.
FIG. 6 shows a block diagram of an image sensor array architecture according to one embodiment of the present application.
Fig. 7 shows a circuit diagram of a pixel structure in one example of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the related art, an image sensing and processing system completes photoelectric conversion through a CMOS active pixel, realizes digitization through an analog-digital conversion module, and finally sends digital signals to a digital image processing chip to perform further functions such as face recognition and motion detection. The related art image sensing and processing system quantizes and converts the complete image signal into a digital signal and then sends the digital signal to the digital processing chip for calculation, wherein a large amount of redundant data exists, and the redundant data occupies extra bandwidth to consume unnecessary power consumption. For intelligent recognition systems, there is a large amount of computation-independent data in the raw data, which occupies additional bandwidth and consumes unnecessary power. At the front end of the analog-to-digital converter, the integral data movement amount of the system can be reduced and the integral energy efficiency of the system can be improved by carrying out feature extraction and data compression on analog signals generated by pixels.
One embodiment of the application provides a pixel-level space difference acquisition circuit, which comprises a comparator and a plurality of current-type multiplication units; the positive current output end of each current type multiplication operation unit is connected with the first input end of the comparator; and the negative current output end of each current type multiplication operation unit is connected with the second input end of the comparator.
Illustratively, the current-mode multiplication unit includes an operational amplifier, a cascode transistor, a first current mirror, and a second current mirror connected in sequence.
Illustratively, the first current mirror includes a first PMOS tube, a second PMOS tube, and a third PMOS tube; the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with each other; the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with each other; the drain electrode of the third PMOS tube is connected with the drain electrode of the cascode transistor; and the drain electrode of the second PMOS tube is connected with the second current mirror.
Illustratively, the second current mirror includes a first NMOS transistor and a second NMOS transistor; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube; the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube and the first current mirror.
Illustratively, the first current mirror comprises a cascode current mirror or a wilson current mirror, and the second current mirror comprises a cascode current mirror or a wilson current mirror. A switch is connected between the drain electrode and the source electrode of the third PMOS tube, and a switch is connected between the source electrode and the drain electrode of the first NMOS tube.
FIG. 1 shows a 1-bit (bit) current-type multiplication circuit structure diagram for realizing a spatial differential algorithm in one embodiment of the application, which mainly comprises an operational amplifier and 1 cascodeTransistors, 5 transistors with current mirror function and 4 transistors with switch function. Wherein NM is marked as NMOS, PM is marked as PMOS, and all switches are NMOS switches. Pixel generated current signal I pix Connected to the negative input of the operational amplifier AMP, flows through the cascode transistor NM0 into a first current mirror structure consisting of PM0, PM1 and PM2 and a second current mirror structure consisting of NM1 and NM2, wherein the aspect ratio of the transistors of each current mirror is the same, respectively. The 4 switches are controlled by SP, SN and SZ signals, respectively, wherein the SP and SN signals are determined by weights, respectively representing weights 1 and-1, and SZ represents weights 0, and when both SP and SN are 0, the SZ will be 0. When the weight is 1, SP is closed and the pixel current is output to I through PM0 and PM1 P A node outputting positive current, and NM1 and NM2 branches are reset to VSS due to the gate terminal, and the current is 0; when the weight is-1, SN is closed, and the pixel current is output to I through PM0, PM2 and NM1, NM2 N A node outputting a negative current; when the weight is 0, SZ is closed, and the gate terminal voltages of PM1 and PM2 are clamped to be VDD, so that no current flows on the branch, and the function of power consumption management is realized.
Fig. 2 shows a spatial differential calculation circuit for implementing 3×3 convolution IN a specific example, where each PE is implemented by the circuit shown IN fig. 1, the module inputs current signals of 3×3 pixels to corresponding multiplication units respectively, 1bit (bit) weight calculation is completed according to the weight, positive current and negative current output are respectively shorted together to implement addition operation of the current, and total positive current and negative current of the 3×3 module respectively correspond to IP and IN the graph.
In the SIGN bit determining stage, S_COMP is closed, S_SAMPLE is opened, positive current and negative current are sent into a current comparator to be compared, and 1bit SIGN is generated; sign=1 when the positive current is greater than the negative current, and sign=0 when the negative current is greater than the positive current.
In the sampling stage, S_SAMPLE is closed, S_COMP is opened, and if the SIGN bit SIGN is 1, the signal is directly sent into the ADC for quantization and subsequent operation without changing a control signal; if the SIGN bit SIGN is 0, the input signal of the ADC is made positive by digitally controlling the flip control signal. For example, when the input weight is 1, there are sp=1, sn=0, sz=0 in the sampling phase, and when sign=0, the switch is adjusted to sp=0, sn=1, sz=0 in the calculation phase. This ensures that the signals received by the ADC are all positive signals, and the control part is implemented in a state machine, which can be implemented by a digital circuit.
The control signal can be realized by a state machine in the chip to realize the reconfigurable weight, the SP is controlled to be closed to realize the weight 1, the SN is controlled to be closed to realize the weight-1, and the SZ is controlled to be closed to realize the weight 0.
Fig. 3 is a schematic diagram showing a correspondence between weights and control signals in a specific example, for example, when the convolution kernel is a Prewitts algorithm as shown in the figure, the corresponding control switch in an operating state is as shown in the figure, the position of 1 in the convolution kernel corresponds to sp=1, the position of-1 corresponds to sn=1, and the position of 0 corresponds to sz=1.
FIG. 4 is a schematic diagram of the array calculation, and FIG. 5 is a timing diagram of the calculation module and the row and column control. When the calculation step length is 1, each time of horizontal shift is 1bit, three rows of space difference calculation can be completed through three periods, and when the column width is n, the space difference calculation needs to be completed
Figure BDA0004143211870000061
And a spatial difference calculation module. The control signals include calculation flow control signals and weight signals, wherein the calculation flow control signals include control signals of S_SAMPLE, S_COMP, S_CAL1, S_CAL2 and S_CAL3. The computation flow control signal is implemented by a state machine. The weight signals include SN, SP and SZ, which are typically off-chip into a state machine buffer for provision to the computation module in order to implement configurable weights. The state machine may be implemented by digital circuitry and operates in the manner described with reference to the timing diagram of fig. 5.
Another embodiment of the present application provides a pixel-level spatial differential acquiring method, which is implemented by the pixel-level spatial differential acquiring circuit of any one of the above embodiments; the acquisition method comprises the following steps:
inputting pixel current signals into corresponding current multiplication units, completing 1-bit weight calculation according to weights, shorting output positive current and negative current together, and realizing addition operation of current;
the comparator compares the positive current output end output signal and the negative current output end output signal of the current type multiplication unit to determine a sign bit;
and obtaining a pixel-level space difference calculation result according to the addition operation result and the sign bit.
In some examples, the pixel-level spatial differential may also be implemented, for example, by a switched capacitor circuit, where the switch is controlled to change the connection relationship of the circuit, and the voltage multiplication and addition is implemented by transferring charges on the capacitor, so as to complete the extraction of the gradient characteristics. The space difference can realize the feature extraction of the space information and the compression of the redundant information, and is a main method for realizing the intra-sense calculation or the proximity calculation.
The embodiment of the application provides a pixel-level space differential acquisition circuit, which can realize space differential calculation of pixel signals through a pixel-level current reading and column-level current-type space differential calculation circuit, can be applied to space information compression algorithms such as edge detection and the like, and reduces the consumption of bandwidth and power consumption caused by unnecessary data movement of an image sensor. The spatial difference can extract gradient features, for example, some gradient features of the center pixel.
Another embodiment of the present application provides an image sensor array, including a current-type pixel array, a switch array, a spatial differential computing unit, and an analog-to-digital conversion unit that are sequentially connected, where the spatial differential computing unit includes the pixel-level spatial differential acquiring circuit described in any one of the above embodiments; and the positive current output end and the negative current output end of each current type multiplication operation unit are connected with the analog-digital conversion unit.
In one embodiment, the current-mode pixel array includes a plurality of current-mode pixel units connected in parallel with each other; each current-type pixel unit comprises a photodiode, a reset tube, a source amplifier and a row selection transistor; the positive electrode end of the photodiode and one end of the reset tube are respectively connected with the grid electrode of the source amplifier; the drain of the source amplifier is connected to one end of the row select transistor.
FIG. 6 illustrates an image sensor array implemented based on spatial differential circuitry in one example. To maximize the benefits of current mode computation, the pixel architecture employs a 3 transistor current mode pixel as shown in fig. 7, which includes a photodiode, a reset tube, a source amplifier, and a row select transistor.
In one embodiment, a method of operating the image sensor array includes: the current-mode multiplication operation unit clamps the source end of the source amplifier in the gated current-mode pixel unit at a low level, so that the source amplifier in the gated current-mode pixel unit works in a linear region; the photodiode linearly converts the photovoltage into a current signal and inputs the current signal into the switch array; the switch array respectively gates corresponding current signals according to externally input control signals to be input into the space differential calculation circuit; and the space difference calculation circuit performs space difference calculation, and the calculated result is quantized into a digital signal through the analog-to-digital conversion module and output.
In the structure shown in fig. 6, the operational amplifier clamps the source terminal of the source amplifier of the gate pixel at a low level (10 mV) to make the source amplifier work in a linear region, the photodiode linearly converts the photovoltage into a current signal, the current signal is input into the switch array, the corresponding current signals are respectively gated according to the array control signal and input into the spatial differential computing circuit, after the spatial differential computing circuit completes the computation, the computed result is quantized into a digital signal through the analog-to-digital conversion module and sent out of the chip. Therefore, space difference is realized in the image sensor, the data movement quantity is reduced, and the overall energy efficiency of the system is improved. The array control signals include control signals of s_cal1, s_cal2, and s_cal3 shown in the timing chart for controlling the switch array to access different columns in the pixels into the spatial differential calculation circuit. The array control signals are also implemented in the state machine.
The basic current mirror structure adopted by the embodiment of the application can be replaced by other current mirror structures, such as a cascode current mirror structure and a Wilson current mirror structure. The embodiment of the application realizes 1-bit (bit) weight, and can realize multi-bit (bit) weight through the proportional copy of the current mirror. The embodiment of the application realizes 3×3 space difference calculation, and can be expanded to convolution kernel calculation with other sizes, such as 2×2, 4×4 and the like.
Compared with voltage type array calculation, current type calculation has no limitation of voltage margin, and higher precision can be realized. The current type calculation is simpler in implementation mode, high-gain operational amplifier and capacitor are not needed, and occupied area is smaller. By designing proper power supply voltage and transistor size, the current mirror can work in a subthreshold area, and low power consumption is realized while the precision is ensured. The embodiment of the application realizes that the weight of the space difference is reconfigurable, and the reconstruction of the weight can be realized by controlling the switch control signal of each multiplication unit through digital logic, so that the space difference calculation of different convolution kernels can be realized.
It should be noted that:
the foregoing examples merely represent embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.

Claims (10)

1. The pixel-level space difference acquisition circuit is characterized by comprising a comparator and a plurality of current-type multiplication units; the positive current output end of each current type multiplication operation unit is connected with the first input end of the comparator; and the negative current output end of each current type multiplication operation unit is connected with the second input end of the comparator.
2. The pixel-level spatial differential acquisition circuit according to claim 1, wherein the current-type multiplication unit comprises an operational amplifier, a cascode transistor, a first current mirror, and a second current mirror, which are sequentially connected.
3. The pixel-level spatial differential acquisition circuit of claim 2, wherein the first current mirror comprises a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with each other; the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with each other; the drain electrode of the third PMOS tube is connected with the drain electrode of the cascode transistor; and the drain electrode of the second PMOS tube is connected with the second current mirror.
4. The pixel-level spatial differential acquisition circuit of claim 2, wherein the second current mirror comprises a first NMOS transistor and a second NMOS transistor; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube; the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube and the first current mirror.
5. The pixel-level spatial differential acquisition circuit of claim 2, wherein the first current mirror comprises a cascode current mirror or a wilson current mirror and the second current mirror comprises a cascode current mirror or a wilson current mirror.
6. The pixel-level spatial differential acquisition circuit according to claim 3, wherein a switch is connected between the drain and the source of the third PMOS transistor.
7. The pixel-level spatial differential acquisition circuit according to claim 4, wherein a switch is connected between the source and the drain of the first NMOS transistor.
8. An image sensor array, comprising a current-type pixel array, a switch array, a spatial differential computing unit and an analog-to-digital conversion unit, which are sequentially connected, wherein the spatial differential computing unit comprises the pixel-level spatial differential acquiring circuit according to any one of claims 1 to 7; and the positive current output end and the negative current output end of each current type multiplication operation unit are connected with the analog-digital conversion unit.
9. The image sensor array of claim 8, wherein the current-mode pixel array comprises a plurality of current-mode pixel cells connected in parallel with one another; each current-type pixel unit comprises a photodiode, a reset tube, a source amplifier and a row selection transistor; the positive electrode end of the photodiode and one end of the reset tube are respectively connected with the grid electrode of the source amplifier; the drain of the source amplifier is connected to one end of the row select transistor.
10. A pixel-level spatial differential acquisition method, characterized by being implemented by a pixel-level spatial differential acquisition circuit as claimed in any one of claims 1-7; the acquisition method comprises the following steps:
inputting pixel current signals into corresponding current multiplication units, completing 1-bit weight calculation according to weights, shorting output positive current and negative current together, and realizing addition operation of current;
the comparator compares the positive current output end output signal and the negative current output end output signal of the current type multiplication unit to determine a sign bit;
and obtaining a pixel-level space difference calculation result according to the addition operation result and the sign bit.
CN202310296074.3A 2023-03-23 2023-03-23 Pixel-level space difference acquisition circuit, method and image sensor array Pending CN116437231A (en)

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