CN115855271B - Readout circuit with large charge processing capability and infrared thermal imaging instrument - Google Patents
Readout circuit with large charge processing capability and infrared thermal imaging instrument Download PDFInfo
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- CN115855271B CN115855271B CN202310145779.5A CN202310145779A CN115855271B CN 115855271 B CN115855271 B CN 115855271B CN 202310145779 A CN202310145779 A CN 202310145779A CN 115855271 B CN115855271 B CN 115855271B
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Abstract
The invention provides a readout circuit with large charge processing capability and an infrared thermal imager, wherein an infrared detection module converts infrared light into current, the current is input into an integrating capacitor module for integration when a first MOS tube is conducted, integrated charge is obtained, and the charge is transferred to a column integrator when a second MOS tube is conducted. The column integrator resets the column integration capacitor when the third MOS tube is conducted, receives charges through the column integration capacitor, obtains a voltage signal, and outputs the voltage signal when the fourth MOS tube is conducted. According to the invention, the third MOS tube for resetting can be moved outside the pixel level unit circuit, and the integrating capacitor module in the pixel level unit circuit is indirectly reset through the operational amplifier, so that the number of transistors in the pixel level unit circuit is reduced, the area of the integrating capacitor module in the pixel area is maximized, the integrating charge quantity of the detector pixel is improved, and the temperature sensitivity of the infrared imager is improved.
Description
Technical Field
The invention belongs to the technical field of infrared thermal imaging, and particularly relates to a readout circuit with large charge processing capability and an infrared thermal imager.
Background
The infrared focal plane detector component is an important photoelectric device for acquiring infrared thermal radiation information of a target scene, and is an important component of the infrared thermal imager. The core component of the infrared focal plane detector assembly is an infrared focal plane detector chip set. The infrared focal plane detector chip set is formed by flip-chip interconnection of an infrared focal plane array (Focal Plane Array, FPA) chip and a readout circuit chip via indium columns. The basic function of the readout circuit chip is to pre-amplify the electrical signals converted by the pixels of the infrared detector array chip, and then serially read out the signals through one or more output buffers (also called multiplexers).
The typical read-out circuit mainly comprises an MXN input stage unit circuit array, a column level sampling-holding circuit, a row and column level shift register, an output amplifying level and the like. In order to obtain dynamic continuous distribution information of target thermal radiation, a high-performance readout circuit generally adopts a Snapshot (snappshot) integration mode, and an integration capacitor is used for integrating a photosensitive current in an input stage unit circuit.
The signal-to-noise ratio of the infrared detector follows the following law: under the condition that the background radiation is certain and the photocurrent is relatively unchanged, the larger the integral charge quantity is, the longer the integral time is, the larger the signal-to-noise value of the infrared detector is, and the higher the temperature sensitivity performance of the infrared thermal imager is.
Typically, the integration capacitance occupies about 70% -80% of the area of the input stage cell of the readout circuit, which is a primary consideration in the design of the readout circuit. Because the MOS capacitor has a higher cell capacitance value, the MOS capacitor is typically used as the integrating capacitor in the input stage unit of the existing readout circuit. However, in the case where the area occupation of the integrating capacitor is relatively large in the limited pixel area, it is difficult to further improve the temperature sensitivity performance of the thermal infrared imager.
Disclosure of Invention
In order to solve the problems, the invention provides a readout circuit with large charge processing capability and a thermal infrared imager.
In a first aspect of the present invention, there is provided a readout circuit having a large charge processing capability, comprising: a plurality of pixel-level unit circuits arranged in a matrix form, and a plurality of column-level integrators respectively corresponding to the pixel-level unit circuits of a plurality of columns in the matrix;
the pixel level unit circuit comprises an infrared detection module, an integrating capacitor module, a first MOS tube and a second MOS tube;
the infrared detection module is used for converting infrared light into current, and inputting the current into the integrating capacitor module for integrating when the first MOS tube is conducted, so as to obtain integrated charge;
the integrating capacitor module is used for transferring the integrated charge to the column integrator when the second MOS tube is conducted;
the column-level integrator comprises a rail-to-rail operational amplifier, a third MOS tube, a fourth MOS tube and a column-level integrating capacitor;
the output end of the integrating capacitor module is connected with the negative input end of the rail-to-rail operational amplifier, the column integrator is used for resetting the column integrating capacitor when the third MOS tube is conducted, receiving the integrated charge through the column integrating capacitor, obtaining a voltage signal, and outputting the voltage signal when the fourth MOS tube is conducted.
In one possible implementation, the infrared detection module includes an N-on-P type infrared detector, or a P-on-N type infrared detector.
In one possible implementation manner, in the case that the infrared detection module is the N-on-P type infrared detector, the reference voltage of the anode of the rail-to-rail operational amplifier is a power supply voltage.
In one possible implementation manner, in the case that the infrared detection module is the P-on-N type infrared detector, the reference voltage of the positive electrode of the rail-to-rail operational amplifier is a ground voltage.
In one possible implementation manner, the integrating capacitor module comprises a MOS capacitor and a MIM capacitor which are connected in parallel, and the MIM capacitor and the MOS capacitor adopt an upper-lower three-dimensional layout manner.
In one possible implementation, the charge handling capability of the pixel level cell circuit is represented by the formula qmax=vdda× (c_mos+c_mim), where Qmax is the maximum value of the integrated charge, VDDA is the supply voltage, c_mos is the capacitance value of the MOS capacitor, and c_mim is the capacitance value of the MIM capacitor.
In one possible implementation manner, after the third MOS transistor is turned on, the first MOS transistor is turned on, after the first MOS transistor is turned on, the second MOS transistor is turned on, and after the second MOS transistor is turned on, the fourth MOS transistor is turned on.
In one possible implementation, the third MOS transistor and the column-level integrating capacitor are connected in parallel and connected across the negative input and output of the rail-to-rail operational amplifier.
In one possible implementation, the rail-to-rail operational amplifier includes at least one set of NMOS differential pair structures and at least one set of PMOS differential pair structures.
In a second aspect of the present invention, there is provided a thermal infrared imager comprising: an infrared focal plane array chip and the readout circuit with large charge processing capability.
According to the readout circuit with large charge processing capability, the third MOS tube for resetting is moved out of the pixel level unit circuit, the integral capacitor module in the pixel level unit circuit is indirectly reset through the performance of operational amplification, the number of transistors in the pixel level unit circuit is reduced, the area of the integral capacitor module in the pixel area is maximized, MOS capacitors and MIM capacitors which are connected in parallel and in a layout mode of an upper three-dimensional layout and a lower three-dimensional layout are used as integral capacitors, and therefore the integral charge quantity of the detector pixel is improved, and the temperature sensitivity performance of an infrared imager is improved. And the integrated charge can be completely converted into a voltage signal by using a rail-to-rail operational amplifier and a column-level integrating capacitor, and high linearity is realized in a full voltage range, so that the performances of a reading circuit and an infrared thermal imager are improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it will be obvious that the drawings in the following description are some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive effort to a person skilled in the art,
FIG. 1 is a schematic diagram of a pixel level cell circuit according to the present invention;
FIG. 2 is a schematic diagram of a column-level integrator provided by the present invention;
FIG. 3 is a schematic diagram of a rail-to-rail operational amplifier provided by the present invention;
FIG. 4 is a timing diagram of signals provided by the present invention;
fig. 5 is a schematic diagram of a thermal infrared imager provided by the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In one possible implementation, to further enhance the temperature sensitivity performance of the thermal infrared imager, the present invention provides a readout circuit with a large charge processing capability, the readout circuit with a large charge processing capability comprising: a plurality of pixel-level unit circuits arranged in a matrix form, and a plurality of column-level integrators respectively corresponding to the pixel-level unit circuits of a plurality of columns in the matrix;
the pixel level unit circuit comprises an infrared detection module, an integrating capacitor module, a first MOS tube and a second MOS tube;
the infrared detection module is used for converting infrared light into electric charge, and inputting the electric charge into the integrating capacitor module for integrating when the first MOS tube is conducted;
the integrating capacitor module is used for transferring the integrated charge to the column integrator when the second MOS tube is conducted;
the column-level integrator comprises a rail-to-rail operational amplifier, a third MOS tube, a fourth MOS tube and a column-level integrating capacitor;
the output end of the integrating capacitor module is connected with the negative input end of the rail-to-rail operational amplifier, the column integrator is used for resetting the column integrating capacitor when the third MOS tube is conducted, receiving the integrated charge through the column integrating capacitor, obtaining a voltage signal, and outputting the voltage signal when the fourth MOS tube is conducted.
According to the readout circuit with large charge processing capability, the third MOS tube for resetting is moved out of the pixel level unit circuit, and the integration capacitance module in the pixel level unit circuit is indirectly reset through the performance of the operational amplifier, so that the number of transistors in the pixel level unit circuit is reduced, the area of the integration capacitance module in the pixel area is maximized, the integrated charge quantity of the detector pixel is improved, and the temperature sensitivity performance of the infrared imager is improved. And the integrated charge can be completely converted into a voltage signal by using a rail-to-rail operational amplifier and a column-level integrating capacitor, and high linearity is realized in a full voltage range, so that the performances of a reading circuit and an infrared thermal imager are improved.
Fig. 1 is a schematic diagram of a pixel level unit circuit provided by the invention, the pixel level unit circuit comprises an infrared detection module, an integration capacitance module, a first MOS tube M1 and a second MOS tube M2, the infrared detection module is connected with a source electrode of the first MOS tube M1, the integration capacitance module is connected with a drain electrode of the first MOS tube M1 and a source electrode of the second MOS tube M2, a drain electrode of the second MOS tube M2 is an output end OUT1 of the pixel level unit circuit, a grid electrode of the first MOS tube M1 is connected with a signal INT, and a grid electrode of the second MOS tube M2 is connected with a READ signal READ. The infrared detection module is configured to convert infrared light into current, that is, photosensitive current, and flow into the integrating capacitor module to perform integration processing when the first MOS transistor M1 is turned on, for example, when the signal INT of the gate of the first MOS transistor M1 is at a high level, the first MOS transistor M1 is turned on, so that the integrating capacitor module can perform integration processing on the photosensitive current. Further, when the second MOS transistor M2 is turned on, the integrated charge may be transferred to the column integrator, that is, to the column integrator corresponding to the column where the pixel unit circuit is located, for example, when the READ signal READ of the gate of the second MOS transistor M2 is at a high level, the second MOS transistor M2 is turned on, and the integrated charge may be output to the column integrator through the output terminal OUT1 of the pixel unit circuit.
In one possible implementation, as shown in FIG. 1, the infrared detection module includes an N-on-P type infrared detector, or a P-on-N type infrared detector. If the N-on-P type infrared detector is used, the N pole of the N-on-P type infrared detector is connected with the source electrode of the first MOS tube M1, and the P pole of the N-on-P type infrared detector is connected with the common electrode SUBPV. If the P-on-N type infrared detector is used, the P electrode of the P-on-N type infrared detector is connected with the source electrode of the first MOS tube M1, and the N electrode of the P-on-N type infrared detector is connected with the common electrode SUBPV.
In one possible implementation, as shown in fig. 1, the integrating capacitor module includes a MOS capacitor c_mos and a MIM capacitor c_mim connected in parallel, and the MIM capacitor and the MIM adopt an upper and lower three-dimensional layout. That is, when the two capacitors are arranged, the two capacitors can be arranged in parallel in the vertical direction, so that the occupied area of the two capacitors is further reduced, the area of the integral capacitor is increased, the integral charge quantity is increased, and the temperature sensitivity performance of the infrared imager is improved. One end of each of the two capacitors of the integrating capacitor module is grounded, and the other end of each of the two capacitors is connected with the drain electrode of the first MOS tube M1 and the source electrode of the second MOS tube M2.
Fig. 2 is a schematic diagram of a column-level integrator provided by the present invention. As shown in fig. 2, the column integrator includes a rail-to-rail operational amplifier a, a third MOS transistor M3, a fourth MOS transistor M4, and a column integrator capacitor C3. The output end OUT1 of the integrating capacitor module is connected with the negative input end Vin-of the rail-to-rail operational amplifier A, and the positive input end vin+ of the rail-to-rail operational amplifier A is connected with the reference voltage Vref.
In one possible implementation, as shown in fig. 2, the third MOS transistor M3 and the column-level integrating capacitor C3 are connected in parallel and connected across the negative input Vin-and the output of the rail-to-rail operational amplifier. The fourth MOS transistor M4 is arranged between the output end of the rail-to-rail operational amplifier A and the output end of the column integrator.
In one possible implementation manner, the column-level integrating capacitor C3 is reset when the third MOS transistor M3 is turned on, and in an example, when the gate of the third MOS transistor M3 is connected to the reset signal RST1, the RST1 is at a high level, the third MOS transistor M3 may be turned on, so that the column-level integrating capacitor C3 is reset. For example, during the reset process, the column level integrating capacitor C3 discharges the charges at both ends of the electrode, for example, discharges the charge introduced by the last pixel level cell circuit, and prepares to receive the charge introduced by the current pixel level cell circuit.
In one possible implementation, the column level integrating capacitor C3 may receive the charge introduced by the integrating capacitor module, so that a potential difference is formed across the column level integrating capacitor C3 to obtain a voltage signal. And, through the integration capacitor C3 of the column level, charge is converted into a voltage signal, so that the linearity of the voltage signal is improved. Further, the voltage signal may be output when the fourth MOS transistor is turned on, in an example, the gate of the fourth MOS transistor is connected to the signal col_sw, and when the signal col_sw is at a high level, the fourth MOS transistor is turned on, and the output terminal OUT of the column integrator outputs the voltage signal, for example, to the chip-level output bus. After the voltage signal is output, a process of receiving the charge of the next pixel level unit circuit, converting the charge into the voltage signal, and outputting the voltage signal can be performed.
In one possible implementation, the reference voltage Vref to which the positive input terminal vin+ of the rail-to-rail operational amplifier a is connected may be determined according to the type of the infrared detection module. In the case that the infrared detection module is the N-on-P type infrared detector, the reference voltage of the positive electrode of the rail-to-rail operational amplifier may be set as a power supply voltage. In the case that the infrared detection module is the P-on-N type infrared detector, the reference voltage of the positive electrode of the rail-to-rail operational amplifier may be set to a ground voltage.
In one possible implementation manner, before each pixel level unit circuit performs charge integration, the integrating capacitor module and the column level integrating capacitor C3 may be reset, as described above, when the third MOS transistor M3 is turned on, the column level integrating capacitor C3 may be reset, and meanwhile, the voltages of the positive input terminal vin+ and the negative input terminal Vin-of the rail operational amplifier a are equal or similar, so that the voltage at the positive input terminal vin+ is approximately equal to the reference voltage Vref, so that when the second MOS transistor M2 is turned on, the potential difference between the integrating capacitor module and the negative input terminal Vin-is approximately equal to the reference voltage Vref, thereby implementing resetting of the integrating capacitor module.
In an example, if the infrared detection module is a P-on-N type infrared detector, the reference voltage of the positive input terminal vin+ of the rail-to-rail operational amplifier a is the ground voltage GNDA, so that the voltage of the negative input terminal Vin-is also the ground voltage GNDA. After the first MOS tube is conducted, the photosensitive current of the P-on-N type infrared detector can charge the MOS capacitor C_MOS and the MIM capacitor C_MIM of the integrating capacitor module, so that the integrating capacitor module reaches or approaches to the power supply voltage VDDA, after the second MOS tube is conducted, the voltage of the negative input end Vin-of the rail-to-rail operational amplifier A is equal to or approaches to the ground voltage GNDA, so that the potential difference between the integrating capacitor module and the negative input end Vin-of the rail-to-rail operational amplifier A is equal to or approximately equal to the power supply voltage VDDA, and the integrated charge in the integrating capacitor module is transferred to a column integrator, such as a column integrator capacitor C3 in the column integrator, to form a voltage signal, and the voltage of the integrating capacitor module is reset to the ground voltage GNDA.
In an example, if the infrared detection module is an N-on-P type infrared detector, the reference voltage of the positive input terminal vin+ of the rail-to-rail operational amplifier a is the power supply voltage VDDA, so that the voltage of the negative input terminal Vin-is also the power supply voltage VDDA. After the first MOS tube is turned on, the photosensitive current of the N-on-P type infrared detector may bleed charges in the MOS capacitor c_mos and the MIM capacitor c_mim of the integrating capacitor module having a voltage equal to or approximately equal to the power supply voltage VDDA, for example, to reach or approach the ground voltage GNDA, and after the second MOS tube is turned on, since the voltage of the negative input terminal Vin-of the rail-to-rail operational amplifier a is equal to or approximately equal to the power supply voltage VDDA, the potential difference between the integrating capacitor module and the negative input terminal Vin-of the rail-to-rail operational amplifier a is equal to or approximately equal to the power supply voltage VDDA, so that the charges integrated in the integrating capacitor module are transferred to the column integrator, for example, the column integrator C3 in the column integrator, to form a voltage signal, and the voltage of the integrating capacitor module is reset to the power supply voltage VDDA.
In one possible implementation, the charge handling capability of the pixel level cell circuit is represented by equation (1) according to the reset and integration procedure above,
Qmax=VDDA×(C_MOS+C_MIM) （1）
wherein Qmax is the maximum value of the integrated charge, that is, the charge amount obtained by integrating the voltage of the integrating capacitor module with the power supply voltage VDDA. VDDA is the supply voltage, C_MOS is the capacitance of the MOS capacitor, and C_MIM is the capacitance of the MIM capacitor.
In one possible implementation, to increase the charge processing capability of the pixel-level unit circuit, the maximum value of the integrated charge is increased, so that the voltages of the positive input terminal vin+ and the negative input terminal Vin-of the rail-to-rail operational amplifier a are close to or almost equal to each other, and thus the charge processing capability of the pixel-level unit circuit can almost reach the maximum value Qmax of the integrated charge.
Fig. 3 is a schematic diagram of a rail-to-rail operational amplifier provided by the present invention. As shown in fig. 3, the rail-to-rail operational amplifier a includes at least one set of NMOS differential pair structures and at least one set of PMOS differential pair structures. In an example, the at least one set of NMOS differential pair structures includes a differential pair structure made up of NMOS transistors MN1 and MN2, a differential pair structure made up of NMOS transistors MN3 and MN4, and a differential pair structure made up of NMOS transistors MN5 and MN 6. The positive input end vin+ of the rail-to-rail operational amplifier A is the gate of the NMOS transistor MN1, and the negative input end Vin-of the rail-to-rail operational amplifier A is the gate of the NMOS transistor MN 2. The gates of the NMOS transistors MN5 and MN6 are connected with the drain of the NMOS transistor MN3, and the sources of the NMOS transistors MN5 and MN6 are grounded. The gates of NMOS transistors MN3 and MN4 are connected to bias voltage VBIAS5. The source of NMOS tube MN3 is connected with the drain of NMOS tube MN5, and the source of NMOS tube MN4 is connected with the drain of NMOS tube MN 6. The drain of NMOS tube MN4 connects the rail to the output terminal Vout of rail operational amplifier A.
In an example, the at least one set of PMOS differential pair structures includes a differential pair structure formed by PMOS transistors MP1 and MP2, a differential pair structure formed by PMOS transistors MP3 and MP4, and a differential pair structure formed by PMOS transistors MP5 and MP 6. The gate of the PMOS tube MP1 is connected with the positive input end Vin+ of the rail-to-rail operational amplifier A, the gate of the PMOS tube MP2 is connected with the negative input end Vin-of the rail operational amplifier A, the sources of the PMOS tubes MP1 and MP2 are connected with the drain of the NMOS tube MN7, the gate of the NMOS tube MN7 is connected with the bias voltage VBIAS2, and the source of the NMOS tube MN7 is grounded. The drains of the PMOS pipes MP1 and MP2 are connected with the source of the PMOS pipe MP7, the grid electrode of the PMOS pipe MP7 is connected with the bias voltage VBIAS1, and the drain electrode of the PMOS pipe MP7 is connected with the power supply voltage VDDA. The gates of the PMOS pipes MP3 and MP4 are connected with bias voltage VBIAS3, the drain is connected with power supply voltage VDDA, the source of the PMOS pipe MP3 is connected with the drain of the PMOS pipe MP5 and the drain of the NMOS pipe MN2, and the source of the PMOS pipe MP4 is connected with the drain of the PMOS pipe MP6 and the drain of the NMOS pipe MN 1. The gates of the PMOS tubes MP5 and MP6 are connected with the bias voltage VBIAS4, the source of the PMOS tube MP5 is connected with the drain of the NMOS tube MN3 and the gates of the NMOS tubes MN5 and MN6, and the PMOS tube MP6 is connected with the output end Vout of the rail-to-rail operational amplifier A.
In one possible implementation, based on the above connection, the negative input Vin-of the rail-to-rail operational amplifier a may be equal to or very close to the supply voltage when the reference voltage is the supply voltage due to the input common mode voltage of the NMOS differential pair structure. Because of the input common mode voltage of the PMOS differential pair structure, when the reference voltage is the ground voltage, the negative input terminal Vin-of the rail-to-rail operational amplifier a can be equal to or very close to the ground voltage.
Fig. 4 is a signal timing diagram provided by the present invention. As shown in fig. 4, the reset signal RST1 connected to the third MOS transistor M3 first rises to a high level, the signal INT connected to the first MOS transistor M1 rises to a high level after the reset signal RST1 falls to a low level, the signal READ connected to the second MOS transistor M2 rises to a high level after the signal INT falls to a low level, and the signal col_sw connected to the fourth MOS transistor M4 rises to a high level after the signal READ falls to a low level.
In one possible implementation manner, based on the timing sequence of the signals, the conduction sequence of each MOS transistor is as follows: after the third MOS tube is conducted, the first MOS tube is conducted, after the first MOS tube is conducted, the second MOS tube is conducted, and after the second MOS tube is conducted, the fourth MOS tube is conducted.
In one possible implementation, after the third MOS transistor is turned on, the column-level integrating capacitor C3 is reset, and after the reset, the third MOS transistor may be turned off, and then, the first MOS transistor is turned on. After the first MOS tube is conducted, the photosensitive current generated by the infrared detection module carries out charge integration treatment on the MOS capacitor C_MOS and the MIM capacitor C_MIM of the integration capacitor module, after integration is completed, the first MOS tube is turned off, and then the second MOS tube is conducted, so that the potential difference between the integration capacitor module and the negative input end Vin-of the rail-to-rail operational amplifier A is approximately equal to the power supply voltage VDDA, and the charge in the integration capacitor module is transferred to the column-level integration capacitor C3 to form a voltage signal, and the integration capacitor module is reset. Then, the second MOS transistor is turned off, and the fourth MOS transistor is turned on, so that the column integrator outputs the voltage signal, for example, to the chip-level output bus.
According to the readout circuit with large charge processing capability, the third MOS tube for resetting is moved out of the pixel level unit circuit, the integral capacitance module in the pixel level unit circuit is indirectly reset through the performance of operational amplification, the number of transistors in the pixel level unit circuit is reduced, the area of the integral capacitance module in the pixel area is maximized, MOS capacitors and MIM capacitors which are connected in parallel and in a layout mode of an upper three-dimensional layout and a lower three-dimensional layout are used as integral capacitors, and therefore the integral charge quantity of the detector pixel is improved, and the temperature sensitivity performance of an infrared imager is improved. And the integrated charge can be completely converted into a voltage signal by using a rail-to-rail operational amplifier and a column-level integrating capacitor, and high linearity is realized in a full voltage range, so that the performances of a reading circuit and an infrared thermal imager are improved.
Experiments prove that: at 30×30um 2 Input stage readout circuit in pixel area and column stage integrating circuit with rail-to-rail operational amplifier for realizing charge processing capability of 76Me-, and integrating time is prolonged by about 2.16 times under the same photocurrent condition compared with 36 Me-charge processing capability in related art, and signal to noise ratioThe detection rate of the long-wave infrared detector is improved by about 1.5 times, and the detection rate of the long-wave infrared detector is improved by about 1.5 times. The reading circuit improves the electrostatic discharge protection capability and enhances the reliability of the reading circuit.
The invention also provides an infrared thermal imager, which comprises: an infrared focal plane array chip and the readout circuit with large charge processing capability.
Fig. 5 is a schematic diagram of a thermal infrared imager provided by the present invention, which includes a readout circuit (i.e., readout circuit chip) with large charge processing capability, and an infrared focal plane array chip, which serves as an infrared detector. The readout circuit chip comprises pixel level unit circuits arranged in a matrix form, wherein each pixel level unit circuit is connected with each pixel of the infrared focal plane array chip through an interconnection indium ball, and the readout circuit chip further comprises an output port for outputting the voltage signals.
Although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. A readout circuit having a large charge processing capability, comprising: a plurality of pixel-level unit circuits arranged in a matrix form, and a plurality of column-level integrators respectively corresponding to the pixel-level unit circuits of a plurality of columns in the matrix;
the pixel level unit circuit comprises an infrared detection module, an integrating capacitor module, a first MOS tube and a second MOS tube;
the infrared detection module is used for converting infrared light into current, and inputting the current into the integrating capacitor module for integrating when the first MOS tube is conducted, so as to obtain integrated charge;
the integrating capacitor module is used for transferring the integrated charge to the column integrator when the second MOS tube is conducted;
the column-level integrator comprises a rail-to-rail operational amplifier, a third MOS tube, a fourth MOS tube and a column-level integrating capacitor;
the output end of the integrating capacitor module is connected with the negative input end of the rail-to-rail operational amplifier, the column integrator is used for resetting the column integrating capacitor when the third MOS tube is conducted, receiving the integrated charge through the column integrating capacitor, obtaining a voltage signal, and outputting the voltage signal when the fourth MOS tube is conducted;
the infrared detection module comprises an N-on-P type infrared detector or a P-on-N type infrared detector;
the integration capacitance module comprises an MOS capacitor and an MIM capacitor which are connected in parallel, and the MIM capacitor and the MOS capacitor adopt an upper-lower three-dimensional layout mode;
after the third MOS tube is conducted, the first MOS tube is conducted, after the first MOS tube is conducted, the second MOS tube is conducted, and after the second MOS tube is conducted, the fourth MOS tube is conducted;
the rail-to-rail operational amplifier comprises at least one set of NMOS differential pair structures and at least one set of PMOS differential pair structures;
the at least one group of NMOS differential pair structures comprise a differential pair structure formed by NMOS tubes MN1 and MN2, a differential pair structure formed by NMOS tubes MN3 and MN4 and a differential pair structure formed by NMOS tubes MN5 and MN 6; the positive input end vin+ of the rail-to-rail operational amplifier A is the grid electrode of the NMOS tube MN1, and the negative input end Vin-of the rail-to-rail operational amplifier A is the grid electrode of the NMOS tube MN 2; the gates of the NMOS transistors MN5 and MN6 are connected with the drain electrode of the NMOS transistor MN3, and the sources of the NMOS transistors MN5 and MN6 are grounded; the gates of NMOS transistors MN3 and MN4 are connected with bias voltage VBIAS5; the source electrode of the NMOS tube MN3 is connected with the drain electrode of the NMOS tube MN5, and the source electrode of the NMOS tube MN4 is connected with the drain electrode of the NMOS tube MN 6; the drain electrode of the NMOS tube MN4 is connected with the output end Vout of the rail-to-rail operational amplifier A;
the at least one group of PMOS differential pair structures comprise a differential pair structure formed by PMOS tubes MP1 and MP2, a differential pair structure formed by PMOS tubes MP3 and MP4 and a differential pair structure formed by PMOS tubes MP5 and MP 6; the grid electrode of the PMOS tube MP1 is connected with the positive electrode input end Vin+ of the rail-to-rail operational amplifier A, the grid electrode of the PMOS tube MP2 is connected with the negative electrode input end Vin-of the rail operational amplifier A, the source electrode of the PMOS tube MP1 is connected with the source electrode of the NMOS tube MN4 and the drain electrode of the NMOS tube MN6, the source electrode of the PMOS tube MP2 is connected with the source electrode of the NMOS tube MN3 and the drain electrode of the NMOS tube MN5, the source electrodes of the NMOS tubes MN1 and MN2 are connected with the drain electrode of the NMOS tube MN7, the grid electrode of the NMOS tube MN7 is connected with the bias voltage VBIAS2, and the source electrode of the NMOS tube MN7 is grounded; the drains of the PMOS pipes MP1 and MP2 are connected with the source of the PMOS pipe MP7, the grid electrode of the PMOS pipe MP7 is connected with the bias voltage VBIAS1, and the drain electrode of the PMOS pipe MP7 is connected with the power supply voltage VDDA; the gates of the PMOS pipes MP3 and MP4 are connected with bias voltage VBIAS3, the drain is connected with power supply voltage VDDA, the source of the PMOS pipe MP3 is connected with the drain of the PMOS pipe MP5 and the drain of the NMOS pipe MN2, and the source of the PMOS pipe MP4 is connected with the drain of the PMOS pipe MP6 and the drain of the NMOS pipe MN 1; the gates of the PMOS transistors MP5 and MP6 are connected with the bias voltage VBIAS4, the source of the PMOS transistor MP5 is connected with the drain of the NMOS transistor MN3 and the gates of the NMOS transistors MN5 and MN6, and the source of the PMOS transistor MP6 is connected with the output end Vout of the rail operational amplifier A.
2. The readout circuit with large charge processing capability according to claim 1, wherein in the case where the infrared detection module is the N-on-P type infrared detector, the reference voltage of the anode of the rail-to-rail operational amplifier is a power supply voltage.
3. The readout circuit with large charge processing capability according to claim 1, wherein in the case where the infrared detection module is the P-on-N type infrared detector, the reference voltage of the anode of the rail-to-rail operational amplifier is a ground voltage.
4. The readout circuit with large charge processing capability according to claim 1, wherein the charge processing capability of the pixel-level cell circuit is represented by the formula Qmax = vdda× (c_mos+c_mim), wherein Qmax is the maximum value of the integrated charge, VDDA is the supply voltage, c_mos is the capacitance value of the MOS capacitor, and c_mim is the capacitance value of the MIM capacitor.
5. The readout circuit with large charge processing capability according to claim 1, wherein the third MOS transistor and the column-level integrating capacitor are connected in parallel and connected across the negative input terminal and the output terminal of the rail-to-rail operational amplifier.
6. A thermal infrared imager, the thermal infrared imager comprising: an infrared focal plane array chip and a readout circuit with large charge processing capability according to any one of claims 1 to 5.
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