CN209446170U - Four sampling low noise cmos detector reading circuits - Google Patents

Abstract

This patent discloses one kind four to sample low noise cmos detector reading circuit, including a light-sensitive detector, a variable gain CTIA integrating circuit, four sample circuits and an output amplifier.When reset pulse Reset is low level, CTIA is in integrating state, and light-sensitive detector photogenerated current is stored in integrating capacitor；When reset pulse Reset is high level, CTIA is in reset state.Reset signal is replaced defeated people's signal by signal sampling pulse S1 and S2 and is controlled by reset samples pulse R1 and R2 alternating input signal control, sampled signal, and switch selA and selB is selected alternately to control the output of reset signal and integrated signal.Channel final output signal is the difference of relevant integral optical signal and reset signal, realizes that real correlated sampling reduces the correlated noise of circuit, finally carries out differential amplification output by the output amplifier in each channel.CTIA integrating circuit is the gear integral of variable gain two, adapts to the detection of different light intensity, increases the adaptation range of reading circuit.

Description

Four sampling low noise cmos detector reading circuits

Technical field

This patent is related to a kind of cmos circuit, and in particular to one kind four samples low noise CMOS reading circuit.

Background technique

Cmos detector has extremely important purposes due to its unique advantage in terms of national defence and space industry.Light Electrical resistivity survey technology has been applied to many fields, ideally, simply by the presence of the place of optical radiation signal, so that it may utilize light Electrical resistivity survey slowdown monitoring circuit comes out signal detection.

In the development of cmos detector, signal-to-noise ratio is the key parameter of detector assembly, and good signal-to-noise ratio is to obtain The basis of more high-definition image, for the application demand for meeting domestic aerospace engineering, it is desirable that examined while cmos circuit design Consider Low Noise Design.When detected signal is very faint, it usually will appear the situation that signal is submerged in noise, therefore, Noise analysis is carried out to photodetection circuit, increases the measure of reducing noise, is had to the detectivity for improving photodetection circuit There is important meaning.In this regard, forefathers have done a lot of work.Wang Ligang, Zhang Dianyuan et al. analyze emphatically photodiode Noise proposes the principle and method of design low noise photodiode；Zhou Shuge, Lei Yutang et al. are from reducing circuit noise Angle devises low-noise amplifier, angularly has studied reduction photodetection circuit from source impedance matching, digital filtering respectively The related measure of noise, and dual-sampling circuit is used, but the letter due in dual-sampling circuit, being generally adopted by former frame Number and a later frame reset signal, there is no correlated-double-sampling truly is realized, although can reduce to a certain extent The noise of circuit, but real relevant fixed picture noise and phase noise are not removed clean, being designed with this method four The reset signal of the signal of former frame and former frame can be stored in sampling electricity further on the basis of double sampled by sample circuit Lu Zhong reads simultaneously carry out difference in a later frame, removes fixed picture noise and phase noise, realize correlation truly Sampling, the preferably total reading noise of reduction circuit.

Summary of the invention

This patent realizes correlated sampling truly using four sampling structures, effectively reduces fixed image and makes an uproar Sound, 1/f noise and KTC noise improve and read signal-to-noise ratio, increase dynamic range.

Four sampling structure includes a light-sensitive detector, a variable gain CTIA integrating circuit, a four sampling electricity Road and output amplifier (Fig. 1).When Reset is low level, CTIA is in integrating state, the storage of light-sensitive detector photogenerated current In integrating capacitor；When Reset is high level, CTIA is in reset state.Reset signal replaces input signal by R1 and R2 Control, sampled signal replace defeated people's signal by S1 and S2 and control, and selA and selB alternately control R1, S1 output and R2, S2's is defeated Out.Each channel final output signal is the difference of relevant optical signal and reset signal, realizes that real correlated sampling reduces circuit Correlated noise, finally by each channel output amplifier carry out differential amplification output.CTIA integrating circuit is variable gain Two gear integrals, adapt to the detection of different light intensity, increase the adaptation range of reading circuit.

Difference amplifier module using Differential Input folded cascode configuration amplifying circuit (Fig. 2), M5, M6, M13, M17 constitute the cascode structure of Differential Input, and M16, M18 are the active load of difference output, and M7, M14 are total to common source Grid provide current source, and bias1, bias2, bias3 are bias voltage port, and In-, In+ are the positive and negative defeated of differential operational amplifier Enter end.Wherein Differential Input is to pipe M5, M6, using interdigital transistor, as far as possible above and below guarantee and symmetrically, and in input to pipe Outside use protection ring.

It is characterized by: the input terminal of four sample circuits is connected to the output end of variable gain CTIA integrating circuit, four are adopted The input terminal of the output termination output amplifier of sample circuit.Four sample circuits include two reset switches R1, R2, and two signals are adopted Sample switch S1, S2, four load capacitances Cload, two groups of gating switches SelA, SelB.It is different from traditional dual-sampling circuit Before to be that four sample circuits can integrate detector start, integral start rear, the different moments such as after the completion of integral photosignals It is sampled and is stored respectively, the output signal of detector is allowed flexibly to handle and reduce the reading noise of device.

Amplifier uses the level-one folded cascode configuration of Differential Input, overcome that traditional second level amplification uses compared with Big miller-compensated electric capacity and occupy excessive area；Four sample circuit is able to achieve correlated-double-sampling truly and reduces admittedly Determine picture noise and 1/f noise, noise is lower than traditional common two samplings reading circuit, can be applied to low-light cmos detector letter Number reading.

The advantages of this patent, is as follows:

Four sample circuit of 1.CMOS detector uses four sampling structures after CTIA integrating circuit, is able to achieve truly Correlated noise remove function, effectively lower circuit output noise, increase the dynamic range of reading circuit, be suitable for faint Signal detection field.

Cascode structure is used in 2.CTIA integrating circuit, supply-voltage rejection ratio is higher, reduces power supply ripple The noise of introducing.Two capacitors of different sizes have been used in the integration circuit, adapt to the detection of different light intensity signals.

3. connecing electricity for adding around the NMOS transistor in N trap in four sampling cmos detector reading circuit layout designs The N+ ring in source, adds the P+ ring of earthing potential around NMOS transistor, then these diffuser rings are shorted with metal, is connect with reducing Power supply and the resistance for connecing low potential, the ohmic drop that majority carrier can be made to be formed in substrate or trap in this way are injecting It is collected before parasitic transistor base area by protection ring, not only can reduce dead resistance resistance value, the electric current of PNP pipe can also be reduced Gain effectively prevents latch.

Detailed description of the invention

Fig. 1 is four sampling unit structural schematic diagram of cmos detector.

Fig. 2 is four sample circuit working timing figure of cmos detector.

Fig. 3 is cmos detector CTIA amplifier circuit configuration figure.

Specific embodiment

Specific implementation of the patent mode is described in further detail with reference to the accompanying drawing:

Embodiment 1

Fig. 1 is four sample circuit cellular construction schematic diagram of cmos detector, including a light-sensitive detector, a variable increasing Beneficial CTIA integrating circuit, four sample circuits and an output amplifier.When Reset is low level, CTIA is in integrating state, Light-sensitive detector photogenerated current is stored in integrating capacitor；When Reset is high level, CTIA is in reset state.Reset letter Number by R1 and R2 alternating input signal control, sampled signal replaces defeated people's signal by S1 and S2 and controls, and selA and selB are alternately controlled The output of R1, S1 output and R2, S2 processed.Each channel final output signal is the difference of relevant optical signal and reset signal, is realized Real correlated sampling reduces the correlated noise of circuit, finally carries out differential amplification output by the output amplifier in each channel. CTIA integrating circuit is the gear integral of variable gain two, adapts to the detection of different light intensity, increases the adaptation range of reading circuit.

Embodiment 2

Fig. 2 is that cmos detector four samples reading circuit working timing figure, and CLK is clock pulses, and SYNC is the frame period Initial pulse, RESET are the reset pulse in frame period, and R1 and R2 are the reset samples signal pulse after resetting, and S1 and S2 are product Signal sampling pulse after the completion of point, selA and selB are two stages, and R1 and S1 are that sampling is kept when selA is low level It is sequentially read out using on capacitor when selA is high level respective, R2 and S2 are that sampling is protected when selB is low level It holds and is sequentially read out using on capacitor when selB is high level respective, selA and selB are opposite time sequential pulse.When When RESET is low level, CTIA is in integrating state, and light-sensitive detector photogenerated current is stored in integrating capacitor；When RESET is When high level, CTIA is in reset state.Reset signal is by R1 and R2 alternating input signal selA and selB control, sampled signal Defeated people's signal selA and selB control is replaced by S1 and S2, i.e. selA and selB alternately control R1, S1 output and R2, S2's is defeated Out.Each channel final output signal is the difference of relevant optical signal and reset signal, realizes that real correlated sampling reduces circuit Correlated noise, finally by each channel output amplifier carry out differential amplification output.Reduce fixed picture noise and 1/f noise influences.

Embodiment 3

When designing the total domain of CMOS low noise detector and pin is arranged, to reduce circuit overall noise, all numbers PAD and simulation PAD are separately laid out, and digital power and analog power are separately powered, and the pulse shock for minimizing number passes through lining It is coupled to analog portion in bottom.When drawing domain, all amplifiers all use interdigital transistor to pipe, guarantee as far as possible up and down and left It is right symmetrical, it can reduce the input terminal imbalance of CMOS differential operational amplifier, the especially input pipe of difference amplifier in this way, especially To be important, in this circuit, since Differential Input uses upper and lower and bilateral symmetry to pipe, this largely reduces whole The input of a differential operational amplifier is lacked of proper care, and is improved the symmetrical performance of circuit, is reduced offset voltage and dark current is caused to bring Circuit overall noise.

In layout design, the increase area P+ inhibits latch with the number that the substrate contact that the area N+ is formed is contacted with trap as far as possible Effect, plus the N+ ring for connecing power supply, will add the P+ of earthing potential around the NMOS transistor in N trap around NMOS transistor Ring, then these diffuser rings are shorted with metal, power supply is connect with reduction and connect the resistance of low potential, most current-carrying can be made in this way The ohmic drop that son is formed in substrate or trap is collected before injecting parasitic transistor base area by protection ring, can not only be subtracted Small dead resistance resistance value, can also reduce the current gain of PNP pipe, effectively prevent latch.

Embodiment 4

The total noise of this Differential input circuit (Fig. 3) mainly determines by input pipe M5, M6 pipe, equivalent input noise voltage Calculation formula are as follows:

(wherein)

First item is channel noise, and Section 2 is 1/f noise.

g_mFor the mutual conductance of input pipe, to reduce overall noise, the size of input pipe W/L and the design of bias current are very heavy It wants.From increase g known to above formula_mIt can reduce channel noise, under conditions of area license, increase the W/L of input pipe, And in input to protection ring has been used outside pipe, advantageously reduces input and come in noise to the imbalance of pipe and extraneous crosstalk. The 1/f noise of PMOS ratio NMOS is small, so input pipe M5, M6 select PMOS to reduce 1/f noise.In addition increasing W × L can also subtract Small 1/f noise, under conditions of power consumption and area are permitted, other pipes consider low noise standard as far as possible also to design.Work as temperature Electric current increasing and threshold voltage V when degree reduces_TIncrease may make device that can not work, so in the W/ for designing each pipe It to be fully considered when L.

The amplifier uses the level-one folded cascode configuration of Differential Input.Wherein M5 and M6 is input to pipe, M5, M6, M13, M17 constitute the cascode structure of Differential Input, and M16, M18 are the active load of difference output, and M7, M14 are to common source Grid provide current source altogether, and bias1, bias2, bias3 are bias voltage, and In-, In+ are the positive negative input of differential operational amplifier End.In circuit without using the passive resistance to very temperature sensitive, so the circuit can be normal under room temperature and low temperature Work, test result show that the current source temperature rejection ability is very strong, so the four samplings cmos detector reading circuit work Temperature range is very wide, can work normally from room temperature 300K to low temperature 77K, is conducive to the reduction of thermal noise under low temperature.

Embodiment 5

The four samplings cmos detector reading circuit does not have using the level-one Foldable cascade structure of Differential Input Have using miller-compensated circuit, which overcomes the shortcomings that conventional dual-stage amplifier easily causes oscillation at low temperature, the spy Surveying device circuit can work normally from room temperature 300K to low temperature 77K.

In difference amplifier, threshold value loss is reduced to increase the output signal amplitude of oscillation using PMOS input pipe, PMOS has Lower flicker noise reduces the front-end noise introduced from the input end ref furthermore with the end REF ground connection, effectively improves system Signal-to-noise ratio.

In four sample circuits, pipe breadth length ratio can also be followed to reduce bus by the first order P after four sampling of reduction and posted Raw capacitor, and reduce P and load pipe bias voltage is followed to increase driving current, signal delay is reduced, the sampling frequency of reading circuit is made Rate increases to 6MHz by original 2MHz, effectively improves the read frequency of long alignment visible light cmos detector.

The CMOS tetra- sampling reading circuit can be applied to visible cmos detector signal read, be also used as it is other not With the reading of the high resistivity silicon detectors signal of wave band.

This patent is illustrated above by specific embodiment, but this patent is not limited to these specific implementations Example.It will be understood by those skilled in the art that various modifications, equivalent replacement, variation etc. can also be done to this patent, these transformation It, all should be within the protection scope of this patent without departing from the spirit of this patent.

Claims (1)

1. one kind four samples low noise cmos detector reading circuit, including a light-sensitive detector, a variable gain CTIA Integrating circuit, four sample circuits and an output amplifier；It is characterized by:

The input terminal of four sample circuits is connected with the output end of a variable gain CTIA integrating circuit, four sample circuits Output termination output amplifier input terminal；

Four sample circuits include two reset switch R1, R2, two signal sampling switch S1, S2, four load capacitance C_load, two Group gating switch Sel_A、Sel_B；

The variable gain CTIA integrating circuit includes two integrating capacitors Cint1 and Cint2, or includes multi-stage integral electricity Hold, a gain control switch Gain by PGA control, integral reset switch Reset, CTIA a difference amplifier is using folding Folded cascode structure, metal-oxide-semiconductor M5, M6, M13, M17 constitute the cascode structure of Differential Input, and M16, M18 are difference output Active load, M7, M14 be cascode current driving tube；Four sample circuits to detector integral start before, integral start Afterwards, the photosignals of different moments is sampled and is stored respectively after the completion of integrating etc., so that the output signal of detector can be with Flexibly handle and reduce the reading noise of device.