JP5093768B2 - Signal readout circuit - Google Patents

Description

  The present invention relates to a signal readout circuit used for a thermal infrared image sensor or the like.

Conventionally, as a thermal infrared image sensor, a frequency band of thermal noise voltage using a thermopile as a noise source by connecting a capacitor in parallel to the thermopile in each pixel and providing a low-pass filter composed of a thermopile resistor and a capacitor. It has been proposed to limit the width (for example, Patent Document 1). Here, the thermal noise voltage is En [Vrms], the Boltzmann constant is k (= 1.38 × 10 ⁻²³ [J / K]), the absolute temperature is T [K], the resistance of the thermopile is R [Ω], the frequency If the bandwidth is Δf, the thermal noise voltage En is expressed by the following formula 1.

  In the thermal infrared image sensor described in Patent Document 1, a capacitor is formed below the thermopile on the main surface side of the semiconductor substrate.

Conventionally, as a configuration for improving the signal-to-noise ratio (S / N ratio) of the output of the sensor, a charge amplifier that is an amplifier that amplifies the output of the sensor, and noise removal provided at the subsequent stage of the charge amplifier (For example, Patent Document 2), it is conceivable to apply such a configuration for improving the S / N ratio to a thermopile signal readout circuit.
Japanese Patent No. 3385762 JP-A-9-159560

  However, in the thermal infrared image sensor disclosed in Patent Document 1, since it is necessary to form a capacitor below the thermopile on the main surface side of the semiconductor substrate, the manufacturing process becomes complicated, and the capacitor due to manufacturing variations The filter characteristics vary due to variations in capacitance and variations in capacitance due to temperature. Further, in the thermal infrared image sensor disclosed in Patent Document 1, it is necessary to provide a signal readout circuit including an amplifier and a sample hold circuit after the filter, and the S / N ratio is lowered.

  Moreover, in the configuration for improving the S / N ratio disclosed in Patent Document 2, it is necessary to provide an amplifier and a noise removing filter, which causes a problem of increasing costs.

  The present invention has been made in view of the above reasons, and an object thereof is to provide a signal readout circuit capable of improving the S / N ratio at low cost.

  The invention of claim 1 is a signal readout circuit that amplifies and reads out the output of a thermopile that generates an output value of an analog amount corresponding to a temperature change due to absorption of infrared rays, and is connected in series to the thermopile and reads out the output of the thermopile Switching element for selecting whether or not, and the inverting input terminal of the operational amplifier is connected in series to the switching element for selection through the first capacitor, and the non-inverting input terminal is connected to the virtual ground and the inverting input terminal A parallel circuit of the second capacitor and the first reset switching element is connected between the output terminal and the output terminal, and the second circuit is connected between the connection point of the selection switching element and the first capacitor and the virtual ground. An integrator that amplifies the output of the thermopile connected to the reset switching element, the output terminal of the integrator, and a virtual ground Hold capacitor connected via a sampling switching element and control means for controlling on / off of each switching element, and the transconductance of the operational amplifier is set to the minimum transconductance that can satisfy the sampling time. It is characterized by.

  According to the present invention, the integrator that functions as an amplifier has a gain determined by the capacitance ratio of the first capacitor and the second capacitor, so that the accuracy of the gain can be increased, and the transconductance of the operational amplifier is determined by the sampling time. Is set to the minimum value of transconductance that satisfies the above condition, it is possible to reduce noise caused by thermal noise using the thermopile as a noise source while amplifying the minute output of the thermopile, and at low cost, the S / N The ratio can be improved.

  According to a second aspect of the present invention, in the first aspect of the invention, each of the switching elements comprises a MOS transistor, and the control means includes the selection switching element, the first reset switching element, and the second reset element. A reset mode in which each of the switching element for sampling and the switching element for sampling is turned on to discharge residual charges of the first capacitor, the second capacitor, and the holding capacitor, and the first switching element for reset and the A sampling mode in which charge is accumulated in the holding capacitor by turning off the second reset switching element; and a reading mode in which the voltage of the holding capacitor can be read by turning off the sampling switching element. When the first reset switching element and the second reset switching element are turned off when shifting from the reset mode to the sampling mode, the control voltage of the first reset switching element is continuously lowered to turn off. The second reset switching element is turned off after being turned on.

  According to this invention, when the control means turns off the first reset switching element and the second reset switching element when shifting from the reset mode to the sampling mode, the first reset switching element. Since the second reset switching element is turned off after the control voltage of the first reset switching element is turned off by continuously reducing the control voltage, the voltage is injected into the integrator from the channel of the MOS transistor constituting the first reset switching element. Charge can be reduced and reset noise can be reduced.

  The invention of claim 3 is the invention of claim 1, further comprising an offset hold capacitor connected via an offset sampling switching element between the output terminal of the integrator and the virtual ground. , The selection capacitor, the first reset switching device, the second reset switching device, the sampling switching device, and the offset sampling switching device are turned on, and the second capacitor is turned on. A reset mode for discharging residual charge of each of the capacitor, the hold capacitor and the offset hold capacitor; the first reset switching element; the second reset switching element; and the offset sampling switch. A sampling mode in which the holding element is turned off and electric charge is accumulated in the holding capacitor, and a reading mode in which the sampling switching element is turned off and the voltage of the holding capacitor can be read out. A switching period, a reset period in which the first reset switching element, the second reset switching element, the sampling switching element, and the offset sampling switching element are turned on, and the reset period is followed by the first An offset hold capacitor, an offset accumulation period in which charges are accumulated in the hold capacitor with the reset switching element turned off, and an offset sampling switching element after the offset accumulation period Characterized in that the offset reading period to allow reading the voltage of the offset hold capacitor is provided as off.

  According to the present invention, the offset holding capacitor is connected between the output terminal of the integrator and the virtual ground via an offset sampling switching element. In the reset mode of the control means, the selection switching is performed. A reset period in which an element, the first reset switching element, the second reset switching element, the sampling switching element, and the offset sampling switching element are turned on, and the reset period is followed by the first reset An offset hold capacitor with the switching element turned off and an offset accumulation period for accumulating charges in the hold capacitor, and an offset hold with the switching element for offset sampling turned off after the offset accumulation period Since there is an offset readout period in which the capacitor voltage can be read out, by taking the difference between the voltage of the hold capacitor read out in the readout mode and the voltage of the offset hold capacitor read out in the offset readout period The influence of offset can be canceled and fixed pattern noise can be reduced.

  The invention of claim 1 can reduce noise caused by thermal noise using the thermopile as a noise source while amplifying the minute output of the thermopile, and can improve the S / N ratio at low cost. There is an effect of becoming.

(Embodiment 1)
In the present embodiment, a thermal infrared image sensor including a signal readout circuit that amplifies and reads the output of a thermopile that generates an output value of an analog amount corresponding to a temperature change due to infrared absorption is exemplified.

As shown in FIG. 6, the thermal infrared image sensor includes a thermopile array A in which the thermopile 1 of each pixel is arranged in a two-dimensional array (matrix shape), and a plurality of thermopiles 1 in each column are formed of MOS transistors. a plurality of vertical read lines 2 are commonly connected to each column through the selection switching element Q _S, a plurality of horizontal signal selecting switching element Q _S are connected in common for each row corresponding to the thermopile 1 of each row Line 3, a plurality of integrators 4 provided for each vertical signal line 2 for amplifying the output of thermopile 1, a sample hold (S / H) circuit 5 provided on the subsequent stage side of each integrator 4, a horizontal scanning circuit 6 for turning on and off the selected switching element Q _S one by n pieces that are connected to the horizontal signal line 3, alternatively a / D output of the sample and hold circuit 5 And a multiplexer 7 to be input to the inverter, thereby making it possible to read the outputs of all of the thermopile 1 in time series. Here, the thermopile 1, as an equivalent circuit, are represented by a series circuit of a voltage source Vs corresponding to thermal electromotive force and the resistance R _p. In the thermal infrared image sensor described above, m × n (for example, 128 × 128) thermopiles 1 are formed on a single semiconductor substrate (for example, a silicon substrate).

  In the above thermal infrared image sensor, if attention is paid to one pixel, the signal readout circuit has a circuit configuration as shown in FIG.

Configuration shown in Figure 1, the selecting switching element Q _S described above for selecting whether reading the output of the thermopile 1 are connected in series with the thermopile 1, an integrator 4 above, the second-stage integrator 4 And the above-described sample-and-hold circuit 5.

Here, the integrator 4 has a non-inverting input terminal with the inverting input of the operational amplifier OP is connected in series to the first switching element for selecting via the capacitor C ₁ Q _S is connected to the virtual ground, an operational amplifier the second capacitor C ₂ is connected between the inverting input terminal and the output terminal of the OP, the first reset switching element Q _R is connected in parallel to the second capacitor C _2, and selecting switching element Q _S the second reset switching element Q _R1 is connected between the virtual ground and the connection point between the first capacitor C _1. Here, the integrator 4 constitutes a switched capacitor integrator, and the gain is determined by the capacitance ratio (C ₁ / C ₂ ) between the _first capacitor C ₁ and the second capacitor C _2. And the influence of fluctuation due to temperature can be suppressed, and gain accuracy can be increased.

The sample hold circuit 5 is constituted by a series circuit of a sampling switching element Q _SS and a hold capacitor C _LS connected between the output terminal of the integrator 4 and the virtual ground, and the sampling switching element 5 When Q _SS is off, the voltage across the holding capacitor C _LS can be read out.

The signal read circuit of this embodiment, the switching elements _{Q S, Q R, Q SS} , the control means comprising a control circuit for turning on and off the Q _R1 comprises a (not shown), the above-mentioned horizontal scanning circuit on-off timing of the selection switching element Q _S by 6 is instructed from the control unit. In the A / D converter described above, the output of each thermopile 1 is sequentially converted into a digital value in synchronization with the read timing controlled by the control means. Here, each switching element Q _S , Q _R , Q _SS , Q _R1 is configured by a MOS transistor, each capacitor C ₁ , C ₂ of the integrator 4 is configured by an MIM capacitor, and is used for holding of the sample hold circuit 5. The capacitor C _LS is composed of a MOS capacitor.

  Hereinafter, an operation example of the signal readout circuit will be described with reference to FIG.

2, given (a) is a control signal (control voltage) .phi.s applied to the selected switching element Q _S from the control unit, (b) the second reset switching element Q _R1 from the control means a control signal (control voltage) φ _R1, (c) the first reset control signal applied to the switching element Q _R (control voltage) phi _R from the control unit, (d) the sampling from the control means A control signal (control voltage) φ _SS applied to the switching element Q _SS is shown, and (e) shows a voltage Vout across the holding capacitor C _LS .

Said control means selectively switching element Q _S, for the first reset switching element Q _R, the first capacitor C ₁ of each second reset switching element Q _R1 and sampling switching element Q _SS as _on, the a reset mode to discharge capacitor C ₂ and a hold capacitor C _LS respective residual charge, the hold capacitor C _LS a first reset switching element Q _R and the second reset switching element Q _R1 as an off has a sampling mode for accumulating an electric charge, and a read mode to enable reading the voltage of the hold capacitor C _LS sampling switching element Q _SS as an off, first reset when the transition from the reset mode to the sampling mode The switching element Q _R, when to turn off the second reset switching element Q _R1, the second reset switching after continuously off by reducing the control voltage phi _R of the first reset switching element Q _R The element _QR1 is turned off.

Therefore, in the reset mode, the residual charges of the first capacitor C ₁ , the second capacitor C ₂ and the hold capacitor C _LS are discharged, so that the voltage Vout across the hold capacitor C _LS is lowered, and the sampling mode so the output of the thermopile 1 is accumulated in the amplified hold capacitor C _LS by the integrator 4, increases the voltage across Vout of the hold capacitor C _LS gradually, in a read mode, the sampling switching element Q _SS Is turned off, and the voltage Vout across the hold capacitor _CLS can be read out. Here, in the present embodiment, the control means, when to the first reset switching element Q _R, off the second reset switching element Q _R1 when the transition from the reset mode to the sampling mode, Fig. 2 (c the as shown in) first reset switching element Q _R control voltage phi _R continuously decrease is caused by turning off the second reset switching element Q _R1 as shown in FIG. 2 (b) after turning off the since thereby, because to MOS transistors constituting the first reset switching element Q _R is weak inversion state between the source and the drain is conductive, charge injected from the channel of the MOS transistor to the integrator 4 Can be reduced, reset noise can be reduced, and the S / N ratio can be improved.

  By the way, in order to increase the thermoelectromotive force of the thermopile 1, it is necessary to increase the thermal resistance. However, increasing the thermal resistance increases the electrical resistance and increases thermal noise.

Here, regarding the signal readout circuit of the present embodiment, the input equivalent noise of the noise component using the thermopile 1 as the noise source is V _ni1 , the input equivalent noise of the noise component _using the operational amplifier OP as the noise source is V _ni2 , and the reset mode. the first reset switching element Q _R and the second input conversion noise of the noise component of the reset switching element Q _R1 and noise sources V _Ni3, when the total input-referred noise and V _ni of the total equivalent input noise V _ni is expressed by the following formula 2.

Here, the input equivalent noise V _ni1 of the noise component using the thermopile 1 as a noise source is obtained based on the equivalent circuit shown in FIG. 3, that is, the equivalent circuit in the sampling mode. In the equivalent circuit shown in FIG. 3, the resistance of the thermopile 1 is R _p , the thermal noise voltage of the noise component using the thermopile 1 as a noise source is V _ni , the transconductance of the operational amplifier OP is g _m , and the gain of the integrator 4 is G When the voltage V _o across the holding capacitor C _LS is assumed, the transfer function H (s) is expressed by the following equation (3).

  Here, when the above equation 3 is arranged, the following equation 4 is obtained.

Here, assuming that G >> ₁ , p ₁ is the dominant pole (dominant pole), and the zero and p ₂ are considered to be much higher than the frequency of p ₁ . Furthermore, since G = C ₁ / C ₂ , Z, p ₁ , and p ₂ in Equation 4 are as shown in Equation 5 below.

  At this time, if the angular frequency is ω and the transfer function with respect to the angular frequency ω is H (jω), it can be regarded as a first-order system as shown in Equation 6 below.

Here, the output conversion noise V _no1 of the noise component using the thermopile 1 as a noise source is expressed by the following _equation (7).

Here, if p ₁ of Equation 5 is substituted into Equation 7, the output equivalent noise V _no1 of the noise component using the thermopile 1 as a noise source is as shown in Equation 8 below.

In Equation _8, if _{GC LS »C 1 (1 + R} p g m), the output referred noise V _no1 noise components that the thermopile 1 and noise source is as the following equation 9.

Therefore, the input equivalent noise V _ni1 of the noise component using the thermopile 1 as a noise source is as shown in the following _equation (10).

Furthermore, the input conversion noise V _ni2 of noise components an operational amplifier OP and the noise source, the excess noise factor of the operational amplifier OP and xi], if _{GC LS »(1 + R p} g m), the noise of the operational amplifier OP Since the output conversion noise V _no2 of the noise component as the source is expressed by the following formula 11, it is expressed by the following formula 12.

Also, the equivalent input noise V _Ni3 thermal noise sampled at a virtual ground in reset mode, the first reset switching element Q _R and the second reset switching element Q _R1 and noise sources, the virtual ground net In this case, it is assumed that G >> 1 and the output conversion noise V _no3 of the noise component is considered. For G»1, since the first capacitance of the capacitor C ₁ is very large relative to the second capacitance of the capacitor C _2, components which are sampled in the first capacitor C ₁ is dominant. Therefore, when the net charge of the virtual ground is Q _net , the charge Q _net is expressed by the following _equation (13).

The charge Q _{net Non,} when allowed to turn on the first reset switching element Q _R, since all appearing at the output is transferred second to the capacitor C _2, the noise source first reset switching element Q _R and since output-referred noise V _no3 noise component is expressed by the following Expression 14, the input conversion noise V _Ni3 of noise components of the first reset switching element Q _R and the noise source is represented by the following Expression 15.

By the way, from the above equation _10, by reducing the transconductance g _m of the operational amplifier OP, the frequency bandwidth can be reduced, and the input equivalent noise V _ni1 of the noise component using the thermopile 1 as a noise source can be reduced. I understand. Here, for example, if C ₁ = 10 pF, C ₂ = 10 fF, C _LS = 10 pF, R _p = 250 kΩ, g _m = 4 × 10 ⁻⁶ [S], then from the above equations 9 and 10, V _no1 ≈640 μVrms and V _{ni1 ≈0.64} μVrms. Further, from _{Equation 12} , if the input equivalent noise V _ni2 of the noise component using the operational amplifier OP as a noise source is, for example, ξ = 1, V _ni2 ≈0.64 μVrms. Also, the noise component of several 15, the input conversion noise V _Ni3 in the reset mode, the _V ni3 ≒ 20.34μVrms next, equivalent input noise V _ni1 and an operational amplifier OP of the noise component to the noise source thermopile 1 and noise source This is sufficiently larger than the input conversion noise _Vni2 . Therefore, the first reset switching element Q _R In the transition from the reset mode to the sampling _mode, when turning off the second reset switching element Q _R1, the first reset switching as shown in FIG. 2 (c) by turning off the second reset switching element Q _R1 as shown in FIG. 2 (b) after the control voltage phi _R of the element Q _R is continuously reduced is allowed to off, the first reset switching element to MOS transistors constituting the Q _R is the weak inversion state to a conducting state between the source and drain, to reduce the charge injected from the channel of the MOS transistor to the integrator 4, thereby reducing the reset noise.

Here, in FIG. 4, the relationship between the gain G when the capacitance of the holding capacitor C _LS is variously changed and the input conversion noise V _ni1 of the noise component using the thermopile 1 as a noise source was obtained by circuit simulation. The result and the value obtained by the approximate expression shown in Equation 10 above are shown together. FIG. 5 shows a circuit simulation of the relationship between the gain G when R _p · g _m (where R _p = 250 kΩ) is changed and the input equivalent noise V _ni1 of the noise component having the thermopile 1 as a noise source. The result obtained by the above and the value obtained by the approximate expression shown in Equation 10 above are shown together.

4 and 5, it can be seen that in the region where the gain G is large (region where G> 20), the result obtained by the circuit simulation agrees well with the value obtained by the approximate expression of Formula 10, from FIG. _However , it can be seen that by reducing the transconductance g _m of the operational amplifier OP, the input equivalent noise V _ni1 of the noise component having the thermopile 1 as a noise source can be reduced.

  Next, the response speed in the sampling mode of the signal readout circuit of this embodiment will be described.

Since it can be considered as a step response, if the input voltage to the integrator 4 is V _i0 , the voltages V _O (s) and v _O (t) across the holding capacitor C _LS are expressed by 17.

  The time constant τ can be expressed by the following formula 18.

Here, it can be seen from Equation 18 that when the transconductance g _m of the operational amplifier OP is decreased, the time constant τ increases and the response speed decreases.

Therefore, the signal read circuit of this embodiment, set to a minimum value of transconductance g _m of the transconductance g _m of the operational amplifier OP is satisfactory sampling time which is the time defined by the sampling mode in response to a predetermined reading rate It is. Here, satisfying the sampling time means that the response time t _r = 3τ is less than the sampling time. _{Incidentally, C LS = 10pF, G =} 1000, R p = 250kΩ, if R _p g _m = 1, a t _r = 7.5 ms.

In the above signal read circuit of the present embodiment described, since the gain G of the integrator 4 which acts as an amplifier depends on the capacitance ratio of the first capacitor C ₁ and the second capacitor C _2, to enhance the gain accuracy of the Since the transconductance g _m of the operational amplifier OP is set to the minimum value of the transconductance g _m that can satisfy the sampling time, noise with the thermopile 1 as a noise source while amplifying a minute output of the thermopile 1 Noise due to thermal noise of components can be reduced, and the S / N ratio can be improved at low cost.

(Embodiment 2)
The basic configuration of the signal readout circuit of this embodiment is substantially the same as that of the first embodiment. As shown in FIG. 7, the sample hold circuit 5 is used for offset sampling between the output terminal of the integrator 4 and the virtual ground. such that it includes an offset hold capacitor C _LR connected through the switching element Q _SR are different. Here, the offset sampling switching element _QSR is composed of a MOS transistor having the same specifications as the sampling switching element _QSS, and is ON / OFF controlled by the control means described in the first embodiment. Further, the offset hold capacitor C _LR is composed of a MOS capacitor having the same specifications as the hold capacitor C _LS . In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted suitably.

  Hereinafter, an operation example of the signal readout circuit will be described with reference to FIG.

8, given (a) is a control signal (control voltage) phi _S applied to the selected switching element Q _S from the control unit, (b) the second reset switching element Q _R1 from the control means a control signal (control voltage) phi _R1 which is, (c) is the first reset control signal applied to the switching element Q _R (control voltage) phi _R from the control unit, (d) is sampled from the control means the use switching element _Q control signal applied to the _SR (control voltage) phi _SR, (e) a control signal (control voltage) supplied from the control means to the sampling switching element _{Q SS} phi _SS, (f) the hold the voltage across Vout of use capacitor _{C LS,} respectively show.

The control means turns on the selection switching element Q _S , the first reset switching element Q _R , the second reset switching element Q _R1 , the sampling switching element Q _SS and the offset sampling switching element Q _SR. A reset mode for discharging residual charges of the first capacitor C ₁ , the second capacitor C ₂ , the hold capacitor C _LS and the offset hold capacitor C _LR ; the first reset switching element Q _R ; hold the sampling mode for accumulating charges in the hold capacitor C _LS a reset switching element Q _R1 and offset sampling switching element Q _SR as an off, the sampling switching element Q _SS as an off And a read mode to enable reading the voltage of the capacitor C _LS.

Here, in the reset mode, the selection switching element Q _S , the first reset switching element Q _R , the second reset switching element Q _R1 , the sampling switching element Q _SS and the offset sampling switching element Q _SR are turned on. and a reset period T1 has an offset accumulation period T2 to accumulate next first reset switching element Q _R charges to offset the hold capacitor C _LR and a hold capacitor C _LS as an off-reset period T1, the offset storage After the period T2, an offset reading period T3 is provided in which the offset sampling switching element _QSR is turned off and the voltage of the offset hold capacitor _CLR can be read.

Therefore, in the signal readout circuit of the present embodiment, the difference between the voltage of the hold capacitor C _LS read out in the read mode and the voltage of the offset hold capacitor C _LR read out during the offset readout period T2 is obtained, thereby resetting the reset mode. Since the noise component in FIG. 6 behaves as a fixed charge, the influence of offset can be canceled, fixed pattern noise can be reduced, and the S / N ratio can be improved.

Regarding the noise in the read mode in this case, the noise component by the operational amplifier OP and the second reset switching element _QR1 is sampled in the offset hold capacitor _CLR in the sample hold circuit 5. These noise components of the input referred noise V _NI4 noise component to the noise source operational amplifier OP, there is an input conversion noise V _NI5 by the ON resistance R _s of the second reset switching element Q _R1, respectively the number of the following 19 and Expression 20

Here, for example, if C _LS = 10 pF, R _s = 10 kΩ, ξ = 1, g _m = 4 × 10 ⁻⁶ [S], V _ni4 ≈0.64 _μV rms, V _ni5≈0.13 μVrms. The total input conversion noise V _{ni at} this time is expressed by the following _equation (21).

Therefore, V _ni ≈1.12 μV rms, and an offset canceling effect can be obtained.

2 is a circuit diagram of a signal readout circuit in Embodiment 1. FIG. It is operation | movement explanatory drawing same as the above. It is an equivalent circuit diagram of a signal readout circuit same as the above. It is explanatory drawing of the noise analysis result of a signal read-out circuit same as the above. It is explanatory drawing of the noise analysis result of a signal read-out circuit same as the above. It is a circuit diagram of the thermal type infrared image sensor same as the above. 5 is a circuit diagram of a signal readout circuit in Embodiment 2. FIG. It is operation | movement explanatory drawing same as the above.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Thermopile 4 Integrator 5 Sample hold circuit _Rp resistance Vs Voltage source Q _S selection switching element OP Operational amplifier C ₁ 1st capacitor C ₂ 2nd capacitor Q _R 1st reset switching element Q _R1 2nd Switching element for reset Q Switching element for _SS sampling Q _SR Switching element for offset sampling C _LS hold capacitor C _LR offset hold capacitor

Claims (3)

  A signal readout circuit that amplifies and reads the output of a thermopile that generates an analog output value in response to temperature changes due to infrared absorption, and is a selection that selects whether to read the thermopile output connected in series to the thermopile Switching element and the inverting input terminal of the operational amplifier are connected in series to the switching element for selection via the first capacitor and the non-inverting input terminal is connected to the virtual ground and between the inverting input terminal and the output terminal. A parallel circuit of the second capacitor and the first reset switching element is connected, and the second reset switching element is connected between the connection point between the selection switching element and the first capacitor and the virtual ground. The integrator that amplifies the output of the thermopile, and the sample between the output terminal of the integrator and the virtual ground. A holding capacitor connected via a switching element and a control means for controlling on / off of each switching element, and the transconductance of the operational amplifier is set to the minimum value of transconductance that can satisfy the sampling time. A characteristic signal readout circuit.   Each of the switching elements comprises a MOS transistor, and the control means turns on the selection switching element, the first reset switching element, the second reset switching element, and the sampling switching element. A reset mode for discharging residual charges of the first capacitor, the second capacitor, and the hold capacitor; and the hold capacitor with the first reset switching element and the second reset switching element turned off. A sampling mode for accumulating charges in the memory and a reading mode in which the sampling switching element is turned off and the voltage of the holding capacitor can be read out. When turning off the first reset switching element and the second reset switching element, the control voltage of the first reset switching element is continuously lowered to turn off the second reset switching element. 2. The signal readout circuit according to claim 1, wherein the reset switching element is turned off.   An offset hold capacitor connected between an output terminal of the integrator and the virtual ground via an offset sampling switching element; and the control means includes the selection switching element and the first reset switching Each of the first capacitor, the second capacitor, the hold capacitor, and the offset hold capacitor is turned on by turning on the element, the second reset switching element, the sampling switching element, and the offset sampling switching element. A reset mode for discharging electric charge, and the hold reset circuit by turning off the first reset switching element, the second reset switching element, and the offset sampling switching element. A sampling mode for accumulating charges in the memory, and a reading mode in which the sampling switching element is turned off and the voltage of the holding capacitor can be read. In the reset mode, the selection switching element, the first switching element A reset period in which the reset switching element, the second reset switching element, the sampling switching element, and the offset sampling switching element are turned on, and the first reset switching element is turned off after the reset period to be offset A capacitor for holding and an offset storage period for storing charges in the capacitor for holding, and a capacitor for offset holding by turning off the offset sampling switching element after the offset storage period. Signal reading circuit according to claim 1, wherein the offset reading period to allow reading the voltage, characterized in that it is provided.

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