JP5738954B2 - Solid-state image sensor - Google Patents

Description

  Embodiments described herein relate generally to a solid-state imaging device.

  Infrared rays have a longer wavelength than visible light, and are therefore less likely to scatter than visible light. Therefore, it has a feature of high permeability to smoke and fog. Moreover, since infrared rays are emitted from a heat source such as a living organism, if infrared rays are used, images can be taken even at night. At this time, since the infrared rays are not visible, even if the subject is illuminated with infrared rays at night, the subject can be photographed without being noticed. Furthermore, if infrared rays emitted from an object or a living body that is a heat source are detected and photographed, temperature information of the subject can be obtained. Due to this property, imaging using infrared rays has a wide range of applications such as surveillance cameras and fire detection cameras in the defense field.

  In recent years, the development of “uncooled infrared solid-state imaging devices” that do not require a cooling mechanism has become active. An uncooled or thermal infrared solid-state imaging device converts incident infrared rays having a wavelength of about 10 μm into heat by an absorption structure, and then converts the temperature change of the heat-sensitive part caused by the weak heat into an electrical signal by some thermoelectric conversion means. Infrared image information is obtained by reading the electrical signal.

  For example, there is a solid-state imaging device using a silicon pn junction that converts a temperature change into a voltage change by applying a constant forward current. This solid-state imaging device has an advantage that it can be mass-produced using a silicon LSI (large scale integrated circuit) manufacturing process by using an SOI (silicon on insulator) substrate as a semiconductor substrate. In addition, even when a large number of infrared detection pixels are arranged in a matrix and connected to a common wiring, the function of row selection can be realized using the rectification characteristics of the pn junction, which is thermoelectric conversion means. Another feature is that it can be configured very simply.

  One index representing the performance of a solid-state imaging device is an equivalent noise temperature difference (NETD, hereinafter referred to as “NETD”) that expresses the temperature resolution of the solid-state imaging device. In order to improve the sensitivity of the solid-state image sensor, it is important to reduce the NETD, that is, to reduce the temperature difference of the solid-state image sensor corresponding to noise.

JP 2004-364241 A JP 2008-268155 A

  Embodiments of the present invention provide a solid-state imaging device with high sensitivity.

According to the embodiment, an infrared detection pixel that is provided on a semiconductor substrate and changes an output potential when receiving infrared rays, and a displacement amount of the output potential that is provided on the semiconductor substrate and receives infrared rays is the infrared detection pixel. A first pixel that is provided on the semiconductor substrate, is connected to the insensitive pixel, and applies a driving potential to the insensitive pixel. A selection line; a second row selection line provided on the semiconductor substrate; connected to the infrared detection pixel; for applying a driving potential to the infrared detection pixel; and provided on the semiconductor substrate; A driving circuit that sequentially selects two row selection lines and applies the driving potential; a vertical signal line provided on the semiconductor substrate and connected to both the infrared detection pixel and the insensitive pixel; Are found provided on the conductor substrate is connected to one end of the vertical signal line, and a first load transistor to flow a constant current, it is provided on the semiconductor substrate is connected to the other end of the vertical signal line, the first A first potential input when a row selection line is selected is held, and a difference between the first potential and a second potential input when the second row selection line is selected There is provided a solid-state imaging device comprising a correlated double sampling circuit that outputs a potential corresponding to. The first row selection line extends in the first direction, the second row selection line extends in the first direction, and a plurality of the first row selection lines are provided, and the vertical signal line extends in the first direction. A plurality of infrared detection pixels and a plurality of insensitive pixels are provided, and the same number of first load transistors as the vertical signal lines are provided. Connected to the vertical signal lines in one-to-one correspondence, and the same number of correlated double sampling circuits as the plurality of vertical signal lines are provided, corresponding to the plurality of vertical signal lines. And the plurality of infrared detection pixels are connected between each of the plurality of second row selection lines and each of the plurality of vertical signal lines. The plurality of insensitive pixels connected to each other. The correlated double sampling circuit has one and the other input terminals and one output terminal, and is connected to the one and the other input terminals. A differential amplifier that outputs a potential corresponding to the difference between the input potentials; a coupling capacitor having one end connected to the vertical signal line and the other end connected to one input terminal of the differential amplifier; and one end A feedback switch connected to one input terminal of the differential amplifier, the other end connected to the output terminal of the differential amplifier, one end connected to one input terminal of the differential amplifier, and the other end A feedback capacitor connected to the output terminal of the differential amplifier, a constant potential is input to the other input terminal of the differential amplifier, and the plurality of vertical signal lines are connected to the first input terminal. The vertical signal line and the second signal line A third potential at a position of the first row selection line connected to the insensitive pixel connected to the first vertical signal line; and The fourth potential at the position of the row selection line connected to the insensitive pixel connected to the second vertical signal line is different from the fourth potential of the second row selection line. A fifth potential at a position connected to the insensitive pixel connected to one of the vertical signal lines, and the insensitivity of the second row selection line connected to the second vertical signal line. The sixth potential at the position connected to the pixel is different from each other, the difference between the third potential and the fourth potential, the difference between the fifth potential and the sixth potential, Are equal.

1 is a circuit diagram illustrating a solid-state imaging device according to a first embodiment. It is a perspective view which illustrates the infrared detection pixel concerning a 1st embodiment. (A) And (b) is the top view and sectional drawing which illustrate the infrared rays detection pixel which concerns on 1st Embodiment, (a) is a top view by the BB 'line | wire shown to (b), (b) is sectional drawing by the AA 'line shown to (a). It is a perspective view which illustrates the insensitive pixel which concerns on 1st Embodiment. (A) And (b) is the top view and sectional drawing which illustrate the insensitive pixel which concerns on 1st Embodiment, (a) is a top view by the BB 'line | wire shown to (b), (b) is sectional drawing by the AA 'line shown to (a). It is a graph which illustrates the relationship between the voltage in the pn diode of the thermoelectric conversion part which concerns on 1st Embodiment, and an electric current. It is a circuit diagram which illustrates the solid-state image sensing device concerning the modification of a 1st embodiment. It is a circuit diagram which illustrates the solid-state image sensing device concerning a 2nd embodiment. It is a circuit diagram which illustrates the solid-state image sensing device concerning a 3rd embodiment.

(First embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the first embodiment will be described.
The present embodiment is an embodiment of a solid-state image sensor.

FIG. 1 is a circuit diagram illustrating a solid-state imaging device according to the first embodiment.
First, the configuration of the solid-state imaging device according to the first embodiment will be described.

  As shown in FIG. 1, the solid-state imaging device 1 is provided on a semiconductor substrate 11. An imaging region 12 is set in the solid-state imaging device 1. In the imaging region 12, a plurality of row selection lines 14 extending in the row direction (first direction) and a plurality of vertical signal lines 15 extending in the column direction (second direction) intersecting, for example, orthogonal to the row direction. Are provided in a grid pattern. Further, the imaging region 12 is provided with one reference potential line 20 extending in the column direction. The reference potential line 20 is disposed outside the region where the plurality of vertical signal lines 15 are provided.

  In the imaging area 12, a plurality of infrared detection pixels IR (Infrared) and a plurality of insensitive pixels TB (Thermal Black) are provided. The infrared detection pixel IR is disposed at the intersection of each row selection line 14 and each vertical signal line 15. The insensitive pixel TB is disposed at the intersection of each row selection line 14 and the reference potential line 20. A pn diode 16 is provided as a thermoelectric conversion unit in the infrared detection pixel IR and the insensitive pixel TB.

  A row selection circuit 17 and a drive potential generation circuit 55 are provided outside the imaging region 12. The row selection circuit 17 and the drive potential generation circuit 55 are arranged along the column direction on one side in the row direction when viewed from the imaging region 12 in order to facilitate connection with the row selection line 14. The row selection circuit 17 is a circuit for selecting the row selection line 14, and the drive potential generation circuit 55 is a circuit for applying a drive potential to the selected row selection line 14. Therefore, in the present specification, hereinafter, when referring to a circuit that exhibits the combined function of the row selection circuit 17 and the drive potential generation circuit 55, the row selection circuit 17 and the drive potential generation circuit 55 are collectively referred to as “drive”. Called “circuit”. Therefore, the drive circuit selects the row selection line 14 and applies a drive potential to the row selection line 14.

  In addition, on one side in the column direction when viewed from the imaging region 12, the same number of load transistors 18 as the total number of the vertical signal lines 15 and the reference potential lines 20 are provided. Each load transistor 18 is arranged in one-to-one correspondence with each vertical signal line 15 and reference potential line 20. Furthermore, one power line 56 extending in the row direction and one power signal line 57 extending in the row direction are provided on the same side as the load transistor 18 when viewed from the imaging region 12.

  On the other hand, the same number of differential amplifiers 19 as the number of vertical signal lines 15 are provided on the other side in the column direction when viewed from the imaging region 12. Each differential amplifier 19 is arranged in one-to-one correspondence with the vertical signal line 15. The differential amplifier 19 is provided with two input terminals and one output terminal.

  In addition, one voltage follower circuit 23 is provided on the same side as the differential amplifier 19 when viewed from the imaging region 12. The voltage follower circuit 23 is an operational amplifier that generates the same output potential as the input potential, and is a circuit that can reduce the impedance while the output potential remains the input potential. The voltage follower circuit 23 is provided with two input terminals and one output terminal, and the negative input terminal is connected to the output terminal. Further, the same number of horizontal selection transistors 26 as the differential amplifier 19 are provided on the same side as the differential amplifier 19 when viewed from the imaging region 12. Each horizontal selection transistor 26 is arranged in one-to-one correspondence with the differential amplifier 19. Furthermore, a column selection circuit 25 is provided on the same side as the differential amplifier 19 when viewed from the imaging region 12.

Next, the connection relationship of each component will be described.
Each row selection line 14 is connected to a plurality of infrared detection pixels IR arranged along the row selection line 14. That is, the anode of the pn diode 16 of the infrared detection pixel IR is connected to the row selection line 14. Each row selection line 14 is connected to one insensitive pixel TB arranged in the vicinity of the row selection line 14. That is, the anode of the pn diode 16 of the insensitive pixel TB is connected to the row selection line 14.

  A plurality of infrared detection pixels IR arranged along the vertical signal line 15 are connected to each vertical signal line 15. In other words, the vertical signal line 15 is connected to the cathode of the pn diode 16 of the infrared detection pixel IR. A plurality of insensitive pixels TB arranged along the reference potential line 20 are connected to the reference potential line 20. That is, the reference potential line 20 is connected to the cathode of the pn diode 16 of the insensitive pixel TB. One end of all row selection lines 14 is connected to the row selection circuit 17.

  One end of the corresponding vertical signal line 15 and reference potential line 20 is connected to one of the source and drain of each load transistor 18. Therefore, the cathodes of the pn diodes 16 of the infrared detection pixel IR and the insensitive pixel TB are connected to one of the source and drain of the load transistor 18 via the vertical signal line 15 and the reference potential line 20. The other of the source and drain is connected to the power supply line 56, and the gate of the load transistor 18 is connected to the power supply signal line 57.

  The other end of the reference potential line 20 is connected to the positive input terminal of the voltage follower circuit 23. A wiring 24 is connected to the output terminal of the voltage follower circuit 23. The other end of the vertical signal line 15 is connected to a positive input terminal of the two input terminals of the differential amplifier 19. The wiring 24 branches into the number of the differential amplifiers 19, and each of the branched wirings is connected to the negative input terminal of the two input terminals of the differential amplifier. That is, the potential of the reference potential line 20 is input to the negative input terminal of each differential amplifier 19 via the voltage follower circuit 23 and the wiring 24, and the potential of the vertical signal line 15 is input to the positive input terminal. Entered.

The output terminal of the differential amplifier 19 is connected to one of the source and drain of the horizontal selection transistor 26 associated with each differential amplifier 19. The other of the source and drain of the horizontal selection transistor 26 is connected to the output terminal 60 of the solid-state imaging device 1. The gate of the horizontal selection transistor 26 is connected to the column selection circuit 25.
In order to make the figure easy to see, only six infrared detection pixels IR are shown in FIG. That is, two infrared detection pixels IR are arranged along the row direction and three along the column direction. Accordingly, only three row selection lines 14 are shown, and only three insensitive pixels TB are shown. On the other hand, only two vertical signal lines 15, differential amplifiers 19 and horizontal selection transistors 26 are shown. However, in the actual solid-state imaging device 1, more infrared detection pixels IR and insensitive pixels TB are provided.

Next, the structures of the infrared detection pixel IR and the insensitive pixel TB according to the first embodiment will be described.
FIG. 2 is a perspective view illustrating the infrared detection pixel IR according to the first embodiment.
FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating the infrared detection pixel according to the first embodiment, and FIG. 3A is a plan view taken along line BB ′ shown in FIG. (B) is sectional drawing by the AA 'line shown to (a).

  As shown in FIGS. 3A and 3B, an SOI substrate is used as the semiconductor substrate 11. The SOI substrate is a substrate in which an insulating BOX layer 29 is provided on a support substrate 28 and a silicon layer 30 is provided on the BOX layer 29. The silicon layer 30 is formed of a silicon single crystal. A wiring layer 41 is provided on the semiconductor substrate 11, and an infrared absorption film 35 is provided on the wiring layer 41. In the wiring layer 41, contacts 62 and connection wirings 34 are embedded in an insulating material 61.

  On the upper surface of the support substrate 28, an inverted quadrangular concave portion 42 is formed. In the region immediately above the recess 42, the BOX layer 29, the silicon layer 30, the wiring layer 41, and the infrared absorption film 35 are selectively removed, and two gaps 43a and 43b (hereinafter collectively referred to as “gap 43”). Say). When viewed from above, the shape of the remaining portions of the BOX layer 29, the silicon layer 30, the wiring layer 41, and the infrared absorption film 35 in the region immediately above the recess 42 is rectangular, inside the recess 42, and from the outer edge of the recess 42 It is arranged in a remote area. The remaining portion forms a thermoelectric conversion portion 32 having a substantially rectangular parallelepiped shape.

  In the silicon layer 30 of the thermoelectric conversion section 32, two p-type regions 44a and 44b that are separated from each other are formed, and the n-type region 45a and the p-type regions 44a and 44b are part of the upper layer portion of each of the p-type regions 44a and 44b. 45b is formed. A pn diode 16a is formed by the p-type region 44a and the n-type region 45a, and a pn diode 16b is formed by the p-type region 44b and the n-type region 45b. An element isolation insulating film 46 is provided around the pn diodes 16a and 16b (also collectively referred to as “pn diode 16”).

  In the wiring layer 41 of the thermoelectric conversion section 32, contacts 62 a to 62 d and connection wirings 34 a to 34 c are provided in the insulating material 61. Contacts 62a to 62d are connected to p-type region 44a, n-type region 45a, p-type region 44b, and n-type region 45b, respectively. The connection wiring 34a is connected to the contact 62a, the connection wiring 34b is connected to the contacts 62b and 62c, and the connection wiring 34c is connected to the contact 62d.

  Hereinafter, in this specification, an XYZ orthogonal coordinate system is employed to describe the infrared detection pixel IR and the insensitive pixel TB. In this XYZ orthogonal coordinate system, the direction from the p-type region 44b to the p-type region 44a is the + X direction, the opposite direction is the -X direction, and is a direction perpendicular to the upper surface of the semiconductor substrate 11 and upward. The direction to go is the + Z direction, the downward direction is the -Z direction, one of the directions orthogonal to both the + X direction and the + Z direction is the + Y direction, and the opposite direction is the -Y direction. The X direction and the Y direction are on the same plane as the above-described row direction and column direction, but are set independently of each other.

  From the end portion of the thermoelectric conversion portion 32 on the + X direction side, a support portion 33a made of the wiring layer 41 extends in the + Y direction. The support portion 33a extends in the + Y direction from the end portion on the + X direction side of the side surface facing the + Y direction of the thermoelectric conversion portion 32, and then is in the region immediately above the recess 42 and seen from the thermoelectric conversion portion 32 in the + X + Y direction side. Is bent in the −X direction at the position, passes through the + Y direction side of the thermoelectric conversion part 32, and reaches the position on the −X + Y direction side as viewed from the thermoelectric conversion part 32 in the region directly above the recess 42. , Bent toward the -Y direction, passes through the side of the thermoelectric conversion part 32 on the -X direction side, reaches the edge immediately above the recess 42, and is integrated with the wiring layer 41 around the gap 43. . In this way, the support portion 33a is bent twice, and makes a half turn around the thermoelectric conversion portion 32. Further, in the support portion 33a, the pixel wiring 36a is provided in the insulating material 61 along the longitudinal direction of the support portion 33a. The pixel wiring 36a is formed integrally with the connection wiring 34a.

  On the other hand, from the end portion of the thermoelectric conversion portion 32 on the −X direction side, a support portion 33b made of the wiring layer 41 extends in the −Y direction. The support portion 33b extends from the end portion on the −X direction side in the −Y direction among the side surfaces facing the −Y direction of the thermoelectric conversion portion 32, and then is in the region immediately above the recess 42 and viewed from the thermoelectric conversion portion 32. Bends in the + X direction at the position on the −X−Y direction side, passes through the side on the −Y direction side of the thermoelectric conversion unit 32, and is in the region immediately above the concave portion 42 and viewed from the thermoelectric conversion unit 32 in the + X−Y direction After reaching the position on the side, it bends in the + Y direction, passes through the side on the + X direction side of the thermoelectric converter 32, reaches the edge of the region directly above the recess 42, and the wiring layer 41 around the gap 43 It is integrated with. As described above, the support portion 33b is bent twice so as to make a half circumference around the thermoelectric conversion portion 32. In the support portion 33b, pixel wirings 36b are provided in the insulating material 61 along the longitudinal direction of the support portion 33b. The pixel wiring 36b is formed integrally with the connection wiring 34c.

  The support part 33a and the support part 33b are not in contact with each other. Further, portions of the support portions 33 a and 33 b other than both end portions are not in contact with any member including the thermoelectric conversion portion 32 and the wiring layer 41 around the gap 43. Moreover, the thermoelectric conversion part 32 is not in contact with members other than the edge part of the support parts 33a and 33b. Thereby, the thermoelectric conversion part 32 is supported only by the support parts 33a and 33b in the region directly above the recess 42. And the support parts 33a and 33b are made into the elongate structure by carrying out the circumference of the thermoelectric conversion part 32 half. On the other hand, as viewed from above, the gaps 43a and 43b each circulate substantially around the thermoelectric converter 32 in a spiral shape. As described above, in the infrared detection pixel IR, a hollow structure including the recess 42 and the gaps 43a and 43b is formed below and to the side of the thermoelectric conversion unit 32.

The pixel wirings 36 a and 36 b connect the anode of the pn diode 16 a and the row selection line 14 of the thermoelectric conversion unit 32 and the cathode of the pn diode 16 b and the vertical signal line 20. An example of the material of the pixel wirings 36a and 36b is titanium nitride.
With such a structure, the infrared detection pixel IR can accumulate heat generated according to incident infrared rays and output a potential based on this heat to the vertical signal line 15. This is because, by forming the hollow structure, it is possible to suppress the heat of the thermoelectric conversion unit 32 from being transmitted to the inside of the semiconductor substrate 11, the wiring layer 41, and the infrared absorption film 35 to be dissipated to the surroundings.

An example of a method for forming the recess 42 is as follows. First, the silicon layer 30 and the BOX layer 29 excluding the thermoelectric conversion portion 32 and the support portion 33 on the surface of the semiconductor substrate 11 are removed by deep dry etching (DEEP RIE) to form gaps 43a and 43b. Thereafter, an etching solution is injected from the gaps 43a and 43b, and the surface portion of the support substrate 28 is wet-etched to form the recesses 42. In this embodiment, a silicon substrate having a surface orientation of (100) is used as the support substrate 28, and this is wet etched to form an inverted quadrangular concave portion 42 having a convex shape downward. At this time, the BOX layer 29 functions as a barrier layer in the wet etching of the support substrate 28 and protects the silicon layer 30 provided with the thermoelectric conversion portion 32 from the wet etching.
The semiconductor substrate 11 is not limited to an SOI substrate. If the thermoelectric conversion part 32 can be bridge | crosslinked by the support part 33 on the recessed part 42, semiconductor substrates 11 other than an SOI substrate can be used.

Next, the structure of the insensitive pixel TB will be described.
FIG. 4 is a perspective view illustrating an insensitive pixel according to the first embodiment.
FIGS. 5A and 5B are a plan view and a cross-sectional view illustrating the insensitive pixel according to the first embodiment, and FIG. 5A is a plan view taken along line BB ′ shown in FIG. (B) is sectional drawing by the AA 'line shown to (a).

  As shown in FIGS. 4, 5A and 5B, in the insensitive pixel TB, the gap 43 is not formed as compared with the above-described infrared detection pixel IR, and two etching grooves are formed. 39a and 39b are formed. When viewed from above, the shape of the etching groove 39a is L-shaped along the edge facing the + X direction and the edge facing the −Y direction in the pn diode 16a. The shape of the etching groove 39b is L-shaped along the end edge of the pn diode 16b facing the −X direction and the end edge of the pn diode 16b facing the + Y direction. Further, the outer edge of the recess 42 when viewed from above (+ Z direction) coincides with the outer edges of the etching grooves 39a and 39b, and is smaller than the recess 42 of the infrared detection pixel IR. Other configurations of the insensitive pixel TB are the same as those of the infrared detection pixel IR.

An example of a method for forming the recess 42 in the insensitive pixel TB is as follows.
First, the etching groove 39 is formed. The etching groove 39 is formed by removing the silicon layer 30 and the BOX layer 29 from the surface of the semiconductor substrate 11 by deep dry etching (DEEP RIE). However, the etching groove 39 is formed at a position closer to the pn diode 16 than the gap 43.
In the present embodiment, the etching grooves 39 are formed at two locations along the mutually opposing corners of the thermoelectric conversion portion 32 as viewed from above so that the concave portion 42 can be efficiently removed under the thermoelectric conversion portion 32. Form. Thereafter, an etching solution is injected from the etching groove 39, and a recess 42 is formed by wet etching the upper portion of the support substrate 28 immediately below the BOX layer 29.

In the infrared detection pixel IR, the thermoelectric conversion part 32 is supported on the recess 42 only by the support parts 33a and 33b. On the other hand, in the insensitive pixel TB, the thermoelectric conversion unit 32 includes the etching grooves 39 a and 39 b among the BOX layer 29, the silicon layer 30, the wiring layer 41, and the infrared absorption film 35 disposed immediately above the recess 42. It is supported by all parts (hereinafter referred to as “peripheral parts”) except for the above.
The reason why the recess 42 is provided also in the insensitive pixel TB is to make the characteristics of the pn junction in the pn diode 16 coincide with the infrared detection pixel IR. By forming the recess 42, the pn diode 16 can be prevented from receiving interference from the electric field from the support substrate 28 made of silicon.

Accordingly, the amount of heat conducted from the thermoelectric conversion unit 32 of the infrared detection pixel IR through the support portions 33a and 33b and other than the thermoelectric conversion unit is such that the heat of the thermoelectric conversion unit 32 of the insensitive pixel TB is transmitted to the peripheral portion. Thus, it is smaller than the amount of heat conduction except for the thermoelectric conversion section 32.
That is, the heat transfer efficiency between the thermoelectric conversion part of the infrared detection pixel and the outside of the infrared detection pixel is higher than the heat transfer efficiency between the thermoelectric conversion part of the insensitive pixel and the outside of the insensitive pixel. Here, “the heat transfer efficiency between the thermoelectric conversion unit and the outside of the pixel” refers to the efficiency when the heat generated in the thermoelectric conversion unit is discharged to the outside of the infrared detection pixel, for example, a certain amount of heat Is generated in the thermoelectric conversion unit, a predetermined ratio of the amount of heat is evaluated by the time required to transfer it to the outside of the infrared detection pixel. The shorter this time, the higher the heat transfer efficiency.
Therefore, the fluctuation amount of the output potential when the infrared detection pixel IR receives the infrared ray is larger than the fluctuation amount of the output potential when the insensitive pixel TB receives the infrared ray.

(Operation of the solid-state imaging device according to the first embodiment)
Next, the operation of the solid-state imaging device according to the first embodiment will be described.
As shown in FIG. 1, the drive circuit generates the bias potential V _d of the drive potential. Then, the row selection line 14 to which the infrared detection pixel IR and the insensitive pixel TB are connected is selected one by one in order, and the bias potential _Vd is applied to the infrared detection pixel IR and the insensitive pixel TB. The load transistor 18 to which the cathode of the pn diode 16 of the infrared detection pixel IR and the insensitive pixel TB is connected is used as a constant current source. In other words, the load transistor 18 is operated in the saturation region, and the infrared detection pixels IR and the insensitive pixels TB connected to the selected row selection line 14 according to the gate potential supplied to the gate electrode of the load transistor 18. A constant current is supplied to the pn diode 16. At this time, the source potential of the load transistor 18 is set to V _d0 .

When the drive circuit applies the bias potential V _d to the pn diode 16 of the selected row selection line 14, the series potential (V _d −V _d0 ) is applied to the pn diode 16 of the selected row selection line 14.
Unselected row select lines 14 are reverse biased. Therefore, the potentials of the infrared detection pixels IR and the insensitive pixels TB connected to the unselected row selection line 14 are not reflected on the vertical signal line 15. That is, the pn diode 16 has a pixel selection function.

  In the infrared detection pixel IR, when the thermoelectric conversion unit 32 receives infrared rays, the infrared rays are converted into heat in the infrared absorption film 35, and the temperature of the thermoelectric conversion unit 32 rises. At this time, since the thermoelectric conversion part 32 is supported only by the support parts 33a and 33b and is almost thermally insulated from the surroundings, the temperature rises sensitively by receiving infrared rays. Then, in the infrared detection pixel IR in the selected row selection line 14, the potential change due to the temperature rise of the thermoelectric conversion unit 32 is reflected on the vertical signal line 15.

  On the other hand, in the insensitive pixel TB, when the thermoelectric conversion unit 32 receives infrared rays, the infrared rays are converted into heat by the infrared absorption film 35, and the thermoelectric conversion unit 32 is connected to the surroundings via the peripheral portion. Since it is thermally connected, the converted heat is quickly discharged from the thermoelectric conversion unit 32. For this reason, in the insensitive pixel TB, even if infrared rays are received, the temperature of the thermoelectric conversion part 32 hardly rises.

FIG. 6 is a graph illustrating the relationship between the potential and current in the pn diode of the thermoelectric conversion unit according to the first embodiment.
As shown in FIG. 6, in the present embodiment, the relationship between the voltage and current of the pn diode 16 is a forward characteristic region, that is, a region where the current increases when the voltage supplied in the forward direction is increased. Used in. A constant current is passed through such a pn diode 16 and the change in potential is measured.
As shown in FIG. 6, for example, the potential between the anode and the cathode of the pn diode 16 when a current of 1 ampere ([A]) is passed as a constant current when no infrared light is received is 5 volts. Suppose there was. When infrared rays are incident on the infrared absorption film, the infrared absorption film 35 of the infrared detection pixel IR generates heat by the incident infrared rays. And the IV characteristic which a pn diode shows changes. Then, under the condition that a constant current of 1 ampere flows, the voltage between the anode and the cathode of the pn diode 16 after the incidence of infrared rays changes to 4.999 volts as shown in FIG. 6, for example. In this way, the pn diode 16 in the thermoelectric conversion unit 32 converts the heat generated in the infrared absorption film 35 into an electrical signal.

When the forward potential of the pn diode when not receiving infrared rays is V _f0 and the potential based on the temperature rise of the thermoelectric conversion unit 32 by infrared rays is V _sig , the potential on the vertical signal line 15 is V _d − (V _f0 −V _sig. )
For example, when the subject temperature changes by 1K (Kelvin), the temperature of the infrared detection pixel changes by about 5 mK. When the thermoelectric conversion efficiency is 10 mV / K, the potential between the anode and the cathode of the pn diode decreases by 50 μV. Therefore, the change in potential in the vertical signal line 15 is {V _d − (V _f0 −V _sig ) − (V _d −V _f0 )}, that is, the potential of the vertical signal line 15 is increased by about 50 μV of V _sig. .
A change in potential generated in the vertical signal line 15 is input to one input terminal of the differential amplifier 19 via the vertical signal line 15.

The potential of the reference potential line 20 becomes the output potential (V _d −V _f0 ) of the insensitive pixel TB connected to the selected row selection line 14. Here, since the forward potentials of the insensitive pixel TB and the infrared detection pixel IR at the time of no infrared reception are designed to be equal, the V _f0 of each other is the same. The potential of the reference potential line 20 of the insensitive pixel TB is impedance-converted by the voltage follower circuit 23, and the same potential is output and connected to the other input terminal of the differential amplifier 19.

In the differential amplifier 19, the potential difference V _sig input to the two terminals is amplified and output. The output potential is read for each column for each horizontal selection transistor 26 selected by the column selection circuit 25. Then, the drive circuit sequentially selects the row selection line 14, thereby repeating the above-described operation and reading out the fluctuation amount of the output potential due to the reception of infrared rays for all infrared detection pixels IR.

(Effect of the solid-state imaging device according to the first embodiment)
Next, effects of the solid-state imaging device according to the first embodiment will be described.
The solid-state imaging device according to the present embodiment applies a bias potential to the infrared detection pixel IR and the insensitive pixel TB through the same row selection line 14 and outputs the infrared detection pixel IR to two input terminals of the differential amplifier 19. The potential and the output potential of the insensitive pixel TB are input, and a potential corresponding to the difference is output. At this time, since the circuit from the insensitive pixel TB to the differential amplifier 19 is formed on the same semiconductor substrate as the infrared detection pixel IR, a single power supply potential can be used. Thereby, the detection sensitivity of a solid-state image sensor can be improved. In addition, since the circuit configuration can be simplified, noise can be reduced and the solid-state imaging device can be downsized.

Further, not only the infrared detection pixel IR but also the insensitive pixel TB is provided with a recess 42. Therefore, in the insensitive pixel TB, since the electric field interference of the semiconductor substrate 11 is not received, the detection sensitivity of the solid-state imaging device 1 can be improved.
In addition, by providing the infrared detection pixel IR and the insensitive pixel TB on the SOI substrate, the thermoelectric conversion portion 32 can be protected from etching when the recess 42 is formed. Therefore, the pixel can be formed with high accuracy and the solid-state imaging device 1 having high sensitivity can be provided.
Furthermore, since the pn diode 16 is formed of a silicon single crystal, there is little variation in characteristics for each pn diode 16. In addition, since the pn diode 16 formed in the silicon single crystal behaves almost as shown in the energy band diagram, the characteristics of the thermoelectric converter can be accurately controlled. This also increases the sensitivity of the solid-state imaging device.

(Modification of the first embodiment)
Next, a solid-state image sensor according to a modification of the first embodiment will be described.
FIG. 7 is a circuit diagram illustrating a solid-state imaging device according to a modification of the first embodiment.
In the first embodiment, as shown in FIG. 1, the reference potential line 20 is provided farther than the plurality of vertical signal lines 15 when viewed from the drive circuit.

  As shown in FIG. 7, in this modification, the reference potential line 20 is provided closer to the plurality of vertical signal lines 15 when viewed from the drive circuit. The configuration other than the above in this modification is the same as that in the first embodiment, and corresponds to the difference in output potential between the infrared detection pixel IR and the insensitive pixel TB input to each of the two input terminals of the differential amplifier. Potential to be output from the output terminal of the differential amplifier. Therefore, also in this modification, the solid-state image sensor 1 with high sensitivity can be obtained.

(Second Embodiment)
Next, a second embodiment will be described.
In the solid-state imaging device 1 according to the first embodiment, the output potential of the insensitive pixel TB is input equally to the differential amplifiers 19 in all columns. However, since the forward current of the diode 16 flows through the row selection line 14, the bias potential as the drive potential drops according to the wiring resistance of the row selection line 14. For this reason, the bias potential becomes higher in the column closer to the drive circuit, and shading of the bias potential occurs. This results in shading of the vertical signal line 15 and means that the potential input from the vertical signal line 15 differs for each differential amplifier 19 associated with the vertical signal line 15.

In the second embodiment, shading correction is performed by creating an equivalent shading for the potential of the wiring 24 in the insensitive pixel TB.
FIG. 8 is a circuit diagram illustrating a solid-state imaging device according to the second embodiment.
As shown in FIG. 8, the solid-state imaging device 2 according to the present embodiment is provided on a semiconductor substrate 11. An imaging region 12 is set in the solid-state imaging device 2.
Further, the imaging region 12 includes a plurality of row selection lines 14 extending in the row direction (first direction) and a plurality of vertical signals extending in the column direction (second direction) intersecting the row direction, for example, orthogonal to the row direction. Lines 15 are provided in a grid pattern. Further, the imaging region 12 is provided with one reference potential line 20 extending in the column direction. The reference potential line 20 is disposed outside the region where the plurality of vertical signal lines 15 are provided.

  In the present embodiment, the position where the drive circuit is arranged is important. The drive circuit is arranged on the side where there is no adjacent vertical signal line 15 when viewed from the reference potential line 20. A second load transistor 40 is provided outside the imaging region 12 on the same side as the differential amplifier 19. The same number of the second load transistors 40 as the vertical reference lines 15 are provided. A power supply line 58 and a power supply signal line 59 are provided on the same side as the differential amplifier 19 when viewed from the imaging region 12.

Next, the connection relationship of each component will be described.
A wiring 24 is connected to the output terminal of the voltage follower circuit 23. The wiring 24 is the same length as the length from the reference potential line 20 to the vertical signal line 15 in the row selection line 14, and the other of the two input terminals of the differential amplifier 19 associated with the vertical signal line 15. It is connected to the. Further, the source / drain of one load transistor 40 is provided between the output terminal of the voltage follower circuit 23 and the input terminal of the differential amplifier 19 and between the input terminals of the differential amplifier 19 in the wiring 24. One side is connected. The other of the source and drain of the load transistor 40 is connected to the power supply line 58. The gate of the load transistor 40 is connected to the power signal line 59. The load transistor 40 operates in the saturation region, and supplies a constant current to the connected wiring 24 in accordance with the voltage of its gate. That is, the load transistor 40 acts as a constant current source. The source voltage of the load transistor 40 is set to _Vd0 .

  The load transistor 40 has the same structure as the load transistor 18 used as the current source of the above-described infrared detection pixel IR, and has the same shape and material. Further, the power line 58 is connected to the power line 56, and the power signal line 59 is connected to the power signal line 57. Therefore, the source voltage and the gate voltage applied to the load transistor 40 are also equal to the source voltage and the gate voltage of the load transistor 18, respectively. The wiring 24 has a resistance value per unit length that is the same as a resistance value per unit length in the row selection line 14. Other configurations in the present embodiment are the same as those in the first embodiment.

(Operation of the solid-state imaging device according to the second embodiment)
Next, the operation of the solid-state imaging device according to the second embodiment will be described.
As shown in FIG. 8, the drive circuit selects the infrared detection pixels IR one by one in order via the row selection line 14 and applies a bias potential to the infrared detection pixels IR. As a result, the pn diode 16 in the thermoelectric converter 32 of the infrared detection pixel IR is forward-biased. Then, a forward bias current including a potential change due to the temperature rise of the infrared detection pixel IR flows through the vertical signal line 15.

When the change in the potential of the infrared detection pixel IR when receiving infrared rays is V _sig , the potential of the vertical signal line 15 is {V _d − (V _f0 −V _sig )}. Here, V _f0 is a pn junction forward potential when no infrared ray is received, and V _sig is a change in potential based on a temperature rise of the thermoelectric converter 32 due to infrared ray reception.

In the second embodiment, since a forward current of a diode flows through the row selection line 14, a bias potential drop occurs according to the wiring resistance of the row selection line 14. That is, the potential of (N−1) I _f · R ₀ is added to the differential amplifier 19, and eventually, {V _d − (V _f0 −V _sig ) + (N−1) I _f · R ₀ } Potential is input.
Here, N is the number of infrared detection pixels IR and insensitive pixels TB from the drive circuit, that is, the number of reference potential lines 20 and vertical signal lines 15, _If is a constant current, and _R0 is a row selection line between columns. The resistance value is 14. When the distance between the reference potential line 20 and the vertical signal line 15 is equal, I _f · R ₀ corresponds to a drop in potential between adjacent vertical signal lines 15 in one column, that is, the row selection line 14.
In this way, the potential generated in the vertical signal line 15 is input to one input terminal of the differential amplifier 19 via the vertical signal line 15.

The potential of the reference potential line 20 of the insensitive pixel TB is (V _d −V _f0 ) when selected. Here, since the forward potentials of the insensitive pixel TB and the infrared detection pixel IR at the time of no infrared reception are designed to be equal, the V _f0 of each other is the same.
In the second embodiment, shading correction is performed by creating equivalent shading on the reference potential line 20 side as well. For this reason, one load transistor 40 is connected to the wiring 24 for each column, that is, for each length from the reference signal line 20 to the vertical signal line 15 or between adjacent vertical signal lines 15. The load transistor 40 supplies a constant current to the wiring 24 as a constant current source.

Therefore, the resistance of the wiring 24 is R ₀ , and the constant current _If flows through the wiring 24. Therefore, the potential on the output side of the voltage follower circuit is (V _d −V _f0 ) at {(N−1) I _f · R ₀ } is added.
With this configuration, it is possible to create a potential gradient that is exactly the same as that of the row selection line 14 in the wiring 24, and the difference in potential input to the two input terminals of the differential amplifier 19 is only V _sig .

(Effect of the solid-state imaging device according to the second embodiment)
Next, effects of the solid-state imaging device according to the second embodiment will be described.
With the configuration of the solid-state imaging device according to the second embodiment, a potential gradient equivalent to that of the row selection line 14 can be created in the wiring 24, so that the potential input to the two input terminals of the differential amplifier 19 can be reduced. Any difference is only V _sig . Therefore, it is possible to provide a solid-state imaging device that suppresses shading and has high detection sensitivity. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

(Third embodiment)
Next, a third embodiment will be described.
In the first and second embodiments, the insensitive pixels TB are arranged along the reference potential lines 20, whereas in the present embodiment, the insensitive pixels TB are arranged along the row selection lines 14. Be placed. The insensitive pixel TB is connected to the vertical signal line 15 in the same column as the infrared detection pixel IR. A correlated double sampling circuit is provided in association with the vertical signal line 15.

FIG. 9 is a circuit diagram illustrating a solid-state imaging device according to the third embodiment.
As shown in FIG. 9, the solid-state imaging device 3 is provided on the semiconductor substrate 11. An imaging region 12 is set in the solid-state imaging device 3.
Further, the imaging region 12 includes a plurality of row selection lines 14 extending in the row direction (first direction) and a plurality of vertical signals extending in the column direction (second direction) intersecting the row direction, for example, orthogonal to the row direction. Lines 15 are provided in a grid pattern. In the present embodiment, unlike the first and second embodiments described above, the reference potential line 20 is not provided.

In the imaging region 12, a plurality of infrared detection pixels IR and a plurality of insensitive pixels TB are provided. The insensitive pixel TB is connected to the intersection of one row selection line 14 and all the vertical signal lines 15. On the other hand, the infrared detection pixels IR are connected to the intersections of the remaining row selection lines 14 and all the vertical signal lines 15. Therefore, the infrared detection pixel IR and the insensitive pixel TB are connected to different row selection lines 14.
In addition, the same number of load transistors 18 as the number of vertical signal lines 15 are provided outside the imaging region 12. Each load transistor 18 is arranged in one-to-one correspondence with each vertical signal line 15.

Furthermore, the same number of correlated double sampling circuits 66 as the number of vertical signal lines 15 are provided on the opposite side of the imaging region 12 from the load transistors 18 in the column direction.
In the correlated double sampling circuit 66, a coupling capacitor 51, a differential amplifier 52, a constant voltage power source V2, a feedback switch 53, and a feedback capacitor 54 are provided. The differential amplifier 52 includes two input terminals and one output terminal, and outputs a potential corresponding to the difference between the potentials input to the two input terminals from the output terminal.

  Further, the same number of horizontal selection transistors 26 as the number of correlated double sampling circuits 66 are provided on the same side as the correlated double sampling circuits 66 in the column direction outside the imaging region 12. Each horizontal selection transistor 26 is arranged in a one-to-one correspondence with the correlated double sampling circuit 66.

Next, the connection relationship of the solid-state imaging device according to the third embodiment will be described.
One end of the coupling capacitor 51 in the correlated double sampling circuit 66 is connected to the other end of the vertical signal line 15. The other end of the coupling capacitor 51 is connected to the positive electrode of the differential amplifier 52 in the correlated double sampling circuit 66. A constant potential V <b> 2 is applied to the negative electrode of the differential amplifier 52 in the correlated double sampling circuit 66. The feedback switch 53 and the feedback capacitor 54 in the correlated double sampling circuit 66 are connected in parallel. One end of each of the feedback switch 53 and the feedback capacitor 54 connected in parallel is connected to the positive electrode of the differential amplifier 52, and the other end is connected to the output terminal of the differential amplifier 52.
The output terminal of the differential amplifier 52 in the correlated double sampling circuit 66 is connected to one of the source and drain of the horizontal selection transistor 26 associated with each correlated double sampling circuit 66.

(Operation of the solid-state imaging device according to the third embodiment)
Next, the operation of the solid-state imaging device according to the third embodiment will be described.
In the present embodiment, the insensitive pixel TB and the infrared detection pixel IR are connected to different row selection lines 14, and the drive potential is applied to these row selection lines 14 at different times. The output potentials of the sensitivity pixel TB and the infrared detection pixel IR cannot be compared simultaneously.
Therefore, a circuit that applies a driving potential to the insensitive pixel TB and the infrared detection pixel IR at different times and amplifies the difference between the output potentials of the two pixels and outputs the same is adopted.

First, in the first period, a bias potential _Vd is applied as a drive potential to the row selection line 14 to which the insensitive pixel TB is connected. Then, the potential of the vertical signal line 15 becomes _(V d _{-V f0).} This potential value is, for example, 1.0 V here.
At this time, when the feedback switch 53 is turned on (short-circuited), the circuit including the differential amplifier 52 and the feedback switch 53 functions in the same manner as the voltage follower circuit. Therefore, the input potential and output potential of the differential amplifier 52 are equal to the constant voltage power supply V2. Here, the constant potential V2 is a constant potential applied to the differential amplifiers 52 in all columns, and is set to 1.5 V, for example. At this time, the potential of one end to which the vertical signal line 15 of the coupling capacitor 51 is connected is 1.0 V, and the potential of the other end to which the differential amplifier 52 of the coupling capacitor 51 is connected is 1.5 V. Subsequently, when the feedback switch 52 is turned off (opened), the above-described potential relationship is maintained.

Next, when a bias potential V _d is applied as a drive potential to the row selection line 14 to which the infrared detection pixel IR is connected in the second period, the potential of the vertical signal line 15 becomes V _d − (V _f0 −V _sig. ) This potential is set to, for example, 1.001V.
Then, since the potential difference between both ends of the coupling capacitor 51 is maintained, the potential of one end to which the vertical signal line 15 of the coupling capacitor 51 is connected becomes higher by 0.001V than the first period. As a result, the potential at the other end to which the differential amplifier 52 of the coupling capacitor 51 is connected is also increased to 1.501V.
At this time, if the gain of the differential amplifier 52 is sufficiently high, the correlated double sampling circuit 66 including the coupling capacitor 51, the differential amplifier 52, and the feedback capacitor 54 becomes an integrating circuit. When the capacitance value of the coupling capacitor 51 is C _c and the capacitance value of the feedback capacitor 54 is C _fb , the output potential is (C _c / C _fb ) · V _sig . For example, if C _c is 5 pF and C _fb is 0.5 pF, the output potential is 0.01 V from (5 / 0.5) · 0.001, and the change in potential V due to infrared absorption in the infrared detection pixel IR V _Sig is amplified 10 times.

(Effect of the solid-state imaging device according to the third embodiment)
Next, effects of the solid-state imaging device according to the third embodiment will be described.
Even in the case where the drive potential V _d supplied to the diode is different for each vertical signal line by the shading described in the second embodiment, V _d is totally reflected in the output potential of the differential amplifier 52 in this embodiment. Since this is not done, shading can be canceled.
Therefore, a highly sensitive solid-state imaging device can be provided.

  In the present embodiment, the pn diode 16 is used as the thermoelectric conversion unit 32, but another member may be provided as the thermoelectric conversion unit 32. Examples of other thermoelectric conversion part materials include vanadium oxide, amorphous silicon, and amorphous silicon germanium. These materials are characterized by excellent sensitivity.

  According to the embodiment described above, it is possible to provide a solid-state imaging device capable of improving sensitivity.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

1, 2: 3, solid-state imaging device, 11: semiconductor substrate, 12: imaging region, 14: row selection line, 15: vertical signal line, 16: pn diode, 17: row selection circuit, 18: load transistor, 19: Differential amplifier, 20: Reference potential line, 23: Voltage follower circuit, 24: Wiring, 25: Column selection circuit, 26: Horizontal selection transistor, 28: Support substrate, 29: BOX layer, 30: Silicon layer, 32: Thermoelectric Conversion unit 33, 33a, 33b: support unit, 34, 34a, 34b, 34c: connection wiring, 35: infrared absorption film, 36, 36a, 36b: pixel wiring, 39: etching groove, 40: load transistor, 41 : Wiring layer, 42: recess, 43, 43a, 43b: gap, 51: coupling capacitor, 52: differential amplifier, 53: feedback switch, 54: feedback capacitor, 55 Drive potential generation circuit, 56, 58: power supply line, 57, 59: power supply signal line, 60: output terminal, 61: insulating material, 62, 62a, 62b, 62c, 62d: contact, 66: correlated double sampling circuit, IR: infrared detection pixel, TB: insensitive pixel, V2: constant potential

Claims (1)

An infrared detection pixel provided on a semiconductor substrate, the output potential of which varies when receiving infrared rays;
An insensitive pixel provided on the semiconductor substrate and having a displacement amount of an output potential when receiving infrared rays is smaller than a displacement amount of an output potential when the infrared detection pixels receive the infrared rays; and
A first row selection line provided on the semiconductor substrate, connected to the insensitive pixel and applying a driving potential to the insensitive pixel;
A second row selection line provided on the semiconductor substrate, connected to the infrared detection pixel and applying a driving potential to the infrared detection pixel;
A driving circuit provided on the semiconductor substrate and sequentially selecting the first and second row selection lines and applying the driving potential;
A vertical signal line provided on the semiconductor substrate and connected to both the infrared detection pixel and the insensitive pixel;
Wherein provided on the semiconductor substrate, it is connected to one end of the previous SL vertical signal line, and a first load transistor to flow a constant current,
A first potential that is provided on the semiconductor substrate and is connected to the other end of the vertical signal line, and that is input when the first row selection line is selected; A correlated double sampling circuit that outputs a potential corresponding to a difference from a second potential inputted when the second row selection line is selected;
With
The first row selection line extends in a first direction,
The second row selection line extends in the first direction, and a plurality of the second row selection lines are provided.
The vertical signal line extends in a second direction intersecting the first direction, and a plurality of the vertical signal lines are provided.
A plurality of the infrared detection pixels and the insensitive pixels are provided,
The first load transistors are provided in the same number as the vertical signal lines, and are connected to the vertical signal lines in a one-to-one correspondence.
The correlated double sampling circuits are provided in the same number as the plurality of vertical signal lines, are associated with the plurality of vertical signal lines in a one-to-one relationship, and are connected to the associated vertical signal lines,
The plurality of infrared detection pixels are connected between each of the plurality of second row selection lines and each of the plurality of vertical signal lines,
The plurality of insensitive pixels are connected between the first row selection line and the plurality of vertical signal lines,
The correlated double sampling circuit includes:
A differential amplifier having one and other input terminals and one output terminal, and outputting a potential corresponding to a difference between potentials input to the one and other input terminals;
A coupling capacitor having one end connected to the vertical signal line and the other end connected to one input terminal of the differential amplifier;
A feedback switch having one end connected to one input terminal of the differential amplifier and the other end connected to the output terminal of the differential amplifier;
A feedback capacitor having one end connected to one input terminal of the differential amplifier and the other end connected to the output terminal of the differential amplifier;
Have
A constant potential is input to the other input terminal of the differential amplifier,
The plurality of vertical signal lines include the first vertical signal line and the second vertical signal line,
A third potential at a position of the first row selection line connected to the insensitive pixel connected to the first vertical signal line, and the second potential of the first row selection line. The fourth potential at the position connected to the insensitive pixel connected to the vertical signal line is different from each other.
A fifth potential of the second row selection line at a position connected to the insensitive pixel connected to the first vertical signal line, and the second potential of the second row selection line. The sixth potential at the position connected to the insensitive pixel connected to the vertical signal line is different from each other,
A solid-state imaging device, wherein a difference between the third potential and the fourth potential is equal to a difference between the fifth potential and the sixth potential.

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