JP2006332796A - Photodetector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photodetector capable of sufficiently eliminating an offset error or the like. <P>SOLUTION: The photodetector 1 includes: photodiodes PD<SB>m, n</SB>, switches SW<SB>m, n</SB>integration circuits 12<SB>m</SB>, and CDS circuits 13<SB>m</SB>. Each of the integration circuits 12<SB>m</SB>, stores electric charges input from the photodiodes PD<SB>m, n</SB>via the SW<SB>m, n</SB>and wires L<SB>m</SB>to capacitive elements C<SB>f</SB>and outputs a voltage in response to the stored electric charge amount. Each of the CDS circuits 13<SB>m</SB>uses a voltage output from the integration circuits 12<SB>m</SB>, for a reference voltage at a reference time when clamp switches SW<SB>3</SB>are opened and outputs a voltage in response to a difference between the reference voltage and the voltage output from the integration circuits 12<SB>m</SB>after the reference time. Let a capacitance of the wires L<SB>m</SB>be C<SB>w</SB>, a capacitance of the capacitive elements C<SB>f</SB>be C<SB>f</SB>, a gain band product of amplifiers A<SB>2</SB>included in the integration circuits 12<SB>m</SB>be GBW, then a time T until the reference time from a time when switches SW<SB>2</SB>are opened and the integration circuits 12<SB>m</SB>reach an electric charge storable state is expressed more than the prescribed value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a light detection device that outputs a voltage value corresponding to an incident light intensity.

  The photodetecting device includes a photodiode that generates an amount of charge corresponding to the incident light intensity, and an integration circuit that accumulates the charge generated by the photodiode and outputs a voltage value corresponding to the amount of accumulated charge. ing. In addition, the photodetection device uses CDS (Correlated Double Sampling, correlated double sampling) in order to remove offset error and switching noise (hereinafter referred to as “offset error”) included in the output voltage value of the integration circuit. A sampling circuit may be further provided (see, for example, Patent Document 1). The CDS circuit uses a voltage value output from the integration circuit at the reference time as a reference voltage value, and outputs a voltage value corresponding to a difference between the voltage value output from the integration circuit and the reference voltage value after the reference time. .

  In addition, the photodetection device can capture a one-dimensional image or a two-dimensional image when a plurality of photodiodes are arranged in a one-dimensional shape or a two-dimensional shape. In such a photodetection device, one set of integration circuit and CDS circuit may be provided for one photodiode, but in this case, the entire circuit scale becomes large. Therefore, in order to reduce the overall circuit scale, it is desirable to provide a set of integration circuits and CDS circuits for a plurality of photodiodes.

For example, when M × N photodiodes are two-dimensionally arranged in M rows and N columns, a set of integration circuits and CDS circuits are provided for the N photodiodes in each row. That is, a total of M sets of integration circuits and CDS circuits are provided. For each row, each of the N photodiodes is sequentially connected to the integrating circuit, and a voltage value corresponding to the intensity of incident light to each of the N photodiodes is sequentially output from the CDS circuit.
JP-A-8-331459

  However, although the above-described photodetection device includes a CDS circuit that removes an offset error or the like included in the output voltage value of the integration circuit, the removal of the offset error or the like may be insufficient. there were.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a photodetector that can sufficiently eliminate an offset error or the like.

The photodetecting device according to the present invention includes (1) a photodiode that generates an amount of electric charge according to incident light intensity, and (2) a photodiode that is provided between the photodiode and the wiring and is closed. A switch that outputs the charge generated in the wiring to the wiring, (3) an amplifier whose input terminal is connected to the wiring, and a capacitive element and a reset switch provided in parallel between the input terminal and the output terminal of the amplifier When the reset switch is open, the charge generated by the photodiode and input through the switch and the wiring is accumulated in the capacitor element, and the voltage value corresponding to the amount of the charge accumulated in the capacitor element is (4) The voltage value output from the integration circuit at the reference time is set as the reference voltage value, and the signal value corresponding to the difference between the voltage value output from the integration circuit and the reference voltage value after the reference time CD that outputs A circuit, characterized in that it comprises, and (5) the switch, the control unit for controlling an integrating circuit and CDS circuit each operation. Furthermore, the control unit included in the optical detection apparatus according to the present invention, the capacitance value of the wiring and C _w, the capacitance of the capacitor and C _f, the gain band product of the amplifier and GBW, reset switch is opened Control is performed so that the relational expression of the following equation (1) is established between these parameters, where T is the time from the time when the integration circuit becomes charge accumulable to the reference time.

  In this photodetection device, the integrating circuit is configured such that when the reset switch is closed, the capacitive element is discharged and the output voltage value is initialized, and then the reset switch is opened to store the input charge in the capacitive element. The charge can be accumulated. If the switch provided with the photodiode is closed while the reset switch is open, the charge generated in the photodiode and accumulated in the junction capacitor is input to the integration circuit via the switch and wiring. Then, the voltage is stored in the capacitive element of the integrating circuit, and a voltage value corresponding to the amount of charge stored in the capacitive element is output from the integrating circuit to the CDS circuit. In the CDS circuit, the voltage value output from the integration circuit at the reference time is set as the reference voltage value, and after this reference time, the signal value corresponding to the difference between the voltage value output from the integration circuit and the reference voltage value. Is output from the CDS circuit. At this time, the control unit performs control so that the relational expression (1) is satisfied, whereby the offset error included in the output voltage value of the integration circuit is sufficiently removed by the CDS circuit, and the offset is obtained. A signal value from which an error or the like has been removed can be output from the CDS circuit.

  In the photodetector according to the present invention, it is preferable that one set of integration circuits and CDS circuits are provided for a plurality of sets of photodiodes and switches. In this case, the plurality of photodiodes are sequentially connected to the integration circuit by sequentially closing the plurality of switches. Each photodiode has a period to be connected to the integration circuit at a constant cycle, and the charges generated between the previous connection period and the current connection period and accumulated in the junction capacitance portion of the photodiode are switches and wirings. Is input to the integration circuit. This photodetection device is a one-dimensional image or two-dimensional image in which an offset error is removed and an S / N ratio is excellent by performing control such that the relational expression (1) is satisfied by the control unit. And the entire circuit scale can be reduced.

The light detection method according to the present invention includes (1) a photodiode that generates an amount of electric charge according to incident light intensity, and (2) a photodiode that is provided between the photodiode and a wiring and is closed. A switch that outputs the charge generated in the wiring to the wiring, (3) an amplifier whose input terminal is connected to the wiring, and a capacitive element and a reset switch provided in parallel between the input terminal and the output terminal of the amplifier When the reset switch is open, the charge generated by the photodiode and input through the switch and the wiring is accumulated in the capacitor element, and the voltage value corresponding to the amount of the charge accumulated in the capacitor element is (4) The voltage value output from the integration circuit at the reference time is set as the reference voltage value, and the signal value corresponding to the difference between the voltage value output from the integration circuit and the reference voltage value after the reference time CD that outputs A method for the light detected by the light detecting device comprising: a circuit. Then, the light detection method according to the present invention, the capacitance value of the wiring and C _w, the capacitance of the capacitor and C _f, the gain band product of the amplifier and GBW, integrating circuit charge storage reset switch is opened It is characterized in that light detection is performed by performing control so that the relational expression (1) is established between these parameters, where T is the time from the time when it becomes possible to the reference time.

  According to the present invention, offset errors and the like can be sufficiently removed.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
First, a first embodiment of a light detection apparatus and a light detection method according to the present invention will be described. FIG. 1 is a configuration diagram of a photodetecting device 1 according to the first embodiment. The photodetection device 1 shown in this figure is capable of capturing a two-dimensional image, and includes a photodetection unit 11, M integration circuits 12 _{1 to} 12 _M , and M CDS circuits 13 _{1 to} 13. _M , M holding circuits 14 _{1 to} 14 _M , an AD conversion circuit 15, and a control unit 19 are provided. Here, each of M and N is an integer of 2 or more. Moreover, m appearing below is an arbitrary integer from 1 to M, and n is an arbitrary integer from 1 to N. The M integration circuits 12 _{1 to} 12 _M have a common configuration. The M CDS circuits 13 _{1 to} 13 _M have a common configuration. The M holding circuits 14 _{1 to} 14 _M have a common configuration.

The light detection unit 11 includes M × N photodiodes PD _{1,1 to} PDM _{, N} and M × N switches SW _{1,1 to} SW _{M, N,} and includes the photodiode PD _{m, n} and the switch SW. These are two-dimensionally arranged in M rows and N columns with _{m and n} as a set. Each photodiode PD _{m, n} is located in the m-th row and the n-th column. Each photodiode PD _{m, n} generates an amount of electric charge according to the incident light intensity, and is connected to the wiring L _m via the switch SW _{m, n} .

Each integrating circuit 12 _m is connected to the input terminal to the wiring L _m, and accumulates charges input through the wiring L _m, and outputs a voltage value corresponding to the accumulated charge amount to the CDS circuit 13 _m . Each CDS circuit 13 _m uses the voltage value output from the integration circuit 12 _{m at} the reference time as a reference voltage value, and after this reference time, it corresponds to the difference between the voltage value output from the integration circuit 12 _m and the reference voltage value. The obtained voltage value is output to the holding circuit 14 _m . Each holding circuit 14 _m holds the voltage value output from the CDS circuit 13 _{m at} a predetermined time, and outputs the held voltage value to the AD conversion circuit 15.

The AD conversion circuit 15 receives a voltage value sequentially output from each of the _M holding circuits 14 _{1 to} 14 _M , converts the voltage value (analog value) into a digital value, and outputs the digital value. . The control unit 19 includes M × N switches SW _{1,1 to} SW _{M, N} , M integration circuits 12 _{1 to} 12 _M , M CDS circuits 13 _{1 to} 13 _M , which are included in the light detection unit 11. Each of the M holding circuits 14 _{1 to} 14 _M and the AD conversion circuit 15 is controlled.

FIG. 2 is a circuit diagram of the photodiode PD _{m, n} , the switch SW _{m, n} , the integrating circuit 12 _m, and the CDS circuit 13 _m included in the photodetector 1 according to the first embodiment. Incidentally, in this figure, the M × N photodiodes included in the photodetecting section 11 PD _1,1 ~PD _{M, N} and the M × N switches SW _{1, 1} to SW _M, of _N, the A photodiode PD _{m, n} and a switch SW _{m, n} located in m rows and n columns are shown as representatives.

Each integrating circuit 12 _m includes an amplifier A ₂ , a capacitive element C _f and a reset switch SW ₂ . The non-inverting input terminal of the amplifier A ₂ is the predetermined voltage value is input, an inverting input terminal of the amplifier A ₂ is connected to the wiring L _m. The capacitor C _f and the reset switch SW ₂ are connected in parallel to each other, it is provided between the inverting input terminal of the amplifier A ₂ and the output terminal. When the reset switch SW ₂ is open, the integrating circuit 12 _m accumulates the electric charge generated by the photodiode PD _{m, n} and input through the switch SW _{m, n} and the wiring L _m in the capacitive element C _f , A voltage value corresponding to the amount of charge accumulated in the element _Cf is output. On the other hand, in the integrating circuit 12 _m , when the reset switch SW ₂ is closed, the capacitive element C _f is discharged, and the output voltage value is initialized.

Each CDS circuit 13 _m includes an amplifier A ₃ , a feedback capacitive element C ₃₁ , a coupling capacitive element C _32, and a clamp switch SW ₃ . The non-inverting input terminal of the amplifier A ₃ is the predetermined voltage value is input, an inverting input terminal of the amplifier A ₃ is connected to an output terminal of the integrating circuit 12 _m via a coupling capacitive element C _32. Further, the feedback capacitor C ₃₁ and the clamp switch SW ₃ is connected in parallel to each other, it is provided between the inverting input terminal of the amplifier A ₃ and the output terminal. The CDS circuit 13 _m uses the voltage value output from the integration circuit 12 _{m at the} time (reference time) when the clamp switch SW ₃ is opened as the reference voltage value, and the voltage value output from the integration circuit 12 _m after this reference time. Is stored in the feedback capacitive element C ₃₁ , so that a voltage value corresponding to the difference between the voltage value output from the integrating circuit 12 _m and the reference voltage value is output to the holding circuit 14 _m . To do.

Here, the capacitance value of the wiring L _m between the switch SW _{m, n} and the integration circuit 12 _m is represented as C _w , the capacitance value of the capacitive element C _f included in the integration circuit 12 _m is represented as C _f, and the integration circuit The gain band product of the amplifier A ₂ included in 12 _m is GBW. The transconductance of the input transistors of the amplifier A ₂ included in the integrating circuit 12 _m and g _m, the internal phase compensation capacitance value of the amplifier A ₂ and C _c. Also, the time from the time when the reset switch SW ₂ included in the integrating circuit 12 _m is opened and the integrating circuit 12 _m is in a charge accumulating state to the reference time when the clamping switch SW ₃ included in the CDS circuit 13 _m is opened. Let T be T. At this time, in the first embodiment, the control unit 19 performs control so that the following relational expression (2) is established between these parameters.

Next, the operation of the photodetecting device 1 according to the first embodiment will be described. The operation described below is performed under the control of the control unit 19. FIG. 3 is a timing chart for explaining the operation of the photodetector 1 according to the first embodiment. In this figure, as operations of the first embodiment, (a) opening and closing of the reset switch SW ₂ included in the integrating circuit 12 _m , (b) opening and closing of the clamp switch SW ₃ included in the CDS circuit 13 _m , ( c) Open / close of a switch SW _{m, n} provided corresponding to the photodiode PD _{m, n} , (d) an output voltage value from the integrating circuit 12 _m , and (e) an output voltage from the CDS circuit 13 _m Value. As operations of the comparative example (when the relational expression (2) is not satisfied), (f) opening / closing of the clamp switch SW ₃ included in the CDS circuit 13 _m , (g) output from the integration circuit 12 _m The voltage value and (h) the output voltage value from the CDS circuit 13 _m are shown.

In the first embodiment, the operation is performed as shown in FIGS. That is, the period from time _{t 11} to time _{t 12,} and the reset switch SW ₂ included in the integrating circuit 12 _m is closed, the capacitor _{C f} is discharged, initializing the output voltage value from the integrating circuit 12 _m Is done. Period from time _{t 11} to time _{t 14,} are closed clamp switch SW ₃ included in the CDS circuit 13 _m, the feedback capacitor _{C 31} is discharged, the output voltage value from the CDS circuit 13 _m is initialized The Further, the switch SW _{m, n} is closed for a certain period from the time t _{15 ,} and the charge generated in the photodiode PD _{m, n} and accumulated in the junction capacitance portion of the photodiode PD _{m, n} is changed to the switch SW _{m, n. The} signal is input to the integrating circuit 12 _m via _n and the wiring L _m .

Here, the context of each time is “t ₁₁ <t ₁₂ <t ₁₄ <t ₁₅ ”. Time integrating circuit 12 _m becomes a charge accumulable state is time _{t 12} to open the reset switch SW _2. The reference time for the CDS circuit 13 _m to take in the reference voltage value is the time t ₁₄ when the clamp switch SW ₃ is opened. In the first embodiment, a time T (= t ₁₄ −t ₁₂ ) from time t ₁₂ to time t ₁₄ satisfies the relational expression (2).

During the period from time t ₁₂ to time t ₁₅ , the integration circuit 12 _m is in a charge accumulating state because the reset switch SW ₂ is open, but the switch SW _{m, n} is open, so that the photodiode PD _No charge is input from _{m and n,} and no charge is accumulated in the capacitive element _Cf. However, the output voltage value from the integrating circuit 12 _m, after the time t ₁₂ will change monotonically, eventually the time t ₁₄ substantially constant voltage value before a certain time (i.e., an offset voltage value) reached. The time for the output voltage value from the integrating circuit _12m to reach the offset voltage value is represented by the right side of the above equation (2a).

When the time _{t 14} to open the clamp switch SW _3, the offset voltage value that is output from the integrating circuit 12 _m at that time _{t 14} (the reference time) is taken up by the CDS circuit 13 _m as a reference voltage value. Then, the reference time _{t 14} after the charge in an amount corresponding to the variation of the voltage value output from the integrating circuit 12 _m is accumulated in the feedback capacitor _{C 31} of the CDS circuit 13 _m, is output from the integrating circuit 12 _m that a voltage value corresponding to the difference between the voltage value and the reference voltage value is output from the CDS circuit 13 _m.

Time _{t 15} to the switch SW _m, when _n is closed, the photodiode PD _m, generated the photodiode PD _m by _n, charges accumulated in the junction capacitance portion of the _n, the switch SW _{m, n} and the wiring _{L m} enter to the integrating circuit 12 _m via is accumulated in the capacitor _{C f} of the integrating circuit 12 _m. Then, the voltage value output from the integrating circuit 12 _m becomes one in which the signal voltage value and the offset voltage value corresponding to the amount of charge stored in the capacitor C _f is superimposed. Further, the voltage value outputted from the CDS circuit 13 _m includes as the signal voltage output from the integrating circuit 12 _m and the offset voltage value is superimposed, is output to the reference time t ₁₄ from the integrating circuit 12 _m captured offset voltage value to the CDS circuit 13 _m (reference voltage value), and those corresponding to the difference between the. Therefore, the voltage value output from the CDS circuit 13 _m is obtained by removing the offset error and the like.

The voltage value output from the CDS circuit 13 _{m at} a certain time after the time t ₁₅ is held by the holding circuit 14 _m . The voltage values held in each of the _M holding circuits 14 _{1 to} 14 _M are sequentially output to the AD conversion circuit 15 and are AD-converted by the AD conversion circuit 15.

When the parallel processing for the _M photodiodes PD _{1, n to} PDM _{, n in} the n-th column is completed as described above, the M photodiodes PD _{1, n + 1 to} PDM _{, n in} the next column are completed _. The parallel processing for _{n + 1} is similarly performed. In this way, the processing for the _M photodiodes PD _{1, n to} PD _{M, n} in each column is repeatedly performed.

As for the m-th row, N photodiodes PD _{m, 1 to} PD _{m, N} are sequentially connected to the integrating circuit 12 _m by sequentially closing _N switches SW _{m, 1 to} SW _{m, N.} Is done. Each photodiode PD _{m, n} has a period in which it is connected to the integrating circuit 12 _m at a constant cycle, and is generated between the previous connection period and the current connection period _{, and} the junction capacitance part of the photodiode PD _{m, n} The charge stored in is input to the integrating circuit 12 _m via the switch SW _{m, n} and the wiring L _m .

  Therefore, this photodetection device 1 is a one-dimensional image in which the offset error and the like are removed and the S / N ratio is excellent by performing control such that the relational expression (2) is satisfied by the control unit 19. Alternatively, a two-dimensional image can be taken and the overall circuit scale can be reduced.

On the other hand, in the comparative example (when the relational expression (2) is not satisfied), the operation is performed as shown in FIGS. That is, unlike the first embodiment, the operation in the case of the comparative example, the time _{t 13} before time _{t 14} and a later than time _{t 12,} the switch SW clamp included in the CDS circuit 13 _{m 3} opens. From the time _{t 12} to the integrating circuit 12 _m reset switch SW ₂ is opened is a charge accumulable state, to the reference time _{t 13} to the CDS circuit 13 _m is opened clamp switch SW ₃ captures a reference voltage value, in between The time T ₁ (= t ₁₃ −t ₁₂ ) does not satisfy the relational expression (2).

In the comparative example, the voltage value output from the integrating circuit 12 _m changes monotonously for a while after the reference time t ₁₃ when the clamp switch SW ₃ is opened and the CDS circuit 13 _m takes in the reference voltage value. Eventually, a certain voltage value (that is, an offset voltage value) is reached at a certain time. That is, the reference voltage value taken into the CDS circuit 13 _m on the reference time t _13, rather than the offset voltage value, and that the remaining offset voltage value from the offset voltage value is subtracted. Further, variation in the output voltage value from the integrating circuit 12 _m of the reference time t ₁₃ later, and a signal voltage value and the residual offset voltage value corresponding to the amount of charge stored in the capacitor C _f is superimposed It will be a thing. Therefore, the voltage value outputted from the CDS circuit 13 _m to the switch SW _{m, n} are closed time t ₁₅ later, be one that is a signal voltage value remaining offset voltage value corresponding to those superposed, offset removal Etc. are incomplete.

As can be seen by comparison with comparative examples, in the first embodiment, from the time t ₁₂ to the reset switch SW ₂ is open the integrating circuit 12 _m becomes a charge accumulable state included in the integrating circuit 12 _m, CDS circuit 13 the time T to the reference time t ₁₄ to open the clamp switch SW ₃ included in the _m is, by satisfying the above expression (2) equation, the voltage output from the CDS circuit 13 _m, the offset error or the like Is sufficiently removed.

(Second Embodiment)
Next, a second embodiment of the light detection device and the light detection method according to the present invention will be described. FIG. 4 is a circuit diagram of the photodetecting device 2 according to the second embodiment. The photodetection device 2 shown in this figure includes a photodiode PD, a switch SW, an integration circuit 22, a CDS circuit 23, an AD conversion circuit 27, and a control unit 29. What is the switch SW and the input terminal of the integration circuit 22? They are connected by wiring L. The configurations of the photodiode PD, the switch SW, and the integrating circuit 22 are the same as those in the first embodiment. The CDS circuit 23 includes a first holding circuit 24 ₁ , a second holding circuit 24 ₂ , a first voltage follower circuit 25 ₁ , a second voltage follower circuit 25 ₂ , a differential conversion circuit 26, a switch SW ₈₁ and a switch SW ₈₂ . .

The first holding circuit 24 ₁ and the second holding circuit 24 ₂ have a common configuration. The first holding circuit 24 ₁ and the second holding circuit 24 ₂ each input terminal is connected to the output terminal of the integrating circuit 22. The first holding circuit 24 ₁ includes an amplifier A ₄ , a capacitive element C _4, and switches SW _{40 to} SW ₄₂ . The non-inverting input terminal of the amplifier A ₄ is the predetermined voltage value is inputted. Inverting input terminal of the amplifier A ₄ is connected to the capacitor C _4, also connected to the output terminal of the integrating circuit 22 via the capacitance element C ₄ and the switch SW _40. The switch SW ₄₁ is provided between the inverting input terminal and the output terminal of the amplifier A ₄ . The switch SW ₄₂ is provided between the connection point between the capacitive element C ₄ and the switch SW ₄₀ and the output terminal of the amplifier A ₄ . The same applies to the configuration of the second holding circuit 24 _2.

The first holding circuit 24 _1, when the switch SW ₄₀ turns from the closed state to the open state, holds the voltage value output from the integrating circuit 22 at that time, then, the open state the switch SW ₄₁ from the closed state Further, the switch SW ₄₂ is changed from the open state to the closed state, and thereafter, the held voltage value is output. The same applies to the operation of the second holding circuit 24 _2. However, the first holding circuit 24 ₁ and the second holding circuit 24 ₂ operates at different timings. That is, the first holding circuit 24 _1, to hold the offset voltage output from the integrating circuit 22, the switch _SW 40 _{to SW 42} are opened and closed. The second holding circuit 24 _2, to hold a signal voltage value offset voltage value is superimposed is output from the integrating circuit 22, the switch _SW 40 _{to SW 42} are opened and closed.

The first voltage follower circuit 25 ₁ and the second voltage follower circuit 25 ₂ have a common configuration. The first voltage follower circuit 25 of _the input terminal is connected to the first holding circuit 24 ₁ of the output terminal via a switch _{SW 81,} the second voltage follower circuit 25 and _second input terminals and the second held via the switch _{SW 82} It is connected to an output terminal of the circuit 24 _2. The first voltage follower circuit 25 ₁ has a non-inverting input terminal of the amplifier is connected to the switch SW _81, an inverting input terminal and the output terminal of the amplifier being connected directly to one another, a high input impedance and low output impedance Ideally, the amplifier circuit has an amplification factor of 1. The same applies to the second voltage follower circuit 25 _2.

The differential conversion circuit 26 includes an amplifier and four resistors R _{1 to} R ₄ . The amplifier has a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal, and an inverting output terminal. The non-inverting input terminal of the amplifier, through the resistor R ₁ is connected to a first voltage follower circuit 25 _first output terminal, via a resistor R ₂ is connected to the inverted output terminal of the amplifier. The inverting input terminal of the amplifier, through the resistor R ₃ is connected to the second voltage follower circuit 25 _{and second} output terminal is connected to the non-inverting output terminal of the amplifier via a resistor R _4. The differential conversion circuit 26, a voltage value output from the first voltage follower circuit 25 ₁ and the second voltage follower circuit 25 ₂ are inputted, a differential voltage value corresponding to the difference between these two input voltage values Output as a signal. The AD conversion circuit 27 receives the voltage value output from the differential conversion circuit 26, converts the voltage value (analog value) into a digital value, and outputs the digital value.

The control unit 29 includes a switch SW provided together with the photodiode PD, a reset switch SW ₂ included in the integration circuit 22, switches SW _{40 to} SW ₄₂ included in the holding circuits 24 ₁ and 24 ₂ , an AD conversion circuit 27, and a switch The operation of each of SW ₈₁ and SW ₈₂ is controlled. Also in the second embodiment, the capacitance value of the wiring L and C _w, the capacitance of the capacitor C _f included in the integrating circuit 22 represents a C _f, the gain band product of the amplifier A ₂ included in the integrating circuit 22 Is the GBW, the transconductance of the input transistor of the amplifier A ₂ is g _m , the internal phase compensation capacitance value of the amplifier A ₂ is C _c , the reset switch SW ₂ is opened, and the integration circuit 22 is in a state capable of storing charges. When the time from the time to the reference time is T, the control unit 29 performs control so that the relational expression (2) is satisfied. However, this second embodiment, reference time CDS circuit 23 takes in the reference voltage value, the switch SW ₄₀ is the time to turn from a closed state to an open state in the first holding circuit 24 _1.

In the second embodiment, CDS circuit 23 holds the first holding circuit 24 ₁ the offset voltage value output from the integrating circuit 22, the signal offset voltage value output from the integrating circuit 22 is superimposed by holding the voltage value by the second holding circuit 24 _2, the difference between the voltage values held by the first holding circuit 24 ₁ and the second holding circuit 24 _2, respectively (i.e., signal voltage value offset error is removed) Can be output from the differential conversion circuit 26 as a differential signal. Further, the AD conversion circuit 27 can convert the signal voltage value as a differential signal output from the differential conversion circuit 26 into a digital value and output the digital value.

  One set of integration circuit 22 and CDS circuit 23 may be provided for one set of photodiode PD and switch SW, or a plurality of sets of photodiodes PD and switches may be provided as in the first embodiment. One set of integrating circuit 22 and CDS circuit 23 may be provided for SW. Further, one CDS circuit 23 may be provided for one integration circuit 22, or one CDS circuit 23 may be provided for a plurality of integration circuits 22. In the latter case, a switch is provided at the subsequent stage of each integration circuit 22, and the voltage value output from each integration circuit 22 is sequentially input to the CDS circuit 23 by this switch.

Also in the CDS circuit 23, a set of voltage follower circuits 25 ₁ and 25 ₂ , a differential conversion circuit 26, and an AD conversion circuit 27 may be provided for the set of holding circuits 24 ₁ and 24 ₂ . In addition, one set of voltage follower circuits 25 ₁ and 25 ₂ , a differential conversion circuit 26 and an AD conversion circuit 27 may be provided for the plurality of sets of holding circuits 24 ₁ and 24 ₂ . In the former case, the switches SW ₈₁ and SW ₈₂ are unnecessary (or are always closed). In the latter case, the switch _SW 81, _{SW 82,} which is provided downstream of each pair of the holding circuit ₂₄ 1, 24 _2, each pair of holding circuits ₂₄ 1, 24 voltage values output from ₂ is sequentially Voltage It is input to the follower circuits 25 ₁ and 25 ₂ .

Next, the operation of the photodetecting device 2 according to the second embodiment will be described. The operation described below is performed under the control of the control unit 29. FIG. 5 is a timing chart for explaining the operation of the photodetecting device 2 according to the second embodiment. The photodiode PD, the switch SW, the integrating circuit 22, the holding circuits 24 ₁ and 24 ₂ , the voltage follower circuits 25 ₁ and 25 ₂ , the differential conversion circuit 26 and the AD conversion circuit 27 are provided one by one. Assuming that the switches SW ₈₁ and SW ₈₂ are always closed, the operation of the photodetector 2 will be described.

The FIG, (a) opening and closing of the reset switch SW ₂ included in the integrating circuit 22, (b1) ~ (b3 ) switch _SW 40 _{to SW 42} of each opening included in the first holding circuit 24 _1, (c1 ) ~ (c3) second holding circuit 24 ₂ to the switch _SW 40 _{to SW 42} of each opening and closing contained, opening and closing of the switches SW provided with (d) a photodiode PD, and, from (e) integrating circuit 22 The output voltage value is shown.

Period from time t ₂₁ to time t _22, though the reset switch SW ₂ is closed to be included in the integrating circuit 22, the capacitor C _f is discharged, the output voltage value from the integrating circuit 22 is initialized. In the first holding circuit 24 _1, the switch _{SW 40} is closed at time _{t 21,} the switch _{SW 41} is closed after _the time _{t 21,} the switch _{SW 40} is opened at time _{t 23,} the switch _{SW 41} is opened after _the time _{t 23,} the time t ₂₄ switch _{SW 42} is closed, the switch _{SW 42} is opened at a time _{t 27.} In the second holding circuit 24 _2, switch _{SW 40} is closed at time _{t 21,} the switch _{SW 41} is closed after _the time _{t 21,} the switch _{SW 40} is opened at time _{t 25,} the switch _{SW 41} is opened after _the time _{t 25,} the time t switch _{SW 42} is closed to _26, the switch _{SW 42} is opened at a time _{t 27.} In addition, the switch SW is closed for a certain period from time t ₂₄ , and the charge generated in the photodiode PD and accumulated in the junction capacitance portion of the photodiode PD is input to the integration circuit 22 via the switch SW and the wiring L. The

Here, the context of each time is “t ₂₁ <t ₂₂ <t ₂₃ <t ₂₄ <t ₂₅ <t ₂₆ <t ₂₇ ”. Time integrating circuit 22 becomes a charge accumulable state is time t ₂₂ to open the reset switch SW _2. Reference time CDS circuit 23 takes in the reference voltage value is the time _{t 23} the switch _{SW 40} included in the first holding circuit 24 ₁ is opened. In the second embodiment, the time T (= t ₂₃ −t ₂₂ ) from the time t ₂₂ to the time t ₂₃ satisfies the relational expression (2).

Period from time t ₂₂ to time t _24, the integrating circuit 22, but has a charge accumulable state because the reset switch SW ₂ is open, electric charge from the photodiode PD because the switch SW is open input No charge is accumulated in the capacitive element _Cf. However, the output voltage value from the integrating circuit 22 will monotonously changes after time t _22, reaches a substantially constant voltage value (i.e., an offset voltage value) to eventually time t ₂₃ before a certain time. The time for the output voltage value from the integrating circuit 22 to reach the offset voltage value is represented by the right side of the above equation (2a).

In the first holding circuit 24 _1, the switch _{SW 40} is opened at time _{t 23,} the switch _{SW 41} is opened after the time _{t 23,} the switch _{SW 42} is closed at time _{t 24,} the output voltage value of the integrating circuit 22 at time _{t 23} A voltage value (reference voltage value) corresponding to the first holding circuit 24 _{1 is} held by the first holding circuit 24 ₁ , and the held voltage value is output from the first holding circuit 24 ₁ after time t ₂₄ . This output voltage value represents the offset voltage value output from the integration circuit 22.

The switch SW is closed for a certain period from time t ₂₄ , and the charge generated in the photodiode PD and accumulated in the junction capacitance portion of the photodiode PD is input to the integration circuit 22 via the switch SW and the wiring L, Accumulated in the capacitive element C _f of the integrating circuit 22. Then, the voltage value output from the integrating circuit 22 becomes the signal voltage value and the offset voltage value corresponding to the amount of charge stored in the capacitor C _f is superimposed.

In the second holding circuit 24 _2, at time _{t 25} to open the switch _{SW 40} is open switch _{SW 41} after time _{t 25,} when the time _{t 26} the switch _{SW 42} is closed, the output voltage value of the integrating circuit 22 at time _{t 25} voltage value corresponding to the held by the second holding circuit 24 _2, the time t ₂₆ after the voltage value that is held is outputted from the second holding circuit 24 _2. This output voltage value represents a signal voltage value on which the offset voltage value output from the integration circuit 22 is superimposed.

The voltage value output from the first holding circuit 24 ₁ during the period from the time t ₂₆ to the time t ₂₇ when both the switches SW _{42 of} the first holding circuit 24 ₁ and the second holding circuit 24 ₂ are both closed is: the first through the voltage follower circuit 25 ₁ is input to the differential conversion circuit 26, and a voltage value output from the second holding circuit 24 ₂ is input to the differential conversion circuit 26 via the second voltage follower circuit 25 ₂ Is done. In the differential conversion circuit 26, a voltage value corresponding to the difference between these two input voltage values is output as a differential signal. This output voltage value represents a signal voltage value from which an offset error or the like has been removed. Further, the voltage value output from the differential conversion circuit 26 is converted into a digital value by the AD conversion circuit 27, and the digital value is output.

In the second embodiment, from the time _{t 22} the reset switch SW ₂ is the integrating circuit 22 is opened is a charge accumulable state included in the integrating circuit 22, the first holding circuit 24 ₁ of the switch SW included in the CDS circuit 23 time T to the reference time t _{23 to 40} open, by satisfying the above expression (2) equation, the voltage output from the CDS circuit 23 becomes offset error has been sufficiently removed.

(Modification)
The present invention is not limited to the above embodiment, and various modifications can be made. For example, the integrating circuit in each embodiment may have a capacitance portion with a variable capacitance value instead of a capacitance element with a fixed capacitance value. By doing so, the dynamic range of light detection can be obtained. Can be increased. In this case, the time T may be set so that the above equation (2) is established with respect to the minimum capacitance value C _f of the variable capacitance section, and for each capacitance value C _f of the variable capacitance section. The time T may be adjusted so that the above equation (2) holds.

  In addition, the specific configuration of the CDS circuit is not limited to that described in the above embodiment, and various configurations are possible. Regardless of the configuration of the CDS circuit, the time T from the time when the integration circuit is in a charge accumulation state to the reference time at which the CDS circuit takes in the reference voltage value satisfies the above equation (2). You can do it.

It is a lineblock diagram of photodetection device 1 concerning a 1st embodiment. FIG. 3 is a circuit diagram of a photodiode PD _{m, n} , a switch SW _{m, n} , an integration circuit 12 _m, and a CDS circuit 13 _m included in the photodetector 1 according to the first embodiment. It is a timing chart explaining operation | movement of the photon detection apparatus 1 which concerns on 1st Embodiment. It is a circuit diagram of the photon detection apparatus 2 which concerns on 2nd Embodiment. It is a timing chart explaining operation | movement of the photon detection apparatus 2 which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 2 ... Photodetection device, 11 ... Photodetection part, 12 ... Integration circuit, 13 ... CDS circuit, 14 ... Holding circuit, 15 ... AD conversion circuit, 19 ... Control part, 22 ... Integration circuit, 23 ... CDS circuit, 24 ... Holding circuit, 25 ... Voltage follower circuit, 26 ... Differential conversion circuit, 27 ... AD conversion circuit, 29 ... Control unit, A ... Amplifier, C ... Capacitance element, L ... Wiring, PD ... Photodiode, R ... Resistance Switch, SW ... switch.

Claims (3)

A photodiode that generates an amount of charge according to the incident light intensity;
A switch that is provided between the photodiode and the wiring and outputs a charge generated in the photodiode to the wiring when the photodiode is closed;
An amplifier having an input terminal connected to the wiring, and a capacitor and a reset switch provided in parallel between the input terminal and the output terminal of the amplifier, and the reset switch is open An integration circuit that accumulates charges generated in the photodiode and input through the switch and the wiring in the capacitive element, and outputs a voltage value corresponding to the amount of charge accumulated in the capacitive element;
A CDS circuit that uses a voltage value output from the integration circuit at a reference time as a reference voltage value, and outputs a signal value corresponding to a difference between the voltage value output from the integration circuit and the reference voltage value after the reference time When,
A control unit that controls operations of the switch, the integrating circuit, and the CDS circuit;
With
Wherein the control unit, the capacitance value of the wiring and C _w, the capacitance value of the capacitor and C _f, the gain band product of the amplifier and GBW, the integrating circuit can charge accumulating the reset switch is opened When the time from the time when the state is reached to the reference time is T,

Control so that the following relational expression holds:
An optical detection device characterized by that.   2. The photodetecting device according to claim 1, wherein one set of the integrating circuit and the CDS circuit is provided for a plurality of sets of the photodiodes and the switches. A photodiode that generates an amount of charge according to the incident light intensity;
A switch that is provided between the photodiode and the wiring and outputs a charge generated in the photodiode to the wiring when the photodiode is closed;
An amplifier having an input terminal connected to the wiring, and a capacitor and a reset switch provided in parallel between the input terminal and the output terminal of the amplifier, and the reset switch is open An integration circuit that accumulates charges generated in the photodiode and input through the switch and the wiring in the capacitive element, and outputs a voltage value corresponding to the amount of charge accumulated in the capacitive element;
A CDS circuit that uses a voltage value output from the integration circuit at a reference time as a reference voltage value, and outputs a signal value corresponding to a difference between the voltage value output from the integration circuit and the reference voltage value after the reference time When,
A method of performing photodetection using a photodetection device comprising:
The capacitance value of the wiring and C _w, from the capacitance value of the capacitor and C _f, the gain band product of the amplifier and GBW, time the integrating circuit the reset switch is opened is a charge accumulable state When the time until the reference time is T, between these parameters

The light is detected by performing control so that the following relational expression holds:
An optical detection method characterized by the above.

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