JPH06189199A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide a wide dynamic range for following up even a bright object by supressing noise generated at amplifying elements in an amplifying type solid-state image pickup device using picture elements provided with the amplifying elements. CONSTITUTION:An unit picture element is constituted of a photodiode 1, an (n) type MOS transistor 2 whose gate is connected to the photodiode 1, a capacitive element 3 and the (n) type MOS transistor 5 for reset use connected between the drain of the transistor 2 and the photodiode 1, a (p) type MOS transistor 4 for load use connected to the drain of the transistor 2 and the capacitive element 8 for which the (n) type MOS transistor 9 for sample hold use is interposed. Then, the output voltage of a bias circuit 35 for setting a bias current is impressed to the gate of the transistor 4, a picture element bias current is controlled and the frequency band of the picture element is changed corresponding to the brightness of the object.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device such as a line sensor having a photodiode array composed of a plurality of pixels, and more particularly to an amplification type solid-state image pickup device having an amplification function for each pixel. The present invention relates to a solid-state imaging device capable of obtaining a high S / N while suppressing noise generation while having a wide dynamic range.

[0002]

2. Description of the Related Art Conventionally, as a solid-state image pickup device, a MOS
In addition to the solid-state imaging device of the type that transfers and reads out the photocharge itself generated in each pixel of CCD type, CCD type, etc., the amplification function is provided for each pixel, and the amplified output corresponding to the photocharge generated in each pixel An amplification type solid-state imaging device for reading out is known.

As an example of the structure of a pixel having this amplification function, the structure shown in FIG. 14 is disclosed in Japanese Patent Application No. 4-36922.
No. In FIG. 14, 1 is a photodiode, 2 is an n-type MOS transistor, the source is grounded, and the drain operates as a load and a current source.
By connecting the MOS transistor 4 of the type, a grounded source type amplifier circuit is configured. The photodiode 1 is connected to the input terminal of the source-grounded amplifier circuit, that is, the gate of the n-type MOS transistor 2, and the output terminal of the source-grounded amplifier circuit, that is, the drain of the n-type MOS transistor 2 to the input terminal (n (Type MOS transistor 2 gate) is connected to the capacitive element 3 for feedback, and the reset n-type MOS transistor 5 for setting the initial potential of the gate of the n-type MOS transistor 2 is connected in parallel with the capacitive element 3. To do. This structure is used as a pixel (basic cell), a sensor is formed when the pixels are arranged one-dimensionally or two-dimensionally, and each pixel is driven by a shift register pulse for selecting a readout pixel. The selection n-type MOS transistor 6 is provided, and when the n-type MOS transistor 6 is turned on, the drain voltage of the n-type MOS transistor 2 appears on the signal output line 7.

Next, the operation of the pixel thus constructed will be described. First, the reset pulse φ _R applied to the gate of the reset n-type MOS transistor 5 is set to “H”.
When the level is set, the charges accumulated in the capacitive element 3 are ejected and the reset state is set. After that, from the time when φ _R = “L” is switched, the photocharge generated in the photodiode 1 is accumulated in the capacitance element 3, and the n-type MOS transistor 2
Drain voltage rises according to the accumulated photocharge.
Then, this voltage is read from the signal output line 7 by turning on the selection n-type MOS transistor 6, and the pixel signal output is output from the output terminal V _OUT .

By the way, in a sensor having a pixel having an amplifying function having the above-mentioned structure, an n-type M for amplifying each pixel is used.
Due to the variation of the OS transistor 2, the offset voltage of each pixel varies and fixed pattern noise (FPN) occurs. In order to suppress this, as shown in FIG. 15, a configuration in which each pixel is provided with an FPN suppressing circuit is disclosed in Japanese Patent Application No. 4-3.
No. 6923.

In FIG. 15, S is a unit pixel having exactly the same configuration as the pixel shown in FIG. Then, the pixel output section, via the input capacitance element 11 (capacitance value C ₁ ), has the source-grounded p-type MOS transistor 16 and the n-type MOS transistor 19 operating as a source follower, and n operating as a load thereof. Of the p-type MOS transistor 16, that is, the gate of the p-type MOS transistor 16. In addition, a pulse φ _{T is applied} between the input node 25 and the output node 26 of the inverting amplifier circuit.
A feedback capacitance element 12 (capacitance value C ₂ ) is connected via a p-type MOS transistor 14 driven by. Further, the switching p-type MOS transistor 13 that applies the initial voltage to the input node 25 and performs the clamp operation of the input capacitance element 11,
It is provided between the input node 25 and the drain terminal of the p-type MOS transistor 16. Further, a p-type MOS transistor 15 for resetting the feedback capacitance element 12 and giving an initial voltage
_Are provided between the connection point of the capacitive element 12 and the p-type MOS transistor 14 and the reference voltage source V _ref . Then, the FPN is generated by the inverting amplifier circuit provided in the subsequent stage of the pixel S.
Is being measured.

Next, the operation of the pixel provided with the FPN suppressing circuit shown in FIG. 15 will be described based on the timing chart shown in FIG. First, in the period T ₁ , the pixel S and the suppression circuit are reset. After that, the reset n-type MOS transistor 5 is turned off, and the integration operation in the pixel is performed from the period T ₂ . After the start of this integration and after the potential V _P of the pixel output node 24 has settled down, the p-type MOS
The transistors 13 and 15 are turned off, the p-type MOS transistor 14 is turned on, and the feedback circuit formed by the capacitive element 12 in the suppression circuit and the switching p-type MOS transistor 14 is connected. In the period T ₃ , the integration operation of the pixel S is continued, and the rise of the potential V _P of the node 24 caused by the integration operation appears at the node 26 as the inverted output V _OUT . After the elapse of a certain integration time, a pulse from the shift register causes n
The MOS transistor 21 is turned on, and the inverted output V _OUT is transmitted to the signal output line 23.

In this operation, the reference voltage clamped to the input capacitance element 11 becomes the potential of the pixel output (V _P ) at the time when the period T ₂ switches to T ₃ . This period T ₂
With reference to the potential of V _P at the time of shifting from T to T ₃ , the signal component V _PS due to the optical integration increased from that is expressed as (V _ref −C ₁ / C ₂ · V _PS ) as a decrease from the reference voltage V _{ref. Is} transmitted to V _OUT of node 26 as a voltage value represented by. The potential is transmitted to the signal output line 23 by scanning the shift register and read.

[0009]

In the conventional pixel structure described above, the sensitivity is determined by the feedback capacitance element 3, so the capacitance value of the feedback capacitance element 3 can be reduced to increase the sensitivity, and as shown in FIG. With such a pixel configuration, the FPN can be further suppressed, the reset noise generated by the reset operation of the pixel S can be removed, and the C ₁ / C ₂ times amplification can be performed, and a high S / N can be expected.

However, in the above conventional pixel configuration,
The S / N is limited due to the following problems. That is, when the sensitivity is increased, the transistor noise of the n-type MOS transistor 2 is also amplified.

FIG. 17 shows an equivalent circuit in the integration operation in the pixel configuration shown in FIG. In FIG. 17, 28 is an amplifier circuit including an n-type MOS transistor 2 in the pixel,
Reference numeral 29 indicates an inverting amplifier circuit, and C ₀ , C ₁ , and C ₂ indicate capacitors corresponding to the respective capacitive elements 3, 11, 12 in FIG. Further, the capacitance C _d shown in parallel with the photodiode 1 is
The junction capacitance of the photodiode 1 is shown.

In this equivalent circuit, the pixel amplification circuit 28
The noise voltage e _n generated at the input section of is amplified as shown by the following equation (1) and generated at the output terminal V _OUT . _{V n = C d / C 0} · C 1 / C 2 · e n ····· (1)

Here, V _n represents the noise voltage at the output terminal V _OUT . As can be seen from this equation (1),
Increase the sensitivity, that is, decrease C ₀ to reduce C ₁ / C
Increasing ₂ also increases the noise voltage, and eventually the S / N is limited by the noise voltage generated at the input of this amplification stage.

To reduce the noise voltage of this output stage,
Reducing the junction capacitance C _d of the photodiode, it is necessary to reduce the noise voltage e _n. The junction capacitance C _d of the photodiode can be reduced by lowering the concentration on the substrate side or the well side of the photodiode, but this is also an array of photodiodes such as a line sensor or area sensor. If placed,
It cannot be made extremely small due to problems such as pixel separation.

The noise voltage e _n can be reduced by reducing the noise voltage of the MOS transistor by improving the device itself, and also by narrowing the frequency band. However, in general, the brightness of the object received by the sensor covers a wide range of about 10 ⁵ , so it is inevitable to image a dark object in a short integration time and still obtain a correct signal output for a bright object. The frequency band must be widened.

For example, when a subject of 1 lux is imaged with an integration time of 100 msec, it must be 1 μsec for 10 ⁵ lux. Therefore, it is necessary to set the band within the pixel so as to follow the integration time of 1 μsec.

That is, when the sensitivity is increased to image a dark subject in a short integration time, the band of the pixel amplifier must be widened to widen the dynamic range, and the amplifier must be widened to reduce noise. There is a problem that the dynamic range must be narrowed in order to narrow the band.

The present invention has been made in order to solve the above problems in an amplification type solid-state image pickup device using a pixel having an amplification element in a conventional pixel, and suppresses noise generated in the amplification element, Moreover, it is an object of the present invention to provide a solid-state imaging device having a wide dynamic range that can correctly follow a bright subject.

[0019]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a photodiode, a means for accumulating charges generated in the photodiode, and a resetting means for discharging accumulated photoelectric charges. And a solid-state imaging device including a sensor array in which a plurality of unit pixels having an amplification output for outputting an amplified output corresponding to the accumulated photocharges are arranged, corresponding to the amount of light incident on the photodiode of the unit pixel. Then, means for changing the frequency band of the amplifying means is provided.

With this configuration, the means for changing the frequency band narrows the band for a dark subject to reduce the noise voltage, and widens the band for a bright subject, thereby making the pixel It is possible to improve the followability of and secure a wide dynamic range.

[0021]

EXAMPLES Next, examples will be described. FIG. 1 is a circuit configuration diagram showing an embodiment in which the present invention is applied to a line sensor. This embodiment shows a line sensor composed of n pixels. In the drawing, 31-1, ... 31-n are pixels, and these pixels are the same as those of the conventional pixel shown in FIG. Through the sample-hold n-type MOS transistor 9 driven by the pulse φ _SH , to the output node of the source-grounded amplifier circuit to which the drains of the n-type MOS transistor 2 and the p-type MOS transistor 4 in the configuration are connected, The capacitor 8 is provided. The output node of each of these pixels is connected to the signal output line 7 via the n-type MOS transistor 6 for selection. 32 is an n-type MOS transistor for resetting the residual charge on the signal output line 7, 33 is also connected to the signal output line 7,
A buffer for low output impedance,
The output of the buffer 33 is connected to the output terminal V _OUT . Also, 34 is an n-type MOS transistor 6 for selection of each pixel.
Is a shift register for sequentially turning on.

The p-type MOS transistor 4 of each pixel
Is commonly connected to the power supply line V _DD , and the gate of the reset n-type MOS transistor 5 is commonly connected to the application terminal of the reset pulse φ _R. Further, the gate of the p-type MOS transistor 4 is commonly connected to each pixel and is connected to the bias circuit 35. The bias current I _BIAS of each pixel is the output voltage V _{BIAS of the} bias circuit 35.
It is determined by, I _BIAS increases when V _BIAS decreases, I _BIAS when V _BIAS approaches the power supply voltage V _DD has become smaller.

The present invention changes the frequency band of the pixel amplification circuit according to the brightness of the object to reduce the noise voltage generated in the n-type MOS transistor 2. In this embodiment, the bias voltage flowing in each pixel is reduced. The frequency band of each pixel is changed by changing the current. The frequency band of each pixel is determined by the bias current flowing through the n-type MOS transistor 2 and the load capacitance element 8. When the bias current is small, the band becomes narrow, and when the bias current is large, the band becomes wide. Therefore, when the subject is bright, the bias current is increased to widen the band, and when the subject is dark, the bias current is reduced to narrow the band.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG. In FIG.
The period T ₀ is a period in which the output voltage V _BIAS of the bias circuit 35 is set. The V _BIAS is set such that V _BIAS is low when the subject is bright and V _BIAS is set when the subject is dark.
Set _BIAS high. Further, the setting made in this period T ₀ is not changed and is kept constant until the reading of the pixel output is completed. Next, the period T ₁ is a period for resetting each pixel, and the reset pulse φ _{R is set} to the “H” level to reset each pixel.

Then, the integration is started when φ _R = “L”, and the integration operation is continued during the period T ₂ . After integration for a certain period of time, the pulse φ _SH is changed from “H” to “L” and the output integrated in the period T ₂ is held in the capacitive element 8. After that, in the period T ₃ , the shift register 34
Are driven to sequentially set the pulses φ ₁ , ..., φ _n to the “H” level, and each pixel signal output is read. At this time, pulse φ
_1, when any one of the · · · phi _n is at the "H" level, n-type M
After the pixel output is read by setting the gate voltage φ _RV of the OS transistor 32 to the “L” level, φ _RV = “H” is set to reset the electric charge of the previous pixel output remaining on the signal output line 7,
The next pixel output is read out.

The capacitance value of the capacitive element 8 is C _H , and the signal output line 7
The output V _OUT is expressed by the following equation (2), where C _{P is} the parasitic capacitance of V and the signal output of the pixel is V _S. V _OUT = C _H / (C _H + C _P ) ・ V _S・ ・ ・ ・ ・ (2)

Therefore, since the gain of the output depends only on the capacitance value C _H of the capacitive element 8, in the reading in this embodiment, the gain is constant even if the bias current is changed to change the frequency band of each pixel. You can get the output of

Next, the bias circuit will be described. FIG. 3 is a conceptual diagram showing an example of the configuration of a bias circuit. This bias circuit includes three types of current sources 41, 42, 43 and the current source 4
Three switching elements controlled by control signals D ₀ , D ₁ , D ₂ for connecting ₁ , 42, 43 to node 44
45, 46, 47 and a voltage corresponding to the current value I _BO are generated,
And a p-type MOS transistor 48 whose gate and drain are commonly connected.

In the bias circuit thus constructed, the current values I ₀ , I ₁ , I ₂ of the current sources 41, 42, 43 are changed to I
_{If 0} : I ₁ : I ₂ = 1: 9: 90 is set, p-type MOS
The current value I _BO of the transistor 48 is the control signals D ₀ , D ₁ ,
By switching the switching elements 45, 46, 47 with D ₂ , switching can be performed from the minimum current value to 100 times the minimum current value. The output voltage V _BIAS of the bias circuit is the current value I _BO.
The bias current I in each pixel.
_BIAS can also be changed up to 100 times.

FIG. 4 is a circuit configuration diagram showing a specific configuration example in which the bias circuit shown in the conceptual diagram of FIG. 3 is realized by MOS transistors. In FIG. 4, n-type MOS transistors 51, 52 and 53 are the current sources 41, 42 and 43 shown in FIG.
Corresponding to the n-type MOS transistors 51, 52,
By changing the gate size ratio W / L of 53, three types of current sources with different weights can be realized. Further, the switching elements 45, 46, 47 in FIG.
It is realized by transistors 55, 56 and 57. Reference numeral 58 is a reference current circuit which forms a current mirror circuit with the n-type MOS transistors 51, 52 and 53.

In the bias circuit having the above structure, the bias output voltage V _BIAS can be controlled by the control signals D ₀ , D ₁ and D ₂ , whereby the bias current I in the pixel is controlled.
It is possible to change _BIAS . In the configuration examples shown in FIGS. 3 and 4, three types of current sources are provided, but this is different from the current value of the current source depending on the brightness range of the subject and the step of setting the bias current. The ratio and the number may be set appropriately.

In the above-described embodiment, the band width is narrowed for a dark subject to reduce the noise voltage, and the band is widened for a bright subject to improve the followability of the pixel and wide dynamic range. The line sensor provided with the frequency band changing means for ensuring the range has been shown. Next, an embodiment having means for judging the brightness on the surface of the line sensor will be described.

FIG. 5 is a circuit configuration diagram showing an embodiment of a line sensor provided with a monitor means for knowing the state of accumulated charges in a pixel. This line sensor has 61 basic pixels
-1, ... 61-n are arranged in n pixels, and basically the same operation as described in the embodiment shown in FIG. 1 is performed. The difference from the embodiment shown in FIG. 1 is that an n-type MOS transistor 62 that operates as a source follower for monitoring is provided in each pixel.
The gate of the transistor 62 is connected to the output part of the grounded-source amplifier circuit in the pixel, the power supply voltage V _DD is applied to the drain, and the source is connected to the source line 63 commonly to each pixel to operate as a current source. Connected to the drain of the biasing n-type MOS transistor 64. Further, the source line 63 is further connected to the other input terminal of the comparator 65, one input terminal of which is connected to the reference voltage V _ref . Then, the monitoring n-type MOS transistor 62 gate is connected to the output of each pixel and the bias for the n-type MOS transistor 64, has a configuration of a peak detection circuit, the voltage V _M of the source line 63 , And shows the peak value of the output voltage of the pixel.

The line sensor having the peak value detecting function configured as described above is further provided with the following means so that the brightness on the sensor surface can be detected and the bias current I _BIAS can be controlled. Has become. That is, as shown in FIG. 5, it is reset by the reset pulse φ _R , operates at the start of integration of the pixel, and the time when the comparator 65 is inverted from the “L” level to the “H” level, that is, the peak value V of the pixel output voltage. A counter 66 that terminates counting when _M exceeds the reference voltage V _ref is provided, and the bias circuit is controlled by the control circuit 67 according to the value of the counter 66.
The bias current I _BIAS is controlled by controlling 35.

The line sensor thus constructed operates as follows. First, the setting of the bias current I _BIAS by the bias circuit 35 is minimized to perform the integration operation. At this time, if the sensor surface is bright, the comparator 65
Takes a short time to invert, and if the sensor surface is dark, it takes a long time to invert. Therefore, when the time until the inversion of the comparator 65 is longer than the reference time, the integration operation is performed as it is, and after a lapse of a certain integration time, the integration is ended and the reading is performed. This integration time control can be efficiently performed if it is performed based on the value of the counter 66.

When the time until the inversion of the comparator 65 is shorter than the reference time, the control circuit 67 sets the bias circuit 35 so that the bias current becomes large, and the reset operation is performed again and the integration operation is performed again. .

When there are two bias settings in the bias circuit 35, the bias current is switched by the above operation. When the bias circuit 35 is set to three or more, the reference time from the start of integration to the inversion of the comparator 65 may be set corresponding to the setting. Then, the integration may be performed by sequentially switching from the smaller bias current.

By performing such an operation, when the sensor surface is dark, that is, when the integration time is long, only one integration operation is required. When it is bright, even if the integration is performed a plurality of times,
Since the integration time per operation is short, the time until the pixel signal is read can be efficiently used.

Comparator in the embodiment shown in FIG.
The 65, the counter 66, and the control circuit 67 may be arranged on the same chip as the pixel, or may be formed as an external circuit.

Next, an embodiment using another means for detecting the brightness on the sensor surface will be described with reference to FIG. In this embodiment, a photodiode for monitoring is added to the embodiment shown in FIG. In the figure, each photodiode constituting the photodiode array 71 is
This corresponds to the photodiode 1 of the embodiment shown in FIG. 1, and the amplifier 72 at the next stage thereof represents an amplifier circuit in the pixel.
With respect to the line sensor having such a configuration, the monitoring photodiode 73 is provided near the photodiode array 71.
Is arranged, and the output of the photodiode 73 is converted into a voltage output by the logarithmic compression type current detection circuit 74 and is input to the control circuit 67.

Photodiode for such a monitor
By disposing 73 in the vicinity of the photodiode array 71, the brightness on the sensor surface can be detected by the output voltage of the current detection circuit 74. Therefore, the current detection circuit 74
According to the output voltage of the control circuit 67, the bias circuit 35
By setting the bias current via the, it becomes possible to set the bias current according to the brightness of the sensor surface.

In the embodiment shown in FIG. 6, when the monitor photodiode 73 and the photodiode array 71 forming the pixel group use optical systems having extremely different brightness, the error becomes large. I can't put it into practice. FIG. 7 is a circuit configuration diagram showing another embodiment in which the brightness on the sensor surface can be detected. The embodiment shown in FIG. 7 is different from the embodiment shown in FIG. 6 in that the embodiment shown in FIG. 6 has a photodiode 73 for a monitor for detecting light. The point is that the brightness is detected by the photocurrent flowing to the substrate side or the well side of the photodiode array 71 forming each pixel. In the configuration according to this embodiment, the direction of the photocurrent is opposite to that of the embodiment shown in FIG. 6 and a negative potential is generated in the current detection circuit 74, but the operation is the same as that of the embodiment shown in FIG. As explained in,
The output voltage of the current detection circuit 74 determines the brightness on the sensor surface, and the bias current value is set.

As described above, by detecting the brightness on the sensor surface by various means, the bias current can be set according to the brightness on the sensor surface.

In each of the above-described embodiments, the means for changing the frequency band of the pixel in accordance with the brightness on the sensor surface has been described by changing the bias current in each pixel. Since the frequency band of the pixel can be changed even if the capacitance value of the load capacitance element 8 is changed as described above, the bias current is kept constant and a means for switching the capacitance value of the load capacitance element 8 is used. Good. But,
In the signal readout method in this pixel configuration, the gain also changes when the frequency band is changed by directly switching the capacitance value. Therefore, in order to prevent this, the configuration of each pixel is changed to a source follower operating as a buffer as shown in FIG. It may be configured to output via a circuit.

In FIG. 8, an n-type MOS transistor 81
Operates as a source follower, and the pixel output is output from the signal output line 7 through the n-type MOS transistor 81.
Is output to. Reference numerals 82 and 83 are a switching n-type MOS transistor and a capacitance element for switching the capacitance value. When the pulse φ _C applied to the gate of the n-type MOS transistor 82 is set to “H” level, the capacitance element 83 The frequency band is narrowed by the addition, and the frequency band is widened when φ _C = “L”. By using the pixel configuration as described above, even if the frequency band is changed by switching the capacitance value of the load capacitance element, the gain is not affected.

Next, an embodiment in which the present invention is applied to a pixel configuration having the conventional FPN suppressing circuit shown in FIG. 15, that is, a pixel configuration having a two-stage amplifying circuit will be described with reference to FIG. explain. Also in this case, as in each of the above embodiments, either the bias current switching means or the load capacitance value switching means may be used.

First, the case where the means for switching the bias current is applied will be described. This case can be realized by controlling the voltage V _BIAS1 applied to the gate of the p-type MOS transistor 4 of the pixel S shown in FIG. 15, and the control is performed by the same means as in each of the above embodiments. be able to. At this time, the n-type MOS transistor 17, which constitutes the inverting amplifier circuit shown in FIG.
The voltage V _BIAS2 applied to each gate of 20 may always be kept at a constant value. As means for detecting the brightness of the sensor surface, a means for providing each pixel with an n-type MOS transistor 62 that operates as a monitor source follower shown in the embodiment shown in FIG. 5, and the photo shown in the embodiment shown in FIG. The means for providing the monitor photodiode 73 in the vicinity of the diode array and the means for detecting the current flowing to the substrate or well side of the photodiode array forming each pixel shown in the embodiment of FIG. 7 can be similarly used. .

Next, a means for changing the frequency band by switching the capacitance value of the load capacitance element will be described. In this case, as shown in FIG. 9, similarly to the embodiment shown in FIG.
It is also possible to provide a switching n-type MOS transistor 82 and a capacitive element 83 for switching the capacitance value at the input part of the input capacitive element 11 so as to switch the band without changing the sensitivity, but it is intentional. It is more efficient to switch the frequency band to and the sensitivity at the same time as described below.

That is, when the sensor surface is bright, the integration time becomes short. Therefore, if the sensitivity is high, the response time of the control circuit must be increased in order to perform the integration time control. Therefore, it is better that the sensitivity is low when the sensor surface is bright.
Further, when the sensor surface is dark, if the sensitivity is low, the integration time is very long to obtain a constant signal output level, so the sensitivity should be as high as possible. Considering this in relation to the frequency band, the sensitivity may be low when the band is wide and the sensitivity may be high when the band is narrow.

FIG. 10 shows an embodiment configured to realize the above-described operation. In this embodiment, in the conventional configuration shown in FIG. 15, the capacitance element 85 (capacitance value C ₃ ) for switching the band and sensitivity, the switching p-type MOS transistor 86, and the input capacitance element 11 (capacitance value C ₁ ) Is connected in parallel.

In the embodiment thus constructed, the gate application pulse φ _C of the p-type MOS transistor 86 is set to "L".
When the level is set and the p-type MOS transistor 86 is turned on, the load capacitance value of the node 24 becomes (C ₁ + C ₃ ), the frequency band becomes narrow, and it is composed of the inverting amplifier circuit and the n-type MOS transistors 19 and 20. The gain of the amplifier circuit at the stage is (C ₁ + C ₃ ) / C ₂ , which is high. Also φ _C =
When the p-type MOS transistor 86 is turned off at "H", the band becomes wider and the gain of the second-stage amplifier circuit is C
_It becomes ₁ / C _{2 and} becomes lower. Thus, according to this embodiment, it is possible to efficiently switch the band and the sensitivity.

Next, the embodiment shown in FIG. 9 and FIG.
In the embodiment described with reference to 15, how to set the timings of the pulse φ _R and the pulse φ _RC when the frequency band of the pixel S in the first stage is changed,
This will be described with reference to the timing chart shown in FIG. Figure
At 16 in the period T ₂ from turning off the reset pulse φ _R (from “H” to “L”) to turning off the pulse φ _RC (from “L” to “H”), the potential V _P of the node 24 Is gradually rising, but this is due to the reset pulse φ
_The charge amount due to the feed-through generated when the reset n-type MOS transistor 5 is turned off from the on state is accumulated in the capacitive element 3 (capacitance value C ₀ ) when _R is turned off. This rise in the potential V _P of the node 24 by the feed-through is over, it is desirable to pulse φ the _RC "H" level when it becomes a steady state.

However, as described above, if the pixel band is changed according to the brightness, the rise time of the potential rise due to this feed through also changes. That is, when the band is wide, the rise time is short, and when the band is narrow, the rise time is long. Therefore, the period T ₂ must be adjusted to the rise time with a narrow band, but if the period T ₂ is too long, the pixels S in the first stage will be saturated during the period T ₂ when the sensor surface is bright. Therefore, it is desirable that the period T ₂ be variable according to the pixel band, and more desirably, the timing of the pulse φ _RC can be obtained with a simple configuration while interlocking with the pixel band.

FIG. 11 shows a timing generating circuit for the pulse φ _RC when the frequency band of each pixel is configured by changing the bias current to change the frequency band, and FIG. 12 shows the band by changing the capacitance value of the load capacitance element. A timing generation circuit for the pulse φ _RC when configured by using the switching method is shown.

In FIG. 11, reference numeral 90 denotes a p-type MOS transistor that operates as a current source, and has a gate connected to the bias output voltage V _BIAS1 so that a current corresponding to the bias current of each pixel flows. . 91 is an n-type MOS transistor driven by a reset pulse φ _R , 92 is a capacitive element, and 93, 94, 95 and 96 are inverter circuits. Further, in the timing generation circuit shown in FIG. 12, an n-type MOS transistor 98 controlled by a pulse φ _C and a capacitive element 97 are added. Instead of the inverter circuits 93 to 96, it is possible to use a comparator in which one end of the input is connected to the reference voltage.

Next, the operation of these timing generation circuits will be described with reference to the timing chart shown in FIG. When the reset pulse φ _R is “H” level, n-type M
Since the OS transistor 91 is turned on, the node 100
Is at ground level. When φ _R = “L”, the current source p-type MOS transistor 90 charges the capacitive element 92 (and 97) and the potential of the node 100 rises.

In the timing generating circuit shown in FIG. 11, the current value of the current source p-type MOS transistor 90 is linked to the bias current of each pixel, so that the current value is large when the pixel band is wide, The rising slope of the node 100 also becomes steep, and conversely, when the pixel band is narrow, the current value is small and the slope becomes gentle. In the timing generation circuit shown in FIG. 12, the same effect can be obtained by setting the pulse φ _C to the “H” level when the pixel band is narrow and the pulse φ _C to the L level when the band is wide. can get.

Therefore, when the band is wide, the period from the fall of the reset pulse φ _R to the rise of the pulse φ _RC becomes short, and conversely, when the band is narrow, the fall of the reset pulse φ _R to the rise of pulse φ _RC . Will be long. That is, according to the frequency band of the pixel, the pulse φ
The rising _edge of _RC can be changed.

In the timing generation circuit shown in FIG. 11, the bias current of the current source p-type MOS transistor 90 follows the bias current of the pixel as it is. Further, in the timing generation circuit shown in FIG. 12, it is possible to follow the same by adjusting the ratio of the capacitance values of the capacitive elements 92 and 97 to the ratio of the capacitance values for switching the band in the pixel. In this way, the timing of the pulse φ _RC can be formed according to the frequency band of the pixel.

By using the timing generation circuit shown in FIGS. 11 and 12, the embodiment shown in FIGS.
Also, as in the embodiment described using the conventional example shown in FIG. 15, even in a sensor using a pixel configuration in which an amplifier circuit has a two-stage configuration, the brightness on the sensor surface is wide in a wide range of brightness. Correspondingly, it is possible to improve the S / N by changing the frequency band in the pixel.

[0061]

As described above on the basis of the embodiments,
According to the present invention, since the frequency band of the pixel is changed according to the brightness of the subject, the noise generated in the amplification means in the pixel is minimized while maintaining the wide dynamic range, and the high S / N can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a conceptual diagram showing a configuration example of a bias circuit of the embodiment shown in FIG.

FIG. 4 is a circuit configuration diagram showing a specific configuration of the bias circuit shown in FIG.

FIG. 5 is a circuit configuration diagram showing an embodiment including means for detecting the brightness on the sensor surface.

FIG. 6 is a circuit configuration diagram showing another embodiment including means for detecting the brightness on the sensor surface.

FIG. 7 is a circuit configuration diagram showing still another embodiment including means for detecting the brightness on the sensor surface.

FIG. 8 is a diagram showing a pixel portion according to another embodiment of the present invention.

FIG. 9 is a circuit configuration diagram showing one pixel portion of an embodiment in which the present invention is applied to a solid-state imaging device having pixels having an FPN suppressing circuit.

FIG. 10 is a circuit configuration diagram showing a pixel portion of another embodiment in which the present invention is applied to a solid-state imaging device having a pixel having an FPN suppression circuit.

11 is a diagram showing a configuration example of a timing generation circuit used in the embodiments shown in FIGS. 9 and 10. FIG.

12 is a diagram showing another configuration example of the timing generation circuit used in the embodiments shown in FIGS. 9 and 10. FIG.

FIG. 13 is a timing chart for explaining the operation of the timing generation circuit shown in FIGS. 11 and 12.

FIG. 14 is a circuit configuration diagram showing an example of a conventional pixel configuration having an amplification function.

FIG. 15 is a circuit configuration diagram showing an example of a pixel configuration having a conventional FPN suppression circuit.

16 is a timing chart for explaining the configuration example shown in FIG.

17 is a diagram showing an equivalent circuit at the time of integration operation of the configuration example shown in FIG. 15.

[Explanation of symbols]

 1 Photodiode 2 n-type MOS transistor 3 capacitance element 4 p-type MOS transistor 5 n-type MOS transistor for reset 6 n-type MOS transistor for selection 7 signal output line 8 load capacitance element 9 n-type MOS transistor for sample hold 11 input capacitance element 31-1, ... 31-n Pixel 32 Signal output line reset n-type MOS transistor 33 Buffer 34 Shift register 35 Bias circuit

Claims (17)

[Claims] 1. A photodiode, means for accumulating charges generated in the photodiode, reset means for discharging accumulated photoelectric charges, and amplification means for outputting an amplified output corresponding to the accumulated photoelectric charges. In a solid-state image pickup device including a sensor array in which a plurality of unit pixels having the above are arranged, a unit for changing the frequency band of the amplifying unit is provided in accordance with the amount of light incident on the photodiode of the unit pixel. Solid-state imaging device. 2. The means for changing the frequency band of the amplifying means changes the frequency band of the amplifying means based on a means for detecting the amount of light incident on the photodiode of the unit pixel and a detection signal from the light amount detecting means. The solid-state imaging device according to claim 1, comprising a band changing unit. 3. The solid-state imaging device according to claim 2, wherein the band changing unit is configured by a unit that changes a bias current supplied to the amplifying unit. 4. The solid-state imaging device according to claim 2, wherein the band changing unit is configured by a unit that changes a capacitance value of a load capacitance element connected to the output unit of the amplifying unit. 5. The incident light amount detection means is composed of a monitor photodiode provided in the vicinity of the sensor array and a circuit for detecting a photocurrent value generated in the monitor photodiode. 5. The solid-state imaging device according to claim 2, wherein the frequency band is set based on the photocurrent value in. 6. The incident light amount detecting means is composed of a circuit for detecting a current value flowing in a common substrate or well of the photodiodes of the unit pixels forming the sensor array, and the light at the start of integration is detected. The solid-state imaging device according to claim 2, wherein the frequency band is set based on a current value. 7. The incident light amount detecting means includes means for detecting a peak value of an amplified output of the sensor array, comparing means for comparing a detection signal from the peak value detecting means with a reference value, and after resetting a pixel. It is constituted by means for counting the time from the start of integration to the time when the output of the comparison means is inverted, and a control section for controlling the setting of the frequency band according to the output signal of the counting means. Item 2,
The solid-state imaging device according to any one of 3 and 4. 8. A photodiode, a means for accumulating charges generated in the photodiode, a first resetting means for discharging accumulated photoelectric charges, and a first output for outputting an amplified output corresponding to the accumulated photoelectric charges. A pixel including an amplifying means, an inverting amplifier circuit connected to the output section of the pixel via a first capacitor element, and a second capacitor element connected to a feedback system between the input and output of the inverting amplifier circuit. A unit cell is formed by a second amplifying means including one or a plurality of switching means for performing a clamping operation of the first capacitive element and a resetting of the second capacitive element, and a plurality of the unit cells are arranged. In the solid-state imaging device including the sensor array described above, the first image sensor corresponding to the amount of light incident on the photodiode of the unit pixel
Solid-state image pickup device comprising means for changing the frequency band of the amplifying means. 9. The means for changing the frequency band of the first amplifying means includes means for detecting the quantity of light incident on the photodiode of the pixel, and the first amplifying means based on a detection signal from the light quantity detecting means. 9. The solid-state imaging device according to claim 8, wherein the solid-state imaging device comprises a band changing unit that changes the frequency band of. 10. The band changing unit is configured by a unit that changes a capacitance value of a first capacitive element connected to an output unit of the pixel, and the band changing unit is configured to change the frequency band of the first amplifying unit. The solid-state imaging device according to claim 9, wherein the gain of the second amplifying unit is also changed. 11. The solid-state imaging device according to claim 9, wherein the band changing unit includes a unit that changes a bias current supplied to the first amplifying unit. 12. The first resetting means of the pixel is released, and then the switching means for performing the clamp operation of the first capacitive element and the resetting of the second capacitive element of the second amplifying means is released. 12. The solid-state imaging device according to claim 8, further comprising a timing setting unit that changes a period until the time corresponding to the setting of the frequency band of the first amplifying unit. . 13. The timing setting means, a capacitive element, a current source for charging the capacitive element, a switching means connected to both ends of the capacitive element and driven in synchronization with the first reset means, A circuit for delaying a falling edge consisting of an inverter or a comparator whose input section is connected to the connection point of the current source and the capacitive element,
13. The solid-state imaging device according to claim 12, wherein the capacitance value of the capacitive element is changed in accordance with the setting of the frequency band of the first amplifying means. 14. The timing setting means, a capacitive element, a current source for charging the capacitive element, a switching means connected to both ends of the capacitive element and driven in synchronization with the first reset means, A circuit for delaying a falling edge consisting of an inverter or a comparator whose input section is connected to the connection point of the current source and the capacitive element,
13. The solid-state imaging device according to claim 12, wherein the current value of the current source is changed according to the setting of the frequency band of the first amplifying means. 15. The incident light amount detecting means includes a monitoring photodiode provided in the vicinity of the sensor array and a circuit for detecting a photocurrent value generated in the monitoring photodiode, and when the integration starts. 15. The solid-state imaging device according to claim 9, wherein the frequency band is set on the basis of the photocurrent value in. 16. The incident light amount detection means is configured by a circuit that detects a current value flowing in a common substrate or well of each photodiode of each pixel that configures the sensor array, 10. The frequency band is set based on the current value.
15. The solid-state imaging device according to claim 14. 17. The incident light amount detection means includes means for detecting a peak value of an amplified output of the sensor array, comparison means for comparing a detection signal from the peak value detection means with a reference value, and after resetting pixels. It is constituted by means for counting the time from the start of integration to the time when the output of the comparison means is inverted, and a control section for controlling the setting of the frequency band according to the output signal of the counting means. Item 9-14
The solid-state imaging device according to any one of 1.