CN109257548B - CMOS image sensor and image output method - Google Patents
CMOS image sensor and image output method Download PDFInfo
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- CN109257548B CN109257548B CN201810908148.3A CN201810908148A CN109257548B CN 109257548 B CN109257548 B CN 109257548B CN 201810908148 A CN201810908148 A CN 201810908148A CN 109257548 B CN109257548 B CN 109257548B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Abstract
The invention discloses a CMOS image sensor which comprises a pixel array, A/2 column-level sampling and holding circuits, a column selection coding and driving circuit and a production line analog-to-digital converter, wherein the pixel array comprises B rows and A columns of pixel units, the m column of pixel units and the m +1 column of pixel units share one column-level sampling and holding circuit, the A/2 column-level sampling and holding circuits are connected to the column selection coding and driving circuit, and the other end of the column selection coding and driving circuit is connected with the production line analog-to-digital converter. According to the CMOS image sensor provided by the invention, the switch and the capacitor are added in the pixel unit, two adjacent rows of pixel units share one row-level sampling and holding circuit, and a complete image can be output through one exposure.
Description
Technical Field
The invention relates to the field of image sensors, in particular to a CMOS image sensor and an image output method.
Background
Image sensors for consumer electronics have a high demand for cost performance. On the premise of keeping the performance unchanged, the number of chips produced on each wafer is increased by reducing the area of the image sensor chip, and the method is a direct mode for reducing the product cost. Therefore, image sensors have begun to adopt chip-scale pipelined analog-to-digital converter type image sensors, i.e., one image sensor uses only one pipelined analog-to-digital converter. Compared with the conventional image sensor adopting the column-level analog-to-digital converter, namely the image sensor which needs to correspond to one column-level analog-to-digital converter for each column of pixel units, the image sensor adopting the chip-level pipeline analog-to-digital converter type has certain miniaturization advantage in the chip area of the reading circuit.
In the prior art, a column-level sample-and-hold circuit uses a group of 2 sample-and-hold capacitors for a column of pixel cells, and the sample-and-hold capacitors include a capacitor for storing a reset signal and another capacitor for storing an optical signal, as shown in fig. 1. The pixel units of each column on a row are sequentially and serially passed through a pipeline type analog-to-digital converter to be converted into digital signals of a row, and then the whole image is output row by row. The sampling capacitor in the prior art is also drawn in the layout area of a column-level circuit, as shown in fig. 2.
However, since the image sensor structure in the prior art needs to adopt a column-level correlated double sampling circuit, the sample-hold capacitor in the sampling circuit still occupies a large part of the chip area, and especially in order to ensure the matching of the sampled signals, avoid distortion and reduce the introduction of noise, the value of the sampling capacitor needs to be larger and better. In practical production application, the capacitance value of each two sampling capacitors is about 500fF, and in order to ensure that the capacitance value is large enough, the area of the column-level correlated double sampling circuit needs to be large enough, so that the column-level correlated double sampling circuit needs to occupy a relatively large area in the whole image sensor layout, and the high-integration development direction of a chip is not facilitated.
In view of the high requirement for the photosensitive performance, the image sensor pixel unit generally needs to maintain the area as large as possible, and the size of the pixel unit is substantially uniform for a certain optical lens size. Therefore, it is still necessary to further explore more reasonable pixel cell structures and layout layouts and reasonably integrate the readout circuits to reduce the chip area of the image sensor except for the pixel array, while maintaining the performance of the product.
Disclosure of Invention
The invention aims to provide a CMOS image sensor, wherein a switch and a capacitor for storing signals are added in a pixel unit, two adjacent columns of pixel units share one column-level sampling and holding circuit and one column-level reading circuit, and a complete image can be output through one-time exposure.
In order to achieve the purpose, the invention adopts the following technical scheme: a CMOS image sensor comprises a pixel array, A/2 column-level sampling and holding circuits, a column selection coding and driving circuit and a pipeline analog-to-digital converter, wherein the pixel array comprises B rows and A columns of pixel units, the m column of pixel units and the m +1 column of pixel units share one column-level sampling and holding circuit, the A/2 column-level sampling and holding circuits are connected to the column selection coding and driving circuit, and the other end of the column selection coding and driving circuit is connected with the pipeline analog-to-digital converter; wherein A is an even number greater than or equal to 2, B is an integer greater than or equal to 1, m is an odd number, and m is greater than or equal to 1 and is less than A.
Furthermore, the mth column pixel unit in the nth row and the mth +1 column pixel unit in the nth row in the pixel array are reset and exposed at the same time and read out sequentially, wherein n is an integer and is greater than or equal to 1 and less than or equal to B.
Further, the CMOS image sensor also comprises A/2 column-level readout circuits, wherein the m column of pixel units and the m +1 column of pixel units in the pixel array share one column-level readout circuit.
Further, the nth row and mth column of pixel units comprise photodiodes PDn,mA transfer control MOS tube MT1_ n, a switch S01_ n and a capacitor C01_ n, wherein the n row and the m +1 column of pixel units comprise a photodiode PDn,m+1The transmission control MOS tube MT2_ n, the switch S02_ n and the capacitor C02_ n, the mth row and mth column pixel units and the nth row and m +1 th row pixel units share the reset MOS tube MR _ n, the amplification MOS tube MF _ n and the row selection MOS tube Mrow _ n, and the specific connection relationship is as follows: the photodiode PDn,mThe anode of the transistor is connected with the ground level, and the cathode of the transistor is connected with the drain of the transmission control MOS transistor MT1_ n; a source of the transmission control MOS transistor MT1_ n is commonly connected to one end of the capacitor C01_ n and one end of the switch SO1_ n, and a gate of the transmission control MOS transistor MT1_ n is connected to a transmission control signal TX01_ n; the other end of the capacitor C01_ n is connected with the ground level; the other end of the switch S01_ n is commonly connected with the grid electrode of the amplifying MOS tube MF _ n, the source electrode of the resetting MOS tube MR _ n and one end of the switch S02_ n; the photodiode PDn,m+1Is connected to ground level, negativeThe pole of the transistor is connected with the drain electrode of the transmission control MOS transistor MT2_ n; a source electrode of the transmission control MOS tube MT2_ n is commonly connected with one end of the capacitor C02_ n and the other end of the switch SO2_ n, and a gate electrode of the transmission control MOS tube MT2_ n is connected with a transmission control signal TX02_ n; the other end of the capacitor C02_ n is connected with the ground level; the other end of the switch S02_ n is commonly connected with the grid electrode of the amplifying MOS tube MF _ n, the source electrode of the resetting MOS tube MR _ n and one end of the switch S01_ n; the grid electrode of the reset MOS tube MR _ n is connected with a reset signal RST _ n, and the drain electrode of the reset MOS tube MR _ n is connected with a power supply anode VDD; the drain electrode of the amplifying MOS tube MF _ n is connected with a power supply anode VDD, the source electrode of the amplifying MOS tube MF _ n is connected with the drain electrode of the row selection MOS tube Mrow _ n, the grid electrode of the row selection MOS tube Mrow _ n is connected with a row selection signal RS _ n, and the source electrode of the row selection MOS tube Mrow _ n is used as a common signal output end of pixel units of the mth row and the (m + 1) th row in the image sensor array.
Further, the signal output ends of each column of pixel units in the pixel array are connected together.
Furthermore, the control signals of the odd columns in each row of pixel units in the pixel array are the same, and the control signals of the even columns are the same.
Furthermore, the MOS tubes in the pixel unit are all NMOS tubes.
Further, the source and drain electrodes in the pixel array may be interchanged.
A method for outputting images by using the CMOS image sensor comprises the following steps:
s01: simultaneously closing the switch S01_ n and the switch S02_ n in the pixel unit in the nth row in the pixel array, and simultaneously resetting the pixel unit in the nth row in the pixel array; wherein n is an integer, and n is more than or equal to 1 and less than or equal to B;
s02: opening a switch S02_ n to hold the reset signal of the pixel unit in the even column in the nth row of the pixel array;
s03: exposing the pixel units in the nth row of the pixel array at the same time, wherein the exposed optical signals are stored in the photodiodes;
s04: the control signal TX01_ n changes to high level so that the optical signals in the photodiodes in the pixel units of the odd columns in the nth row are transmitted to the capacitor C01_ n, and then the images of the odd columns in the nth row are read out;
s05: the control signal TX02_ n changes to high level so that the optical signals in the photodiodes in the pixel cells of the even columns in the nth row are transmitted to the capacitor C02_ n, and then the images of the even column groups in the nth row are read out;
s06: combining the odd-numbered column images and the even-numbered column images in the nth row into an nth row image;
s07: steps S01-S06 are repeated with a reset exposure readout of all rows in the pixel array resulting in a complete image.
The invention has the beneficial effects that: the pixel units are added with switches and capacitors for storing signals, and the adjacent odd-even column pixel units share one column-level sample hold circuit, and the odd-even column images can be output after one exposure. Compared with the prior art in which each column of pixels corresponds to one column-level sample-and-hold circuit, the invention can realize miniaturization on the chip area. Meanwhile, the column-level sample-and-hold circuit shared by odd and even columns can avoid the loss of layout area between columns due to the requirement of a design rule, so that the area occupied by the chip in the column direction is further reduced under the condition of a certain capacitance value. Therefore, the structure of the invention can greatly reduce the chip area and achieve the effect of reducing the chip cost.
Drawings
Fig. 1 is a schematic diagram of a column-level sample-and-hold circuit in the prior art.
Fig. 2 is a schematic structural diagram of a CMOS image sensor in the prior art.
Fig. 3 is a schematic structural diagram of a pixel unit of a CMOS image sensor in the prior art.
Fig. 4 is a schematic structural diagram of a CMOS image sensor according to the present invention.
Fig. 5 is a schematic structural diagram of a pixel unit of a CMOS image sensor according to the present invention.
Fig. 6 is a layout diagram of a CMOS image sensor according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, a typical column-level sample-and-hold circuit uses a group of 2 sample-and-hold capacitors for a column of pixel cells, and specifically includes one capacitor for storing a reset signal and another capacitor for storing an optical signal. The pixel units of each column on a row are sequentially and serially passed through a pipeline type analog-to-digital converter to be converted into digital signals of a row, and then the whole image is output row by row. The sampling capacitance is also plotted in the layout area of a column level circuit, as shown in fig. 2.
In the prior art, the structure of the pixel unit corresponding to the above column-level sample-and-hold circuit is shown in fig. 3, the structure of each pixel unit is the same, the anode of the photodiode PD of the mth column pixel unit in the nth row in the image sensor array is connected to the ground level, the cathode of the photodiode PD is connected to the drain of the transmission control MOS transistor MT _ n, the source of the transmission control MOS transistor MT _ n is connected to the gate of the amplification MOS transistor MF _ n, the source of the reset MOS transistor MR _ n is connected together, and the gate of the transmission control MOS transistor MT _ n is connected to the transmission control signal TX _ n; the drain electrode of the reset MOS tube MR _ n is connected with the positive electrode of the power supply, and the grid electrode of the reset MOS tube MR _ n is connected with a reset signal; the drain electrode of the amplifying MOS tube MF _ n is connected with the power supply anode VDD, the source electrode of the amplifying MOS tube MF _ n is connected with the drain electrode of the row selection MOS tube Mrow _ n, the grid electrode of the row selection MOS tube Mrow _ n is connected with a row selection signal RS _ n, and the source electrode of the row selection MOS tube Mrow _ n is used as the signal output end of the nth row and mth column pixel unit in the image sensor array. Wherein m and n represent any pixel unit in the pixel array, and the whole pixel array structure is shown in fig. 3.
In the conventional pixel unit as shown in fig. 3, the pixels in each row are subjected to reset exposure simultaneously, and the pixel unit in each column corresponds to a column-level sample-and-hold circuit and a column-level readout circuit, and after the pixels in each row are subjected to simultaneous reset exposure, the electrical signals in the pixel units in each row are read out by the corresponding column-level readout circuit.
The innovation point of the invention is that the number of the column-level sampling hold circuits and the column-level readout circuits is reduced by half, namely two adjacent columns of pixel units share one column-level sampling hold circuit and one column-level readout circuit; this can reduce the area occupied by the column-level sample-and-hold circuit and the column-level readout circuit, and a larger capacitance value can be set on the same area. Different from the structure that the same column of pixel units share one group of readout circuits in the prior art, the invention adopts the structure that the adjacent odd-even column of pixel units share one group of column-level readout circuits and column-level sample hold circuits, and certain difficulty can be encountered in reading out the signals of the whole pixel array: because the reset clearing and exposure of each row are all completed at the same time, namely, a pair of odd and even columns of each row are reset and exposed at the same time, but the readout circuit is shared, so that the odd column signals and the even column signals on one row cannot be read out simultaneously. If no particular pixel structure is used, the odd columns are read first and then the even columns, although the readout circuitry, including the time for analog-to-digital conversion, is the same because the total number of signals is the same. However, this requires 2 exposures, i.e. after reading the odd columns, the same exposure is repeated to read the even columns. Thus, the frame rate of the image sensor may be greatly reduced. The present invention therefore requires the use of a different pixel cell structure than the prior art, so that adjacent odd and even column pixels are read out sequentially through a reset exposure. Specifically, the structure of the pixel unit in the invention adds a switch and a capacitor for storing an electric signal, and the adjacent odd-even column pixel units share one column-level sample hold circuit, so that an odd-even column image can be output through one exposure, and the whole image can be read out through one reset exposure as in the existing sensor.
As shown in fig. 5, the pixel unit in the present invention adopts the following structure: since the pixels of the adjacent odd-even columns share one column-level sample-and-hold circuit, the structure of the pixel unit in the invention is described in fig. 3 by taking two pixel units of one row in the adjacent odd-even columns as an example: specifically, the description will be given by taking the pixel unit in the mth row and the pixel unit in the m +1 th row as an example:
the nth row and the mth column of pixel units comprise photodiodes PDn,mA transfer control MOS tube MT1_ n, a switch S01_ n and a capacitor C01_ n, wherein the (n) th row and (m + 1) th column of pixel units comprise a photodiode PDn,m+1The transfer control MOS tube MT2_ n, the switch S02_ n and the capacitor C02_ n, the mth column pixel unit in the nth row and the mth +1 column pixel unit in the nth row share the reset MOS tube MR _ n, the amplifying MOS tube MF _ n and the row selection MOS tube Mrow _ n. Wherein n is an integer, and n is more than or equal to 1 and less than or equal to B; m is an odd number, and m is more than or equal to 1 and less than A.
The specific connection relationship is as follows: photodiode PDn,mThe anode of the transistor is connected with the ground level, and the cathode of the transistor is connected with the drain of a transmission control MOS transistor MT1_ n; a source electrode of the transmission control MOS tube MT1_ n is commonly connected with one end of the capacitor C01_ n and one end of the switch SO1_ n, and a grid electrode of the transmission control MOS tube MT1_ n is connected with a transmission control signal TX01_ n; the other end of the capacitor C01_ n is connected with the ground level; the other end of the switch S01_ n is commonly connected with the grid electrode of the amplifying MOS tube MF _ n, the source electrode of the resetting MOS tube MR _ n and one end of the switch S02_ n; photodiode PDn,m+1The anode of the transistor is connected with the ground level, and the cathode of the transistor is connected with the drain of a transmission control MOS transistor MT2_ n; the source electrode of the transmission control MOS tube MT2_ n is commonly connected with one end of the capacitor C02_ n and the other end of the switch SO2_ n, and the gate electrode of the transmission control MOS tube MT2_ n is connected with a transmission control signal TX02_ n; the other end of the capacitor C02_ n is connected with the ground level; the other end of the switch S02_ n is commonly connected with the grid electrode of the amplifying MOS tube MF _ n, the source electrode of the resetting MOS tube MR _ n and one end of the switch S01_ n; the grid electrode of the reset MOS tube MR _ n is connected with a reset signal RST _ n, and the drain electrode of the reset MOS tube MR _ n is connected with a power supply anode VDD; the drain electrode of the amplifying MOS tube MF _ n is connected with a power supply positive electrode VDD, the source electrode of the amplifying MOS tube MF _ n is connected with the drain electrode of the row selection MOS tube Mrow _ n, the grid electrode of the row selection MOS tube Mrow _ n is connected with a row selection signal RS _ n, and the source electrode of the row selection MOS tube Mrow _ n serves as a common signal output end of the nth row pixel unit, the m-column pixel unit and the m + 1-column pixel unit in the image sensor array. By analogy, the output ends of the pixel units in the (n) th row and the (m + 2) th column and the (m + 3) th column are connected to be used as a common output end. And the outputs in the same column are connected together.
The structures of the pixel units of the odd-even columns of the two adjacent rows in the pixel array in the invention are the same as the above expression, the pixel units of the m-th column and the m + 1-th column of the (n + 1) -th row can be referred to as the pixel unit shown in fig. 5, and of course, the structures of the pixel units outside the fig. 5 are also the same as the above expression.
Referring to fig. 5, in the pixel array of the present invention, the control signals of the odd-numbered rows in each row of the pixel units are the same, and the control signals of the even-numbered rows are the same. The MOS tube can be an NMOS tube or a PMOS tube at the same time, and the source electrode and the drain electrode of the MOS tube can be interchanged.
Referring to fig. 6, the structure and layout of sharing one column-level sample-and-hold circuit for odd and even columns based on the odd and even column sharing pixel unit structure of the present invention can greatly reduce the layout area required by the image sensor readout circuit. Meanwhile, the sharing structure provided by the invention can avoid the area loss of the active region caused by the layout design rule, thereby further reducing the occupied area of the whole read-out circuit layout, and the principle is shown in fig. 6. In the prior art, a certain distance exists between layouts of each group of column-level sample-and-hold circuits, because the production design rule of the layouts is to be met, as shown in the upper left corner of the attached drawing 6, because each column-level sample-and-hold circuit is provided with two capacitors, namely a capacitor I for storing a reset signal and a capacitor II for storing an optical signal, in the prior art, four MOS capacitors exist in two column-level sample-and-hold circuits, and because the production design rule of the layouts, certain distances need to be kept between every two capacitors, and the distances occupy partial areas in the layouts. However, with the structure of the odd-even column sharing column-level sample-and-hold circuit in the present invention, the adjacent odd-even column pixel units only need one column-level sample-and-hold circuit, corresponding to two capacitors, and therefore only need to keep a gap between the two MOS capacitors, as shown in the schematic diagram of MOS capacitors at the lower left corner and the upper right corner in fig. 6. That is to say, the invention reduces the layout area wasted by the gap between the MOS capacitors, and can avoid the area loss caused by the design rule if the MOS capacitors with the same size need to be drawn. Therefore, the capacitance value and the layout area with the same size can be more miniaturized.
The method for outputting the image by adopting the CMOS image sensor comprises the following steps:
s01: simultaneously closing the switch S01_ n and the switch S02_ n in the pixel unit in the nth row in the pixel array, and simultaneously resetting the pixel unit in the nth row in the pixel array; wherein n is an integer, and n is more than or equal to 1 and less than or equal to B;
s02: opening a switch S02_ n to hold the reset signal of the pixel unit in the even column in the nth row of the pixel array;
s03: exposing the pixel units in the nth row of the pixel array at the same time, wherein the exposed optical signals are stored in the photodiodes;
s04: the control signal TX01_ n changes to high level so that the optical signals in the photodiodes in the pixel units of the odd columns in the nth row are transmitted to the capacitor C01_ n, and then the images of the odd columns in the nth row are read out;
s05: the control signal TX02_ n changes to high level so that the optical signals in the photodiodes in the pixel cells of the even columns in the nth row are transmitted to the capacitor C02_ n, and then the images of the even column groups in the nth row are read out;
s06: combining the odd-numbered column images and the even-numbered column images in the nth row into an nth row image;
s07: steps S01-S06 are repeated with a reset exposure readout of all rows in the pixel array resulting in a complete image.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (6)
1. A CMOS image sensor is characterized by comprising a pixel array, A/2 column-level sampling and holding circuits, a column selection coding and driving circuit and a pipeline analog-to-digital converter, wherein the pixel array comprises B rows and A columns of pixel units, the m column of pixel units and the m +1 column of pixel units share one column-level sampling and holding circuit, the A/2 column-level sampling and holding circuits are connected to the column selection coding and driving circuit, and the other end of the column selection coding and driving circuit is connected with the pipeline analog-to-digital converter; wherein A is an even number more than or equal to 2, B is an integer more than or equal to 1, m is an odd number, and m is more than or equal to 1 and is less than A;
resetting and exposing the mth row pixel unit and the m +1 th row pixel unit in the nth row in the pixel array at the same time, and reading out the pixel units in sequence, wherein n is an integer and is more than or equal to 1 and less than or equal to B;
the CMOS image sensor also comprises A/2 column-level readout circuits, wherein the m column of pixel units and the m +1 column of pixel units in the pixel array share one column-level readout circuit;
the pixel unit of the n row and the m column comprises a photodiode PDn,mA transfer control MOS tube MT1_ n, a switch S01_ n and a capacitor C01_ n, wherein the n row and the m +1 column of pixel units comprise a photodiode PDn,m+1The transmission control MOS tube MT2_ n, the switch S02_ n and the capacitor C02_ n, the mth row and mth column pixel units and the nth row and m +1 th row pixel units share the reset MOS tube MR _ n, the amplification MOS tube MF _ n and the row selection MOS tube Mrow _ n, and the specific connection relationship is as follows:
the anode of the photodiode PDn, m is connected to ground, and the cathode is connected to the drain of the transmission control MOS transistor MT1 — n; a source of the transmission control MOS transistor MT1_ n is commonly connected to one end of the capacitor C01_ n and one end of the switch SO1_ n, and a gate of the transmission control MOS transistor MT1_ n is connected to a transmission control signal TX01_ n; the other end of the capacitor C01_ n is connected with the ground level; the other end of the switch S01_ n is commonly connected with the grid electrode of the amplifying MOS tube MF _ n, the source electrode of the resetting MOS tube MR _ n and one end of the switch S02_ n; the positive electrode of the photodiode PDn, m +1 is connected with the ground level, and the negative electrode of the photodiode PDn, m +1 is connected with the drain electrode of the transmission control MOS transistor MT2_ n; a source electrode of the transmission control MOS tube MT2_ n is commonly connected with one end of the capacitor C02_ n and the other end of the switch SO2_ n, and a gate electrode of the transmission control MOS tube MT2_ n is connected with a transmission control signal TX02_ n; the other end of the capacitor C02_ n is connected with the ground level; the other end of the switch S02_ n is commonly connected with the grid electrode of the amplifying MOS tube MF _ n, the source electrode of the resetting MOS tube MR _ n and one end of the switch S01_ n; the grid electrode of the reset MOS tube MR _ n is connected with a reset signal RST _ n, and the drain electrode of the reset MOS tube MR _ n is connected with a power supply anode VDD; the drain electrode of the amplifying MOS tube MF _ n is connected with a power supply anode VDD, the source electrode of the amplifying MOS tube MF _ n is connected with the drain electrode of the row selection MOS tube Mrow _ n, the grid electrode of the row selection MOS tube Mrow _ n is connected with a row selection signal RS _ n, and the source electrode of the row selection MOS tube Mrow _ n is used as a common signal output end of pixel units of the mth row and the (m + 1) th row in the image sensor array.
2. The CMOS image sensor according to claim 1, wherein signal output terminals of each column of pixel cells in the pixel array are connected together.
3. The CMOS image sensor of claim 1, wherein the control signals of odd columns in each row of pixel units in the pixel array are the same, and the control signals of even columns are the same.
4. The CMOS image sensor according to claim 1, wherein said MOS transistors of said pixel unit are all NMOS transistors.
5. The CMOS image sensor of claim 1, wherein the source and drain electrodes of the pixel array are interchangeable.
6. A method of outputting an image using the CMOS image sensor of claim 1, comprising the steps of:
s01: simultaneously closing the switch S01_ n and the switch S02_ n in the pixel unit in the nth row in the pixel array, and simultaneously resetting the pixel unit in the nth row in the pixel array; wherein n is an integer, and n is more than or equal to 1 and less than or equal to B;
s02: opening a switch S02_ n to hold the reset signal of the pixel unit in the even column in the nth row of the pixel array;
s03: exposing the pixel units in the nth row of the pixel array at the same time, wherein the exposed optical signals are stored in the photodiodes;
s04: the control signal TX01_ n changes to high level so that the optical signals in the photodiodes in the pixel units of the odd columns in the nth row are transmitted to the capacitor C01_ n, and then the images of the odd columns in the nth row are read out;
s05: the control signal TX02_ n changes to high level so that the optical signals in the photodiodes in the pixel cells of the even columns in the nth row are transmitted to the capacitor C02_ n, and then the images of the even column groups in the nth row are read out;
s06: combining the odd-numbered column images and the even-numbered column images in the nth row into an nth row image;
s07: steps S01-S06 are repeated with a reset exposure readout of all rows in the pixel array resulting in a complete image.
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| KR20220023821A (en) | 2020-08-21 | 2022-03-02 | 선전 구딕스 테크놀로지 컴퍼니, 리미티드 | Image sensors, fingerprint detection devices and electronic devices |
| CN113676652B (en) * | 2021-08-25 | 2023-05-26 | 维沃移动通信有限公司 | Image sensor, control method, control device, electronic apparatus, and storage medium |
| CN113676651B (en) * | 2021-08-25 | 2023-05-26 | 维沃移动通信有限公司 | Image sensor, control method, control device, electronic apparatus, and storage medium |
| CN117793563A (en) * | 2024-02-23 | 2024-03-29 | 天津希格玛微电子技术有限公司 | Readout device for image sensor |
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| KR101077408B1 (en) * | 2010-02-05 | 2011-10-26 | 서강대학교산학협력단 | CMOS Image Sensor |
| CN101815179B (en) * | 2010-04-15 | 2012-06-20 | 昆山锐芯微电子有限公司 | CMOS (Complementary Metal Oxide Semiconductor) image sensor |
| KR102503213B1 (en) * | 2016-04-05 | 2023-02-23 | 삼성전자 주식회사 | Cds circuit for decreasing settling time and image sensor including the same |
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