JP2011244246A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device having both functions of pixel addition and global electronic shutter.SOLUTION: A solid-state image pickup device 1 includes a pixel array 10 having plurality of pixels PE arrayed in matrix and plurality of column signal lines CL provided in accordance with each line of the pixel array 10. Each pixel of the pixels PE constituting the pixel array 10 includes an imaging part 11; a capacitive element Cs; and a switching part 12. The imaging part 11 outputs voltage depending on a charge amount generated by a photoelectric conversion. The capacitive element Cs is being connected to one end of a reference node GND and being supplied reference voltage from the reference node GND. The switching part 12 switches to a state where the other end of the capacitive element Cs is connected to an output node 13 of the imaging part 11; is connected to the column signal line CL in response; or is not connected to either of the output node 13 or the column signal line CL in response.

Description

  The present invention relates to a solid-state imaging device using a solid element, and more particularly to a CMOS solid-state imaging device using a MOS transistor.

  Solid-state imaging devices are roughly classified into CCD (Charge Coupled Device) solid-state imaging devices and CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging devices. CMOS solid-state imaging devices are characterized by low power consumption compared to CCD solid-state imaging devices, and in recent years, the number of pixels has been increasing. In a CMOS solid-state imaging device having a large number of pixels, when high-speed readout is required as in the case of capturing a moving image, pixel addition for adding signals of adjacent pixels is often performed.

  For example, in a CMOS solid-state imaging device disclosed in Japanese Patent Laying-Open No. 2005-277709 (Patent Document 1), a plurality of capacitive elements are arranged corresponding to each readout signal line, and readout is performed from different rows in the corresponding column. Pixel signals are stored in these capacitive elements. Next, these capacitive elements are short-circuited by switch transistors, and the pixel signals of different rows are averaged. At the same time, the capacitor elements in the adjacent columns are electrically short-circuited by the switch transistor, and a sub-sampling operation (pixel addition) for compressing a maximum of four pixels into one pixel is executed.

  An example of another CMOS solid-state imaging device capable of pixel addition is disclosed in Japanese Patent Laying-Open No. 2008-98834 (Patent Document 2). In the solid-state imaging device of this document, pixel blocks are arranged in a matrix on the light receiving surface. In each pixel block, 16 pixels arranged in 4 rows and 4 columns are arranged. The floating diffusions of four pixels arranged in the vertical direction are connected by a vertical FD connection line. The first and third vertical FD connection lines are connected by the first horizontal FD connection line. The second and fourth vertical FD connection lines are connected by the second horizontal FD connection line. The first and second vertical FD connection lines are connected to the first and second vertical read lines through the amplification transistor and the row selection transistor, respectively.

  One of the technical problems with CMOS solid-state imaging devices is the realization of a global electronic shutter. Unlike a CCD solid-state imaging device, a CMOS solid-state imaging device can easily realize a rolling shutter that sequentially releases a shutter for each scanning line due to its structure and circuit configuration. It has been considered difficult so far.

  Japanese Patent Laying-Open No. 2005-65074 (Patent Document 3) discloses an example of a configuration of a CMOS solid-state imaging device that realizes a global electronic shutter function. The first solid-state imaging device described in this document includes means for performing photoelectric conversion, gate means for transferring signal charges generated by the photoelectric conversion means to the next stage, and storage means for accumulating signal charges from the gate means. And reset means for resetting the signal charge of the storage means, storage means for temporarily storing the signal from the storage means, and means for reducing reset noise based on the reset voltage by the reset means and the voltage stored in the storage means Provided in each pixel. The second solid-state imaging device described in this document includes means for performing photoelectric conversion, gate means for transferring signal charges generated by the photoelectric conversion means to the next stage, and storage means for accumulating signal charges from the gate means. A reset means for resetting the signal charge, a first storage means for storing the voltage at the time of resetting the signal charge, and a second storage means for storing the signal voltage from the photoelectric conversion means. . The voltages stored in the first and second storage means are difference-calculated outside the image array and output as a differential voltage to cancel the reset noise.

JP 2005-277709 A JP 2008-98834 A JP 2005-65074 A

  The above-described pixel addition function and global electronic shutter function are important techniques for capturing a moving image using a CMOS solid-state imaging device, but a CMOS solid-state imaging device that has both functions has not been realized so far.

  An object of the present invention is to provide a solid-state imaging device that has both a pixel addition function and a global electronic shutter function.

  A solid-state imaging device according to an embodiment of the present invention includes a pixel array having a plurality of pixels arranged in a matrix, and a plurality of column signal lines provided corresponding to each column of the pixel array. Prepare. Each of the plurality of pixels constituting the pixel array includes an imaging unit, a first capacitive element, and a first switching unit. The imaging unit outputs a first voltage corresponding to the amount of charge generated by photoelectric conversion. One end of the first capacitive element is connected to a reference node that provides a reference voltage. The first switching unit includes a state in which the other end of the first capacitor is connected to the output node of the imaging unit, a state in which the other end of the first capacitor is connected to the corresponding column signal line, and a first The other end of the capacitive element is switched to one of the states in which the other end of the capacitive element is not connected to both the output node of the imaging unit and the corresponding column signal line.

  According to the solid-state imaging device according to the above embodiment, a voltage corresponding to the generated charge amount can be held in the first capacitor element in each pixel, so that a global electronic shutter can be realized. Furthermore, since the first capacitor elements of a plurality of pixels in the same column can be connected to the corresponding column signal line using the first switching unit, addition reading can be performed.

It is a block diagram which shows the structure of the solid-state imaging device 1 by Embodiment 1 of this invention. It is a circuit diagram which shows the structure of pixel PE (m, n) of the m-th row and the n-th column. FIG. 6 is a timing diagram for explaining the operation of the solid-state imaging device 1 in the all-pixel readout mode. FIG. 6 is a timing diagram for explaining the operation of the solid-state imaging device 1 in the addition reading mode. It is a circuit diagram which shows the structure of the modification of pixel PE (m, n) shown in FIG. It is a circuit diagram which shows the structure of the solid-state imaging device 2 by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the solid-state imaging device 3 by Embodiment 3 of this invention. FIG. 11 is a timing diagram for explaining the operation of the solid-state imaging device 3 in the addition reading mode. It is a block diagram which shows the structure of the semiconductor device for cameras to which the solid-state imaging devices 1-3 of this invention are applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
FIG. 1 is a block diagram showing a configuration of a solid-state imaging device 1 according to Embodiment 1 of the present invention. As shown in FIG. 1, the solid-state imaging device 1 includes a pixel array 10 in which a plurality of pixels PE are arranged in a matrix. In FIG. 1, the X direction is the row direction (horizontal direction), and the Y direction is the column direction (vertical direction). The pixel in the m-th row and the n-th column is described as a pixel PE (m, n). Although the pixel array 10 includes a large number of pixels PE, FIG. 1 shows two rows and four columns of pixels PE for ease of illustration.

  The solid-state imaging device 1 further includes column signal lines (vertical signal lines) CL (CL (1), CL (2),...) Provided individually corresponding to the respective columns of the pixel array 10, and for each row. And six row signal lines (horizontal signal lines) provided by six. The column signal line CL is used when reading the output signal of each pixel PE. Each column signal line CL has a parasitic capacitance Cv (vertical signal line capacitance) with the ground node GND (generically referred to as a capacitance 24). Control signals φTX, φRST, φSWdi, φSWsi, φSWdo, φSWso are applied to the row signal lines provided in each row. The control signals φTX, φRST, φSWdi, φSWsi are common signals in each row, and the control signals φSWdo, φSWso are separate signals in each row. Hereinafter, the control signals φSWdo and φSWso in the m-th row are referred to as φSWdo (m) and φSWso (m).

  The solid-state imaging device 1 further includes a precharge unit 25, a switching unit 30, a column amplifier CAMP and an analog / digital (A / D) converter ADC provided corresponding to each column signal line CL, and a control unit. 20 and so on.

  The precharge unit 25 supplies a control signal φPRE to a MOS (Metal Oxide Semiconductor) transistor (referred to as a precharge transistor Tpre) having a source electrode connected to each column signal line CL and a gate electrode of the precharge transistor Tpre. Signal line. A precharge voltage Vpre is supplied to the drain electrode of each precharge transistor Tpre. Each column signal line CL is precharged to a predetermined precharge voltage Vpre via a corresponding precharge transistor Tpre before reading an image signal from each pixel PE.

  The switching unit 30 includes a plurality of switch transistors Tadd, Tline configured by MOS transistors, and three row signal lines for supplying control signals φADD, φLINE1, and φLINE2.

  As shown in FIG. 1, the first switch transistor Tadd is connected to the first column signal line CL (1) and the second column signal line CL (2). Similarly, the i-th (where i is an integer equal to or greater than 1) switch transistor Tadd includes the column signal line CL (2i−1) of the 2i−1th column and the column signal line CL (2i of the 2ith column). ) (Where i is an integer of 1 or more). That is, in the case of FIG. 1, a group is constituted by two column signal lines, ie, the column signal line CL (2i-1) of the 2i-1th column and the column signal line CL (i) of the 2ith column. The column signal lines CL in each group are connected to each other by the switch transistor Tadd. A control signal φADD is supplied to the gate electrode of each switch transistor Tadd.

  The switch transistor Tline is inserted in each column signal line CL. Each switch transistor Tline is provided between an input node of a column amplifier CAMP provided on the corresponding column signal line CL and a connection node connecting the corresponding column signal line CL and the switch transistor Tadd. A control signal φLINE1 is supplied to the gate electrode of the switch transistor Tline inserted in the column signal lines CL (1), CL (3),... In the odd columns, and the column signal lines CL (2), CL (4 in the even columns. The control signal φLINE2 is supplied to the gate electrode of the switch transistor Tline inserted in),. As will be described with reference to FIGS. 3 and 4, the switching unit 30 is provided to perform addition reading for a plurality of pixels provided in different columns.

  The column amplifier CAMP receives a signal output from each pixel PE connected to the corresponding column signal line CL. As illustrated in FIG. 2, each pixel PE has a signal (referred to as an optical signal) corresponding to the amount of electric charge generated by photoelectric conversion, and a signal (dark signal and signal) when the electric charge generated by photoelectric conversion is reset. Output). The column amplifier CAMP samples and holds these optical signals and dark signals, and amplifies and outputs a difference signal between the optical signals and the dark signals. An operation for obtaining an image signal based on a difference between an optical signal and a dark signal is called a CDS (Correlated Double Sampling) operation.

  The A / D converter ADC digitally converts the output of the corresponding column amplifier CAMP and outputs a digital bit string.

  The control unit 20 includes a vertical scanning circuit 22 and a control logic circuit 21. The vertical scanning circuit 22 includes a signal generation circuit 23 and buffer circuits B <b> 1 to B <b> 6 provided corresponding to the row signal lines of each row of the pixel array 10. The signal generation circuit 23 outputs the control signals φTX, φRST, φSWdi, φSWsi, φSWdo, φSWso based on the command of the control logic circuit 21. The output control signals φTX, φRST, φSWdi, φSWsi, φSWdo, φSWso are amplified by the buffer circuits B1 to B6 for each row and supplied to each row signal line.

  The control logic circuit 21 controls the signal generation circuit 23 and generates control signals φPRE, φADD, φLINE1, and φLINE2 to be supplied to the precharge unit 25 and the switching unit 30. The control logic circuit 21 further receives a digital bit string output from the A / D converter ADC provided corresponding to each column signal line CL, and outputs the digital bit string to the outside of the solid-state imaging device 1.

  FIG. 2 is a circuit diagram showing a configuration of the pixel PE (m, n) in the m-th row and the n-th column. Since all of the pixels PE constituting the pixel array 10 of FIG. 1 have the same configuration, FIG. 2 shows the configuration of the pixel PE (m, n) as a representative. As illustrated in FIG. 2, the pixel PE (m, n) includes an imaging unit 11, a switching unit 12, and capacitive elements Cd and Cs.

  The imaging unit 11 is configured by a semiconductor element such as a MOS transistor. Specifically, the imaging unit 11 includes a photodiode PD, a transfer transistor TX, a floating diffusion FD, an amplification transistor AMI, a reset transistor RST, and a current source ISS.

  The photodiode PD generates a charge corresponding to the amount of received light by photoelectric conversion. Instead of the photodiode, another photoelectric conversion element such as a phototransistor may be used. The transfer transistor TX is connected between the cathode of the photodiode PD and the floating diffusion FD. The transfer transistor TX transfers the charge generated by the photodiode PD to the floating diffusion FD in response to the control signal φTX supplied to the gate electrode. The floating diffusion FD is a high-concentration impurity region formed on the semiconductor substrate, is in an electrically floating state, and accumulates the charge transferred from the transfer transistor TX. The potential of the floating diffusion FD is determined according to the amount of accumulated charge. The amplification transistor AMI has a drain electrode connected to the power supply node VCC, a gate electrode connected to the floating diffusion FD, and a source electrode connected to the current source ISS as the output node 13 of the imaging unit 11. Since the source follower is configured by the amplification transistor AMI, a voltage corresponding to the potential of the floating diffusion FD is generated at the source electrode (output node 13) of the amplification transistor AMI. Reset transistor RST is connected between power supply node VCC and floating diffusion FD. The reset transistor RST resets the voltage of the floating diffusion FD by depleting the floating diffusion FD in response to the control signal φRST supplied to its gate electrode.

  The switching unit 12 includes switch transistors SWdi, SWsi, SWdi, SWdo configured by MOS transistors. The switch transistors SWdi and SWdo are connected in series between the output node 13 of the imaging unit 11 and the corresponding column signal line CL (n) in this order. Capacitance element Cd is provided between connection node 14 of switch transistors SWdi and SWdo and ground node GND. A control signal φSWdi is supplied to the gate electrode of the switch transistor SWdi, and a control signal φSWdo (m) is supplied to the gate electrode of the switch transistor SWdo. The switch transistors SWsi and SWso are connected in series between the output node 13 of the imaging unit 11 and the corresponding column signal line CL (n) in this order. Capacitance element Cs is provided between connection node 15 of switch transistors SWsi and SWso and ground node GND. A control signal φSWsi is supplied to the gate electrode of the switch transistor SWsi, and a control signal φSWso (m) is supplied to the gate electrode of the switch transistor SWso.

  The capacitive elements Cd and Cs are provided to hold the dark signal and the optical signal output from the imaging unit 11, respectively. When the dark signal is held in the capacitive element Cd, the voltage of the floating diffusion FD is reset by the reset transistor RST, and then the switch transistor SWdi is turned on. As a result, the output voltage of the amplification transistor AMI and the voltage of the capacitive element Cd at the time of reset can be made equal. In the case where the optical signal is held in the capacitor element Cs, the charge generated in the photodiode PD by the transfer transistor TX is transferred to the floating diffusion FD, and then the switch transistor SWsi is turned on. As a result, the output voltage of the amplification transistor AMI and the voltage of the capacitive element Cs according to the amount of charge generated by photoelectric conversion can be made equal. Since the above operations can be performed in parallel on each pixel PE, a global electronic shutter is realized.

  The structures of the capacitive elements Cd and Cs are not particularly limited. For example, a double polycapacitor structure in which an oxide film is sandwiched between two polysilicon layers or a metal-metal capacitor structure in which an insulating layer is sandwiched between two metal layers may be used. . Alternatively, the space between the gate electrode of the MOS transistor and the diffusion layer may be used as a capacitor.

  The conventional general CMOS solid-state imaging device is not provided with the capacitive elements Cd and Cs. Even in the conventional configuration, it is possible to hold the charge in the floating diffusion FD for a short time. For example, in order to take a moving image of 16 frames per second, the charge is stored in the floating diffusion FD for 1/16 second. If it tries to hold, noise such as leakage current will increase. Therefore, it has been considered difficult to realize a global electronic shutter with a conventional CMOS solid-state imaging device. In the solid-state imaging device 1 according to the first embodiment, a global electronic shutter can be realized by providing each pixel with capacitive elements Cd and Cs that hold a dark signal and an optical signal.

  On the other hand, in the pixel PE (m, n) of FIG. 2, when the dark signal held in the capacitive element Cd is read, the switch transistor SWdo is turned on by activating the control signal φSWdo (m) to a high level. To. When reading the optical signal held in the capacitive element Cs, the switch transistor SWso is turned on by activating the control signal φSWso (m) to a high level. As described with reference to FIGS. 3 and 4, by simultaneously turning on a predetermined number of switch transistors SWdo in the same column, the dark signals held in the capacitor Cd can be added and read. Similarly, by simultaneously turning on a predetermined number of switch transistors SWso in pixels in the same column, the optical signals held in the capacitor Cs can be added and read out.

  Next, the operation of the solid-state imaging device 1 will be described with reference to the timing charts of FIGS. The solid-state imaging device 1 has an all-pixel readout mode and an addition readout mode as operation modes. In the all-pixel reading mode, the dark signal and the optical signal held in the capacitive elements Cd and Cs of each pixel are individually read for each row. In the addition reading mode, the dark signal and the optical signal held in the capacitive elements Cd and Cs of each pixel are added and read for each predetermined number of pixels. In the case of the solid-state imaging device 1 of FIG. 1, addition reading is performed on a total of four pixels, two in the row direction and two (2 × 2) in the column direction.

  FIG. 3 is a timing diagram for explaining the operation of the solid-state imaging device 1 in the all-pixel readout mode. FIG. 3 shows the pulse waveforms of the control signals φRST, φTX, φSWdi, φSWsi, φSWdo (1), φSWso (1), φSWdo (2), φSWso (2) output from the vertical scanning circuit 22 of FIG. The pulse waveforms of control signals φPRE, φADD, φLINE1, and φLINE2 supplied to horizontal signal lines provided in precharge unit 25 and switching unit 30 are shown. For the control signals φSWdo and φSWso, only the signals in the first and second rows are shown.

  In the all-pixel readout mode, the control signal φADD is always at the low (L) level (inactive state), and the control signals φLINE1 and φLINE2 are always at the high (H) level (active state). As a result, the switch transistor Tadd of the switching unit 30 is turned off, and the switch transistor Tline is turned on.

  1 to 3, the control signals φRST and φTX output from the vertical scanning circuit 22 become high level (active state) between time t10 and time t20 in FIG. 3 (during this time, the vertical scanning circuit 22 All other control signals output from are at a low level (inactive state). Thereby, in each pixel PE constituting the pixel array 10, the transfer transistor TX and the reset transistor RST are turned on, so that the charge generated in the photodiode PD and the charge accumulated in the floating diffusion FD are reset.

  At the next time t20, the control signals φRST and φTX become low level. Since all the control signals output from the vertical scanning circuit 22 are at the low level from the time t20 to the time t30, the transistors TX, RST, SWdi, SWsi, SWdo, SWso constituting the imaging unit 11 are included in each pixel. Turns off. As a result, charges corresponding to the amount of received light are generated and stored in the photodiode PD by photoelectric conversion.

  During the next time t30 to time t31, the control signal φRST is activated, whereby the reset transistor RST is turned on in each pixel. During the subsequent time t31 to time t32, the control signal φSWdi is activated, whereby the switch transistor SWdi is turned on in each pixel. As a result, the output voltage (dark signal) of the amplification transistor AMI corresponding to the potential of the floating diffusion FD in the reset state is held in the capacitive element Cd.

  During the next time t32 to time t33, the transfer signal TX is turned on by activating the control signal φTX. As a result, the charge generated and accumulated by the photodiode PD after time t20 is transferred to the floating diffusion FD. During the subsequent time t33 to time t34, the control signal φSWsi is activated, so that the switch transistor SWsi is turned on in each pixel. As a result, the output voltage (optical signal) of the amplification transistor AMI corresponding to the amount of charge accumulated in the floating diffusion FD is held in the capacitive element Cs. Since the operations from time t30 to time t34 are simultaneously executed in each pixel, the global electronic shutter is executed.

  Between the next time t40 and time t50, the dark signal and the optical signal of each pixel in the first row of the pixel array 10 are read out. First, when the control signal φPRE is activated between time t41 and time t42, each precharge transistor Tpre of the precharge unit 25 is turned on. As a result, the capacitance Cv of each column signal line CL is precharged to a predetermined precharge voltage Vpre.

  The control signal φSWdo (1) is activated between the next time t42 and time t43, whereby the switch transistor SWdo is turned on in each pixel in the first row of the pixel array 10. As a result, the voltage of each column signal line CL changes according to the voltage (dark signal) held in the capacitive element Cd of each pixel in the first row. The voltage of each column signal line CL after the change is sampled and held by each column amplifier CAMP.

  When the control signal φPRE is activated between the next time t43 and time t44, each precharge transistor Tpre of the precharge unit 25 is turned on. As a result, the capacitance Cv of each column signal line CL is precharged to a predetermined precharge voltage Vpre.

  When the control signal φSWso (1) is activated between the next time t44 and time t45, the switch transistor SWso is turned on in each pixel in the first row of the pixel array 10. As a result, the voltage of each column signal line CL changes according to the voltage (optical signal) held in the capacitive element Cs of each pixel in the first row. The voltage of each column signal line CL after the change is sampled and held by each column amplifier CAMP. Each column amplifier CAMP amplifies and outputs the difference between the voltage corresponding to the sampled and held optical signal and the voltage corresponding to the dark signal. Each A / D converter ADC digitally converts the output of the corresponding column amplifier CAMP and outputs it to the control logic circuit 21. Thus, reading of the image signal generated at each pixel in the first row is completed.

  Between the next time t50 and time t60, the dark signal and the optical signal of each pixel are read out to the second row of the pixel array 10. Since this reading operation is the same as the reading operation of the image signal in the first row, it will be briefly described below. First, the control signal φPRE is activated between time t51 and time t52, whereby each column signal line CL is precharged to a predetermined precharge voltage Vpre. When the control signal φSWdo (2) is activated between the next time t52 and time t53, the dark signal held in the capacitive element Cd of each pixel in the second row is read, and the column of each column Sampled and held by an amplifier CAMP. The control signal φPRE is activated between the next time t53 and time t54, whereby each column signal line CL is precharged to a predetermined precharge voltage Vpre. When the control signal φSWso (2) is activated between the next times t54 and t55, the optical signal held in the capacitor element Cs of each pixel in the second row is read, and the column amplifier of each column Sampled and held by CAMP. Each column amplifier CAMP amplifies and outputs the difference between the voltage corresponding to the sampled and held optical signal and the voltage corresponding to the dark signal. Each A / D converter ADC digitally converts the output of the corresponding column amplifier CAMP and outputs it to the control logic circuit 21.

  Thus, reading of the image signal generated at each pixel in the second row is completed. By repeating the above operation from the third row to the last row, the reading of the image signal generated in each pixel of the pixel array 10 is completed.

  FIG. 4 is a timing chart for explaining the operation of the solid-state imaging device 1 in the addition reading mode. FIG. 4 shows the pulse waveforms of the control signals φRST, φTX, φSWdi, φSWsi, φSWdo (1), φSWso (1), φSWdo (2), and φSWso (2) output from the vertical scanning circuit 22 of FIG. The pulse waveforms of control signals φPRE, φADD, φLINE1, and φLINE2 supplied to horizontal signal lines provided in precharge unit 25 and switching unit 30 are shown. For the control signals φSWdo and φSWso, only the signals in the first and second rows are shown.

  In the addition reading mode, the control signal φADD is always at a high (H) level, the control signal φLINE1 is always at a high (H) level, and φLINE2 is always at a low (L) level. As a result, the switch transistor Tadd of the switching unit 30 is turned on, the odd-numbered switch transistors Tline are turned on, and the even-numbered switch transistors Tline are turned off.

  1, 2, and 4, the period from time t <b> 10 to time t <b> 40 in FIG. 4 is the same as that in FIG. 3, and therefore description thereof is not repeated. At time t40, a dark signal is held in the capacitive element Cd of each pixel constituting the pixel array 10, and an optical signal is held in the capacitive element Cs.

  Between the next time t40 and time t50, the dark signal and the optical signal generated in each pixel in the first row and the second row of the pixel array 10 are added to each four and read out. First, when the control signal φPRE is activated between time t41 and time t42, each precharge transistor Tpre of the precharge unit 25 is turned on. As a result, the capacitance Cv of each column signal line CL is precharged to a predetermined precharge voltage Vpre.

  The control signals φSWdo (1) and φSWdo (2) are activated between the next time t42 and time t43, so that the switch transistors SWdo in each pixel in the first row and the second row of the pixel array 10 are activated. Turns on. At this time, the column signal line CL (1) of the first column and the column signal line CL (2) of the second column are in a conductive state via the switch transistor Tadd in the on state. The voltages of the column signal lines CL (1) and CL (2) of the eyes are the four pixels PE (1,1), PE (1,2), PE (2,1), PE (2,2). The voltage is obtained by averaging each dark signal. The averaged voltage is sampled and held by the column amplifier CAMP in the first column (since the switch transistor Tline in the second column is in the off state, the column amplifier CAMP in the second column is not used). Similarly, the switch signal Tadd in which the column signal line CL (2i-1) in the 2i-1th column and the column signal line CL (2i) in the 2ith column (where i is an integer equal to or greater than 1) are turned on. Therefore, the voltages of the column signal lines CL (2i-1) and CL (2i) of the 2i-1th column and the 2ith column are four pixels PE (1,2i-1). , PE (1,2i), PE (2,2i-1), and PE (2,2i) are averaged voltages. The averaged voltage is sampled and held by the column amplifier CAMP in the (2i-1) th column.

  When the control signal φPRE is activated between the next time t43 and time t44, each precharge transistor Tpre of the precharge unit 25 is turned on. As a result, the capacitance Cv of each column signal line CL is precharged to a predetermined precharge voltage Vpre.

  When the control signals φSWso (1) and φSWso (2) are activated between the next time t44 and time t45, the switch transistors SWso in each pixel in the first row and the second row of the pixel array 10 are activated. Turns on. At this time, the column signal line CL (1) of the first column and the column signal line CL (2) of the second column are in a conductive state via the switch transistor Tadd in the on state. The voltages of the column signal lines CL (1) and CL (2) of the eyes are the four pixels PE (1,1), PE (1,2), PE (2,1), PE (2,2). The voltage is obtained by averaging each optical signal. This averaged voltage is sampled and held by the column amplifier CAMP in the first column. Similarly, the switch signal Tadd in which the column signal line CL (2i-1) in the 2i-1th column and the column signal line CL (2i) in the 2ith column (where i is an integer equal to or greater than 1) are turned on. Therefore, the voltages of the column signal lines CL (2i-1) and CL (2i) of the 2i-1th column and the 2ith column are four pixels PE (1,2i-1). , PE (1,2i), PE (2,2i-1), and PE (2,2i) are averaged voltages. The averaged voltage is sampled and held by the column amplifier CAMP in the (2i-1) th column.

  Each column amplifier CAMP in the odd-numbered column amplifies and outputs the difference between the voltage corresponding to the sampled and held optical signal and the voltage corresponding to the dark signal. Each A / D converter ADC in the odd column digitally converts the output of the corresponding column amplifier CAMP and outputs the result. Thus, the addition reading of the image signals generated by the pixels in the first row and the second row is completed. Similarly, for the third and subsequent rows, the pixels in the 2j-1th row and the 2jth row (where j is an integer of 2 or more) are added and read every two columns. Thus, the addition reading of the pixel array 10 is completed.

  FIG. 5 is a circuit diagram showing a configuration of a modification of the pixel PE (m, n) shown in FIG. In the pixel PEA (m, n) of FIG. 5, the configuration of the switching unit 16 is different from that of the switching unit 12 of FIG. As shown in FIG. 5, the switching unit 16 includes switch transistors SWi, SWo, SWd, and SWs configured by MOS transistors. The switch transistors SWi and SWo are connected in series between the output node 13 of the imaging unit 11 and the corresponding column signal line CL (n) in this order. The switch transistor SWd is connected between the connection node 17 of the switch transistors SWi and SWo and the first terminal of the capacitive element Cd. The second terminal of the capacitive element Cd is connected to the ground node GND. Further, the switch transistor SWs is connected between the connection node 17 and the first terminal of the capacitive element Cs. The second terminal of the capacitive element Cs is connected to the ground node GND. Control signals φSWi, φSWd, φSWs, and φSWo (m) are supplied to the control electrodes of the switch transistors SWi, SWd, SWs, and SWo by four row signal lines provided for each column of the pixel array 10. . The control signals φSWi, φSWd, and φSWs are signals common to each row, and φSWo (m) is a separate signal for each row.

  When holding the dark signal in the capacitive element Cd, the reset transistors RST reset the voltage of the floating diffusion FD, and then activate the control signals φSWi and φSWd to turn on the switch transistors SWi and SWd. When the optical signal is held in the capacitive element Cs, the charges generated in the photodiode PD by the transfer transistor TX are transferred to the floating diffusion FD, and the switch transistors SWi and SWs are activated by activating the control signals φSWi and φSWs. Turn on. When reading the dark signal held in the capacitive element Cd, the switch transistors SWd and SWo are turned on by activating the control signals φSWd and φSWo (m). When reading the optical signal held in the capacitive element Cs, the switch transistors SWs and SWo are turned on by activating the control signals φSWs and φSWo (m). Since the other points of FIG. 5 are the same as those of FIG. 2, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  The configuration of the switching units 12 and 16 provided in each pixel PE is not limited to the case shown in FIGS. The state in which the first terminals of the capacitive elements Cd and Cs are connected to the output node 13 of the imaging unit 11, the state in which the first terminals are connected to the corresponding column signal line CL, and the respective first terminals correspond to the output node 13 and the corresponding node. The configuration of the switching unit may be any configuration as long as it can be switched to any one of the states not connected to both the column signal lines CL.

  As described above, according to the solid-state imaging device 1 of the first embodiment, a global electronic shutter can be realized by providing the capacitive elements Cd and Cs in each pixel PE. Furthermore, by providing the switching element 12 or 16 for switching the connection between the capacitive elements Cd and Cs in each pixel PE, pixel addition can be performed for a predetermined number of pixels provided in the same column. Furthermore, by providing the switching unit 30 that electrically connects a predetermined number of column signal lines CL to each other, pixel addition can be performed for a predetermined number of pixels provided in different columns.

<Embodiment 2>
FIG. 6 is a circuit diagram showing a configuration of a solid-state imaging device 2 according to Embodiment 2 of the present invention. The solid-state imaging device 2 in FIG. 6 is different from the solid-state imaging device 1 in FIG. 1 in that a switching unit 31 is included instead of the switching unit 30 in FIG. Furthermore, the control signal supplied to the switching unit 31 in FIG. 6 is different from the control signal supplied to the switching unit 30 in FIG. Since the solid-state imaging device 2 of FIG. 6 is the same as the solid-state imaging device 1 of FIG. 1 in other points, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  When the number of column signal lines CL is N, the switching unit 31 illustrated in FIG. 6 includes N−1 switch transistors Tadd1, Tadd2,..., TaddN−1 and N switch transistors Tline1, Tline2,. Including TlineN. The first switch transistor Tadd1 is connected to the first column signal line CL (1) and the second column signal line CL (2). Similarly, the p-th (p is an integer between 1 and N−1) switch transistors Taddp are connected to the p-th column signal line CL (p) and the p + 1-th column signal line CL (p + 1). Connected. Control signals φADD1 to φADDN-1 are supplied to the gate electrodes of the switch transistors Tadd1 to TaddN−1 via row signal lines, respectively.

  The switch transistors Tline1 to TlineN are inserted into the column signal lines CL (1) to CL (N), respectively. Each switch transistor Tline is provided between an input node of a column amplifier CAMP provided on the corresponding column signal line CL and a connection node connecting the corresponding column signal line CL and the switch transistor Tadd. Control signals φLINE1 to φLINEN are supplied to the gate electrodes of the switch transistors Tline1 to TlineN, respectively.

  According to the above configuration, the number of pixels in the row direction when performing pixel addition can be changed. For example, when averaging image signals for two columns as in the case of pixel addition for four pixels PE in two rows and two columns, odd-numbered switch transistors Tadd1, Tadd3,. The even-numbered switch transistors Tadd2, Tadd4,... Are turned off. Further, the switch transistors Tline1, Tline3,... Provided in the odd-numbered column signal lines CL are turned on, and the switch transistors Tline2, Tline4,. As for the switch transistor Tline, conversely, the switch transistors Tlin1, Tline3,... Provided in the odd-numbered column signal lines CL are turned off, and the switch transistors provided in the even-numbered column signal lines CL are turned on. Also good.

  The first, second, fourth, fifth, seventh, eighth,... Switch is used when averaging three columns of image signals as in the case of pixel addition for nine pixels PE in three rows and three columns. The transistor Tadd is turned on, and the third, sixth, ninth,..., Transistors are turned off. Further, the first, fourth, seventh,... Switch transistors Tline are turned on, and the other switch transistors Tline are turned off.

<Embodiment 3>
In Embodiment 3, an example of a color imaging solid-state imaging device will be described.

  FIG. 7 is a circuit diagram showing a configuration of a solid-state imaging device 3 according to Embodiment 3 of the present invention. In the solid-state imaging device 3 of FIG. 7, the configuration of the pixel array 10A, the control signal supplied to the pixel array 10A, the configuration of the switching unit 32, and the control signal supplied to the switching unit 32 are the same as those of the solid-state imaging device 1 of FIG. Different.

  The pixel array 10A is different from the pixel array 10 of FIG. 1 in that it further includes a color filter formed on the light receiving surface of each pixel PE. In the case of FIG. 7, the arrangement of the color filters is a Bayer system. That is, red filters (R) and green filters (Gr) are alternately arranged in odd rows of the pixel array 10A, and green filters (Gb) and blue filters (B) are alternately arranged in even rows. . The circuit configuration of each pixel PE is the same as in FIG.

  Each row of the pixel array 10A is provided with four row signal lines for supplying control signals φRST, φTX, φSWdi, and φSWdo. Control signals φRST, φTX, φSWdi, and φSWdo are common to each row. Since this point is the same as that in FIG. 1, the illustration is omitted in FIG.

  In the odd-numbered rows of the pixel array 10A, four row signal lines for supplying control signals φSWdo_r, φSWso_r, φSWdo_gr, and φSWso_gr are further provided. Signal lines for supplying the control signals φSWdo_r and φSWso_r are connected to the gate electrodes of the switch transistors SWdo and SWso of the pixel PE provided with the red filter (R), respectively. Signal lines for supplying the control signals φSWdo_gr and φSWso_gr are connected to the gate electrodes of the switch transistors SWdo and SWso of the pixel PE provided with the green filter (Gr), respectively. In the even-numbered rows of the pixel array 10A, four row signal lines for supplying control signals φSWdo_b, φSWso_b, φSWdo_gb, and φSWso_gb are further provided. The signal lines for supplying the control signals φSWdo_b and φSWso_b are respectively connected to the gate electrodes of the switch transistors SWdo and SWso of the pixel PE provided with the blue filter (B). The signal lines for supplying the control signals φSWdo_gb and φSWso_gb are connected to the gate electrodes of the switch transistors SWdo and SWso of the pixel PE provided with the green filter (Gb), respectively. Since these control signals differ from column to column, they are distinguished by adding (row number) after the signal name as shown in FIG.

  The switching unit 32 includes a plurality of switch transistors Tadd, Tline configured by MOS transistors, and four row signal lines for supplying control signals φADD1, φADD2, φLINE1, and φLINE2.

  As shown in FIG. 7, the first switch transistor Tadd is connected to the first column signal line CL (1) and the third column signal line CL (3). The second switch transistor Tadd is connected to the second column signal line CL (2) and the fourth column signal line CL (4). Similarly, the 2i-1th (i is an integer greater than or equal to 1) switch transistor Tadd includes the column signal line CL (4i-3) of the 4i-3th column and the column signal line CL of the 4i-1th column. (4i-1). The 2i-th (i is an integer greater than or equal to 1) switch transistor Tadd is connected to the column signal line CL (4i-2) of the 4i-2th column and the column signal line CL (4i) of the 4ith column. The A control signal φADD1 is supplied to the gate electrode of the odd-numbered (2i−1) -th switch transistor Tadd. A control signal φADD2 is supplied to the gate electrode of the even-numbered (2i-th) switch transistor Tadd.

  The switch transistor Tline is inserted in each column signal line CL. Each switch transistor Tline is provided between an input node of a column amplifier CAMP provided on the corresponding column signal line CL and a connection node connecting the corresponding column signal line CL and the switch transistor Tadd. A control signal φLINE1 is supplied to the switch transistor Tline provided in the first and second column signal lines CL (1) and CL (2). A control signal φLINE2 is supplied to the gate electrode of the switch transistor Tline provided in the third and fourth column signal lines CL (3) and CL (4). Similarly, the gate electrode of the switch transistor Tline provided in the column signal lines CL (4i-3) and CL (4i-2) in the 4i-3th and 4i-2th columns (i is an integer of 1 or more). Is supplied with a control signal φLINE1. The control signal φLINE2 is supplied to the gate electrode of the switch transistor Tline provided in the column signal lines CL (4i-1) and CL (4i) of the 4i-1th and 4ith columns (i is an integer of 1 or more). Is done.

  Next, the operation of the solid-state imaging device 3 will be described. The solid-state imaging device 3 has an all-pixel readout mode and an addition readout mode as operation modes.

  In the all-pixel readout mode, the control signals φADD1 and φADD2 are always at the low (L) level (inactive state), and the control signals φLINE1 and φLINE2 are always at the high (H) level (active state). As a result, the switch transistor Tadd of the switching unit 30 is turned off, and the switch transistor Tline is turned on. Since the operation of the solid-state imaging device 3 in the all-pixel readout mode is the same as that in the case of FIG. 3, the description will not be repeated. However, as for the control signals φSWdo and φSWso of FIG. 3, in the case of the solid-state imaging device 3, different control signals are used for each color of the color filter.

  On the other hand, in the addition reading mode, signals of four pixels for two rows and two columns are added for each color of the color filter.

  FIG. 8 is a timing chart for explaining the operation of the solid-state imaging device 3 in the addition reading mode. FIG. 8 shows control signals φRST, φTX, φSWdi, φSWsi, φSWdo_gr (1), φSWso_gr (1), φSWdo_r (1), φSWso_r (1), φSWdo_gb (2) output from the vertical scanning circuit 22 of FIG. , ΦSWso_gb (2), φSWdo_b (2), φSWso_b (2), φSWdo_gr (3), φSWso_gr (3), φSWdo_r (3), φSWso_r (3), φSWdo_gb (4), φSWso_gb (4), φSWso_gb (4), φSWso_gb (4) , ΦSWso_b (4), and pulse waveforms of control signals φPRE, φADD1, φADD2, φLINE1, and φLINE2 supplied to horizontal signal lines provided in the precharge unit 25 and the switching unit 32 are shown. For the control signals φSWdo_gr, φSWso_gr, φSWdo_r, and φSWso_r, only the signals in the first and third rows are shown, and for the control signals φSWdo_gb, φSWso_gb, φSWdo_b, and φSWso_b, only the signals in the second and fourth rows. It is shown.

  In the addition reading mode, the control signals φADD1 and φADD2 are always at a high (H) level, the control signal φLINE1 is always at a high (H) level, and φLINE2 is always at a low (L) level. As a result, the switch transistors Tadd1 and Tadd2 of the switching unit 32 are turned on, and the switch transistors Tline in the 4i-3rd column and the 4i-2th column (i is an integer equal to or greater than 1) are turned on. The switch transistors Tline in the 4i-1th column and the 4ith column are turned off.

  2, 7, and 8, the period from time t <b> 10 to time t <b> 40 in FIG. 8 is the same as that in FIG. 3, and therefore description thereof will not be repeated. At time t40, a dark signal is held in the capacitive element Cd of each pixel PE constituting the pixel array 10A, and an optical signal is held in the capacitive element Cs.

  Between the next time t40 and time t50, the light signal and the dark signal generated in each pixel in the first and third rows of the pixel array 10A are converted into four pixels PE provided with a red filter (R). And each four pixels PE provided with a green filter (Gr) are added and read. First, when the control signal φPRE is activated between time t41 and time t42, each precharge transistor Tpre of the precharge unit 25 is turned on. As a result, the capacitance Cv of each column signal line CL is precharged to a predetermined precharge voltage Vpre.

  The control signals φSWdo_gr (1), φSWdo_r (1), φSWdo_gr (3), and φSWdo_r (3) are activated between the next time t42 and time t43, so that the first and third rows of the pixel array 10A are activated. In each pixel in the row, the switch transistor SWdo is turned on. At this time, the column signal line CL (1) of the first column and the column signal line CL (3) of the third column are in a conductive state via the switch transistor Tadd in the on state. The voltages of the column signal lines CL (1) and CL (3) of the columns are the four pixels PE (1,1), PE (1,3), PE (3,3) provided with the red filter (R). 1) A voltage obtained by averaging the dark signals of PE (3, 3). This averaged voltage is sampled and held by the column amplifier CAMP in the first column (since the switch transistor Tline in the third column is in the off state, the column amplifier CAMP in the third column is not used). . Since the column signal line CL (2) of the second column and the column signal line CL (4) of the fourth column are in a conductive state via the on-state switch transistor Tadd, the second and fourth columns The voltages of the column signal lines CL (2) and CL (4) are the four pixels PE (1,2), PE (1,4), PE (3,2) provided with the green filter (Gr), The voltage is obtained by averaging the dark signals of PE (3, 4). This averaged voltage is sampled and held by the column amplifier CAMP in the second column (since the switch transistor Tline in the fourth column is in the off state, the column amplifier CAMP in the fourth column is not used). .

  Similarly, the column signal line CL (4i-3) in the 4i-3rd column and the column signal line CL (4i-1) in the 4i-1th column (where i is an integer equal to or greater than 1) are in the ON state. Therefore, the voltages of the column signal lines CL (4i-3) and CL (4i-1) of the 4i-3th column and the 4i-1th column are red filter ( The dark signals of the four pixels PE (1, 4i-3), PE (1, 4i-1), PE (3, 4i-3), and PE (3, 4i-1) provided with R) are provided. It becomes the averaged voltage. The averaged voltage is sampled and held by the column amplifier CAMP in the 4i-3rd column. The column signal line CL (4i-2) of the 4i-2th column and the column signal line CL (4i) of the 4ith column (where i is an integer equal to or greater than 1) are connected via the switch transistor Tadd. Since it is in the conductive state, the voltages of the column signal lines CL (4i-2) and CL (4i) of the 4i-2th column and the 4ith column are the four pixels PE provided with the green filter (Gr). This is a voltage obtained by averaging the dark signals of (1, 4i-2), PE (1, 4i), PE (3,4 i-2), and PE (3, 4i). The averaged voltage is sampled and held by the column amplifier CAMP in the 4i-2th column.

  When the control signal φPRE is activated between the next time t43 and time t44, each precharge transistor Tpre of the precharge unit 25 is turned on. As a result, the capacitance Cv of each column signal line CL is precharged to a predetermined precharge voltage Vpre.

  The control signals φSWso_gr (1), φSWso_r (1), φSWso_gr (3), and φSWso_r (3) are activated between the next time t44 and time t45, so that the first and third rows of the pixel array 10A are activated. In each pixel in the row, the switch transistor SWso is turned on. At this time, the column signal line CL (4i-3) in the 4i-3th column and the column signal line CL (4i-1) in the 4i-1th column (where i is an integer equal to or greater than 1) are on. Therefore, the voltages of the column signal lines CL (4i-3) and CL (4i-1) of the 4i-3th column and the 4i-1th column are red filter ( The optical signals of the four pixels PE (1, 4i-3), PE (1, 4i-1), PE (3, 4i-3), and PE (3, 4i-1) provided with R) are provided. It becomes the averaged voltage. The averaged voltage is sampled and held by the column amplifier CAMP in the 4i-3rd column. The column signal line CL (4i-2) of the 4i-2th column and the column signal line CL (4i) of the 4ith column (where i is an integer equal to or greater than 1) are connected via the switch transistor Tadd. Since it is in the conductive state, the voltages of the column signal lines CL (4i-2) and CL (4i) of the 4i-2th column and the 4ith column are the four pixels PE provided with the green filter (Gr). This is a voltage obtained by averaging the optical signals of (1, 4i-2), PE (1, 4i), PE (3, 4i-2), and PE (3, 4i). The averaged voltage is sampled and held by the column amplifier CAMP in the 4i-2th column.

  Each column amplifier CAMP in the 4i-3rd column and the 4i-2th column (where i is an integer equal to or greater than 1) has a difference between the voltage corresponding to the sampled and held optical signal and the voltage corresponding to the dark signal. Is amplified and output. Each A / D converter ADC in the 4i-3rd column and the 4i-2th column (where i is an integer of 1 or more) digitally converts the output of the corresponding column amplifier CAMP and outputs the result. Thus, the addition reading of the optical signal and the dark signal generated in each pixel in the first row and the third row is completed.

  Between the next time t50 and time t60, the light signal and the dark signal generated in each pixel in the second and fourth rows of the pixel array 10A are converted into four pixels PE provided with a blue filter (B). And every four pixels PE provided with the green color filter (Gb). First, when the control signal φPRE is activated between time t51 and time t52, each precharge transistor Tpre of the precharge unit 25 is turned on. As a result, the capacitance Cv of each column signal line CL is precharged to a predetermined precharge voltage Vpre.

  The control signals φSWdo_gb (2), φSWdo_b (2), φSWdo_gb (4), and φSWdo_b (4) are activated between the next time t52 and time t53, whereby the second and fourth rows of the pixel array 10A are activated. In each pixel in the row, the switch transistor SWdo is turned on. At this time, the column signal line CL (1) of the first column and the column signal line CL (3) of the third column are in a conductive state via the switch transistor Tadd in the on state. The voltages of the column signal lines CL (1) and CL (3) of the columns are the four pixels PE (2,1), PE (2,3), PE (4,4) provided with the green filter (Gb). 1) A voltage obtained by averaging the dark signals of PE (4, 3). This averaged voltage is sampled and held by the column amplifier CAMP in the first column. Since the column signal line CL (2) of the second column and the column signal line CL (4) of the fourth column are in a conductive state via the on-state switch transistor Tadd, the second and fourth columns The voltages of the column signal lines CL (2) and CL (4) are the four pixels PE (2,2), PE (2,4), PE (4,2) provided with the blue filter (B), The voltage is obtained by averaging the dark signals of PE (4, 4). This averaged voltage is sampled and held by the column amplifier CAMP in the second column.

  Similarly, the column signal line CL (4i-3) of the 4th-3th column and the column signal line CL (4i-1) of the 4i-1th column (where i is an integer of 1 or more) are in the on state. Since it is in a conductive state via the switch transistor Tadd, the voltages of the column signal lines CL (4i-3) and CL (4i-1) of the 4i-3rd column and the 4i-1th column are green filters (Gb ) Are averaged over the dark signals of the four pixels PE (2,4i-3), PE (2,4i-1), PE (4,4i-3), and PE (4,4i-1). Voltage. The averaged voltage is sampled and held by the column amplifier CAMP in the 4i-3rd column. The column signal line CL (4i-2) of the 4i-2th column and the column signal line CL (4i) of the 4ith column (where i is an integer equal to or greater than 1) are connected via the switch transistor Tadd. Since it is in the conducting state, the voltages of the column signal lines CL (4i-2) and CL (4i) of the 4i-2th column and the 4ith column are the four pixels PE provided with the blue filter (B). This is a voltage obtained by averaging the dark signals of (2, 4i-2), PE (2, 4i), PE (4, 4i-2), and PE (4, 4i). The averaged voltage is sampled and held by the column amplifier CAMP in the 4i-2th column.

  The control signal φPRE is activated between the next time t53 and time t54, whereby each precharge transistor Tpre of the precharge unit 25 is turned on. As a result, the capacitance Cv of each column signal line CL is precharged to a predetermined precharge voltage Vpre.

  The control signals φSWso_gb (2), φSWso_b (2), φSWso_gb (4), φSWso_b (4) are activated between the next time t54 and time t55, so that the second and fourth rows of the pixel array 10A are activated. In each pixel in the row, the switch transistor SWso is turned on. At this time, the column signal line CL (4i-3) in the 4i-3th column and the column signal line CL (4i-1) in the 4i-1th column (where i is an integer equal to or greater than 1) are on. Therefore, the voltages of the column signal lines CL (4i-3) and CL (4i-1) of the 4i-3th column and the 4i-1th column are green filters ( The optical signals of the four pixels PE (2,4i-3), PE (2,4i-1), PE (4,4i-3), PE (4,4i-1) provided with Gb) are provided. It becomes the averaged voltage. The averaged voltage is sampled and held by the column amplifier CAMP in the 4i-3rd column. The column signal line CL (4i-2) of the 4i-2th column and the column signal line CL (4i) of the 4ith column (where i is an integer equal to or greater than 1) are connected via the switch transistor Tadd. Since it is in the conducting state, the voltages of the column signal lines CL (4i-2) and CL (4i) of the 4i-2th column and the 4ith column are the four pixels PE provided with the blue filter (B). It becomes a voltage obtained by averaging the optical signals of (2, 4i-2), PE (2, 4i), PE (4, 4i-2), and PE (4, 4i). The averaged voltage is sampled and held by the column amplifier CAMP in the 4i-2th column.

  Each column amplifier CAMP in the 4i-3rd column and the 4i-2th column (where i is an integer equal to or greater than 1) has a difference between the voltage corresponding to the sampled and held optical signal and the voltage corresponding to the dark signal. Is amplified and output. Each A / D converter ADC in the 4i-3rd column and the 4i-2th column (where i is an integer of 1 or more) digitally converts the output of the corresponding column amplifier CAMP and outputs the result. Thus, the addition reading of the optical signal and the dark signal generated in each pixel in the second row and the fourth row is completed. Similarly for the fifth and subsequent rows, signals of four pixels for two rows and two columns are added for each color of the color filter. Thus, the addition reading of the pixel array 10A is completed.

  In the above description, the case where the 2 × 2 four pixels PE are added has been described. However, by changing the configuration of the switching unit, it is possible to perform pixel addition of another number of pixels such as 3 × 3.

<Configuration of semiconductor device for camera>
FIG. 9 is a block diagram showing a configuration of a semiconductor device for a camera to which the solid-state imaging devices 1 to 3 of the present invention are applied. A camera system 100 shown in FIG. 9 includes a semiconductor device 101 that is an LSI (Large-Scale Integration) circuit in which any one of the solid-state imaging devices 1 to 3 described in Embodiments 1 to 3 is incorporated, and a microcontroller unit. (MCU: Micro Controller Unit) 106, power supply chip 107, liquid crystal display (LCD) 108, and frame buffer 109 are included. In addition to the solid-state imaging device 1, the semiconductor device 101 includes a drive IC (Integrated Circuit) 102, an image processing engine 103, and a memory card interface (I / F) 104.

  In FIG. 9, the MCU 106 controls the entire camera system 100. The power supply chip 107 generates a predetermined DC voltage and supplies it to the solid-state imaging device 1. The driving IC 102 generates a driving pulse signal supplied to the solid-state imaging device 1 in response to an instruction from the MCU 106. The solid-state imaging device 1 converts an image of a subject formed by a lens (not shown) provided in the camera system 100 into an electrical signal corresponding to the light intensity and transfers the electrical signal to the image processing engine 103. The image processing engine 103 processes the image signal received from the solid-state imaging device 1 to generate an image data ID. The image data ID generated by the image processing engine 103 is transferred via the memory card I / F 104 to a removable memory card attached to the dedicated slot. The image data ID generated by the image processing engine 103 is further output to the liquid crystal display device 108 and the frame buffer 109 (built-in memory of the camera system 100).

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1-3 solid-state imaging device, 10, 10A pixel array, 11 imaging unit, 12, 16 switching unit, 30, 31, 32 switching unit, 13 output node, 20 control unit, 21 control logic circuit, 22 vertical scanning circuit, 25 Precharge unit, 101 semiconductor device, AMI amplification transistor, CL column signal line, Cd, Cs capacitive element, FD floating diffusion, GND ground node, PD photodiode, PE, PEA pixel, RST reset transistor, SWdi, SWsi, SWdo, SWso switch transistor (for switching unit 12), SWd, SWs, SWi, SWo switch transistor (for switching unit 16), Tadd, Tline switch transistor (for switching unit 30), TX transfer transistor.

Claims (7)

A pixel array having a plurality of pixels arranged in a matrix;
A plurality of column signal lines provided individually corresponding to each column of the pixel array,
Each of the plurality of pixels constituting the pixel array is
An imaging unit that outputs a first voltage corresponding to the amount of charge generated by photoelectric conversion;
A first capacitive element having one end connected to a reference node providing a reference voltage;
A state in which the other end of the first capacitive element is connected to an output node of the imaging unit, a state in which the other end of the first capacitive element is connected to a corresponding column signal line, and the first capacitive element A solid-state imaging device including: a first switching unit configured to switch the other end of the first switching unit to any one of the unconnected states of the output node and the corresponding column signal line. The imaging unit further outputs a second voltage when the charge generated by the photoelectric conversion is reset,
The solid-state imaging device further includes a second capacitive element having one end connected to the reference node,
In the first switching unit, the other end of the second capacitor is connected to the output node of the imaging unit, and the other end of the second capacitor is connected to a corresponding column signal line. 2. The solid-state imaging device according to claim 1, wherein the state is switched to one of a state where the other end of the second capacitive element is not connected to both the output node and the corresponding column signal line. The plurality of column signal lines are divided into a plurality of groups each including a plurality of column signal lines,
The solid-state imaging device according to claim 2, further comprising a second switching unit that electrically connects column signal lines belonging to the same group. The solid-state imaging device has, as an operation mode, a pixel addition mode in which the output voltage of each imaging unit is added and read for each predetermined number of pixels,
The solid-state imaging device further includes a control unit,
The control unit is output from the imaging unit by connecting the other end of the first capacitive element to the output node using the first switching unit in each pixel constituting the pixel array. Holding the first voltage in the first capacitor,
The control unit is output from the imaging unit by connecting the other end of the second capacitive element to the output node using the first switching unit in each pixel constituting the pixel array. Holding the second voltage in the second capacitor element;
When the controller adds the first voltage held in the first capacitor to a plurality of pixels in the same column in the pixel addition mode, the control unit adds the first voltage to each pixel to be added. Connecting the other end of the capacitive element to a corresponding column signal line by the first switching unit;
When the controller adds the second voltage held in the second capacitor to a plurality of pixels in the same column in the pixel addition mode, the control unit adds the second voltage to each pixel to be added. The solid-state imaging device according to claim 2, wherein the other end of the capacitive element is connected to a corresponding column signal line by the first switching unit. The solid-state imaging device has, as an operation mode, a pixel addition mode in which the output voltage of each imaging unit is added and read for each predetermined number of pixels,
The solid-state imaging device further includes a control unit,
The control unit is output from the imaging unit by connecting the other end of the first capacitive element to the output node using the first switching unit in each pixel constituting the pixel array. Holding the first voltage in the first capacitor,
The control unit is output from the imaging unit by connecting the other end of the second capacitive element to the output node using the first switching unit in each pixel constituting the pixel array. Holding the second voltage in the second capacitor element;
When the controller adds the first voltage held in the first capacitor to a plurality of pixels provided in different columns in the pixel addition mode, the controller corresponds to each pixel to be added. In the state where the column signal line to be connected is connected by the second switching unit, the other end of the first capacitive element is connected to the corresponding column signal line by the first switching unit in each pixel to be added. ,
When the controller adds the second voltage held in the second capacitor element to a plurality of pixels provided in different columns in the pixel addition mode, the controller corresponds to each pixel to be added. In the state where the column signal line to be connected is connected by the second switching unit, the other end of the second capacitor element is connected to the corresponding column signal line by the first switching unit in each pixel to be added. The solid-state imaging device according to claim 3. The first switching unit includes:
A first switch element connected to an output node of the imaging unit and the other end of the first capacitive element;
A second switch element connected to the other end of the first capacitive element and a corresponding column signal line;
A third switch element connected to the output node and the other end of the second capacitive element;
The solid-state imaging device according to claim 2, further comprising a fourth switch element connected to the other end of the second capacitive element and a corresponding column signal line. The second switching unit includes a plurality of fifth switch elements,
Each of the plurality of fifth switch elements corresponds to any two of the plurality of column signal lines, and is connected to the corresponding two column signal lines,
4. The solid-state imaging device according to claim 3, wherein each of the plurality of column signal lines is connected to at least one of the plurality of fifth switch elements.

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