CN109257548A - A kind of cmos image sensor and image output method - Google Patents
A kind of cmos image sensor and image output method Download PDFInfo
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- CN109257548A CN109257548A CN201810908148.3A CN201810908148A CN109257548A CN 109257548 A CN109257548 A CN 109257548A CN 201810908148 A CN201810908148 A CN 201810908148A CN 109257548 A CN109257548 A CN 109257548A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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Abstract
The invention discloses a kind of cmos image sensors, including pixel array, A/2 column grade sampling hold circuit, column selection coding and driving circuit and production line analog-digital converter, the pixel array includes B row A column pixel unit, the m column pixel unit and m+1 column pixel unit share a column grade sampling hold circuit, the A/2 column grade sampling hold circuit is connected to the column selection coding and driving circuit, the other end connection production line analog-digital converter of the column selection coding and driving circuit.A kind of cmos image sensor provided by the invention, switch and capacitor are increased in pixel unit, and two adjacent column pixel units share a column grade sampling hold circuit, by single exposure, that is, exportable secondary complete image, chip area can substantially be reduced using structure of the invention, achieve the effect that reduce chip cost.
Description
Technical field
The present invention relates to field of image sensors, and in particular to a kind of cmos image sensor and image output method.
Background technique
Consumer electronics imaging sensor is to the more demanding of cost performance.Under the premise of retention property is constant, pass through contracting
Small image sensor chip area increases the core number of output on every wafer, is the direct mode for reducing product cost.Cause
This imaging sensor starts the imaging sensor using chip-scale pipelined analog-digital converter type, i.e. an imaging sensor
Only use the analog-digital converter of a flow work mode.Compare traditional image sensing using column grade analog-digital converter
Device, i.e., each column pixel unit needs the imaging sensor of a corresponding column grade analog-digital converter, using chip-scale pipeline system
The imaging sensor of analog-digital converter type has been provided with the advantage centainly minimized on the chip area of reading circuit.
Column grade sampling hold circuit in the prior art is all that a column pixel unit uses one group of 2 sampling holding capacitor,
The sampling holding capacitor includes the capacitor that a capacitor for storage reset signal is used to store optical signal with another, such as
Shown in Fig. 1.The pixel unit of each column in a line successively serially passes through a pipelined analog-digital converter, converts in a row
Then digital signal exports entire image line by line again.Above-mentioned sampling capacitance is also drawn in the version of a column grade circuit in the prior art
In the area of pictural surface, as shown in Figure 2.
But since image sensor structure in the prior art is needed using column grade correlated double sampling circuit, sampling electricity
Sampling holding capacitor in road still can account for a big chunk chip area, especially for guarantee sampled signal matching,
The value needs of introducing that is undistorted and reducing noise, sampling capacitance are the bigger the better.In production application, every one or two are adopted
The capacitance of sample capacitor is in 500fF or so, and in order to guarantee that the capacitance is sufficiently large, the area of column grade correlated double sampling circuit is just needed
Want sufficiently large, therefore column grade correlated double sampling circuit needs to occupy in whole image sensor layout sizable area, and
It is unfavorable for the high integration developing direction of chip.
Based on the high request to photosensitive property, image sensor pixel cells usually require to keep area big as far as possible, and
And corresponding certain optical lens size, the size of pixel unit are substantially uniform.Therefore, we also need further to explore more
Reasonable pixel cell structure and laying out pattern, and reading circuit is reasonably integrated, it is removed with downscaled images sensor
Chip area outside pixel array, while maintaining properties of product constant.
Summary of the invention
The object of the present invention is to provide a kind of cmos image sensors, switch are increased in pixel unit and for storing
The capacitor of signal, and two adjacent column pixel units share a column grade sampling hold circuit and column grade reading circuit, pass through
A single exposure, that is, exportable secondary complete image, can substantially reduce chip area using structure of the invention, reach reduction core
The effect of piece cost.
To achieve the goals above, the present invention adopts the following technical scheme: a kind of cmos image sensor, including pixel battle array
Column, A/2 column grade sampling hold circuit, column selection coding and driving circuit and production line analog-digital converter, the pixel array packet
The A column pixel unit of row containing B, the m column pixel unit and m+1 column pixel unit share a column grade sampling hold circuit,
The A/2 column grade sampling hold circuit is connected to the column selection coding and driving circuit, the column selection coding and driving circuit
The other end connect the production line analog-digital converter；Wherein, A is the even number more than or equal to 2, and B is the integer more than or equal to 1, m
For odd number, and 1≤m < A.
Further, line n m column pixel unit and line n m+1 column pixel unit are multiple simultaneously in the pixel array
Position exposure, and is read out sequentially, wherein n is integer, and 1≤n≤B
Further, the cmos image sensor further includes A/2 column grade reading circuit, wherein the pixel array
In m column pixel unit and m+1 column pixel unit share a column grade reading circuit.
Further, stating line n m column pixel unit includes photodiode PDn,m, transmission control metal-oxide-semiconductor MT1_n, open
S01_n and capacitor C01_n is closed, the line n m+1 column pixel unit includes photodiode PDn,m+1, transmission control metal-oxide-semiconductor
MT2_n, switch S02_n and capacitor C02_n, the line n m column pixel unit and line n m+1 column pixel unit share multiple
Position metal-oxide-semiconductor MR_n, amplification metal-oxide-semiconductor MF_n and row select metal-oxide-semiconductor Mrow_n, specific connection relationship are as follows: the photodiode PDn,m
Anode be connected with ground level, cathode with it is described transmit control metal-oxide-semiconductor MT1_n drain electrode be connected；The transmission controls metal-oxide-semiconductor
The source electrode of MT1_n is connect jointly with one end of one end of the capacitor C01_n and the switch SO1_n, and the transmission controls MOS
The grid of pipe MT1_n is connected with transmission of control signals TX01_n；The other end of the capacitor C01_n is connected with ground level；It is described
The other end and the grid of amplification metal-oxide-semiconductor MF_n of switch S01_n, the source electrode for resetting metal-oxide-semiconductor MR_n, one end of switch S02_n are total
With connection；The photodiode PDn,m+1Anode be connected with ground level, cathode and transmit control metal-oxide-semiconductor MT2_n drain electrode phase
Even；The source electrode of the transmission control metal-oxide-semiconductor MT2_n and one end of the capacitor C02_n and the other end of the switch SO2_n are total
With connection, the grid of the transmission control metal-oxide-semiconductor MT2_n is connected with transmission of control signals TX02_n；The capacitor C02_n's is another
One end is connected with ground level；The other end of the switch S02_n and the source for amplifying the grid of metal-oxide-semiconductor MF_n, reset metal-oxide-semiconductor MR_n
Pole, switch S01_n one end connect jointly；The grid for resetting metal-oxide-semiconductor MR_n is connected with reset signal RST_n, described multiple
The drain electrode of position metal-oxide-semiconductor MR_n is connected with positive pole VDD；The drain electrode of the amplification metal-oxide-semiconductor MF_n is connected with positive pole VDD,
The source electrode of the amplification metal-oxide-semiconductor MF_n selects the drain electrode of metal-oxide-semiconductor Mrow_n to be connected with row, and the row selects the grid of metal-oxide-semiconductor Mrow_n
Be connected with row selects signal RS_n, the row select the source electrode of metal-oxide-semiconductor Mrow_n as in image sensor array line n m column and
The common signal output end of line n m+1 column pixel unit.
Further, the signal output end of each column pixel unit links together in the pixel array.
Further, the control signal of odd column is all the same in every row pixel unit in the pixel array, even column
It is all the same to control signal.
Further, the metal-oxide-semiconductor in the pixel unit is NMOS tube.
Further, the source electrode and drain electrode in the pixel array can be interchanged.
A method of image output is carried out using cmos image sensor of the present invention, is included the following steps:
S01: the switch S01_n and switch S02_n in pixel array in line n pixel unit are simultaneously closed off, to pixel battle array
Pixel unit in column line n is resetted simultaneously；Wherein, n is integer, and 1≤n≤B；
S02: turning on the switch S02_n, maintains the reset signal of even column pixels unit in pixel array line n；
S03: being exposed the pixel unit in pixel array line n simultaneously, at this point, the optical signal after exposure is stored in
In photodiode；
S04: control signal TX01_n becomes high level, so that in line n in odd column pixel unit in photodiode
Optical signal transmission into capacitor C01_n, later read line n in odd column image；
S05: control signal TX02_n becomes high level, so that in line n in even column pixels unit in photodiode
Optical signal transmission into capacitor C02_n, later read line n in even column group image；
S06: odd column figure in line n and even column image are combined into line n image；
S07: repeating step S01-S06, carries out resetting exposure reading to all rows in pixel array, obtains complete figure
Picture.
The invention has the benefit that switch and the capacitor for storing signal are increased in the present invention in pixel unit,
And adjacent parity column pixel unit shares a column grade sampling hold circuit, by single exposure, that is, exportable parity column figure
Picture.The corresponding column grade sampling hold circuit of middle each column pixel, the present invention can be realized on chip area compared with the prior art
Miniaturization.Meanwhile because the column grade sampling hold circuit that parity column is shared can be to avoid between the column and the column because of design rule
Requirement caused by chip area lose, to further reduce chip in the case where capacitance size is certain and arrange
Area occupied by direction.Therefore, structure of the invention can substantially reduce chip area, reach the effect for reducing chip cost
Fruit.
Detailed description of the invention
Attached drawing 1 is the structural schematic diagram of column grade sampling hold circuit in the prior art.
Attached drawing 2 is the structural schematic diagram of cmos image sensor in the prior art.
Attached drawing 3 is the structural schematic diagram of the pixel unit of cmos image sensor in the prior art.
Attached drawing 4 is the structural schematic diagram of cmos image sensor in the present invention.
Attached drawing 5 is the structural schematic diagram of the pixel unit of cmos image sensor in the present invention.
Attached drawing 6 is the domain schematic diagram of cmos image sensor in the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, with reference to the accompanying drawing to specific reality of the invention
The mode of applying is described in further detail.
As described in Fig. 1, general column grade sampling hold circuit is all that a column pixel unit is kept using one group of 2 sampling
Capacitor, the specific capacitor for being used to store optical signal with another comprising a capacitor for storage reset signal.In a line
The pixel unit of each column successively serially passes through a pipelined analog-digital converter, converts digital signal in a row, then again
Entire image is exported line by line.Sampling capacitance is also drawn in the chip area of a column grade circuit, as shown in Figure 2.
It is as shown in Fig. 3 using the corresponding pixel cell structure of above-mentioned column grade sampling hold circuit in the prior art, it is each
The structure of a pixel unit is all the same, the anode of the photodiode PD of line n m column pixel unit in image sensor array
It is connected with ground level, cathode is connected with the drain electrode of transmission control metal-oxide-semiconductor MT_n, the source electrode of transmission control metal-oxide-semiconductor MT_n and amplification
The grid of metal-oxide-semiconductor MF_n, the source electrode for resetting metal-oxide-semiconductor MR_n connect jointly, the grid connection transmission control of transmission control metal-oxide-semiconductor MT_n
Signal TX_n processed；The drain electrode for resetting metal-oxide-semiconductor MR_n connects positive pole, and grid connects reset signal；Amplify the leakage of metal-oxide-semiconductor MF_n
Pole is connected with positive pole VDD, and the source electrode for amplifying metal-oxide-semiconductor MF_n selects the drain electrode of metal-oxide-semiconductor Mrow_n to be connected with row, and row selects metal-oxide-semiconductor
The grid of Mrow_n is connected with row selects signal RS_n, and row selects the source electrode of metal-oxide-semiconductor Mrow_n as line n in image sensor array
The signal output end of m column pixel unit.Wherein, m, n indicate any one pixel unit in pixel array, whole pixel battle array
Array structure is as shown in Fig. 3.
In existing pixel unit as shown in Fig. 3, the pixel of every a line carries out reset exposure, and each column simultaneously
The corresponding column grade sampling hold circuit of pixel unit and column grade reading circuit, when every one-row pixels carry out while resetting exposure
Later, the electric signal in every a line in pixel unit is read by corresponding column grade reading circuit.
The innovation of the invention consists in that the quantity of column grade sampling hold circuit and column grade reading circuit is halved, that is, phase
Two adjacent column pixel units share a column grade sampling hold circuit and column grade reading circuit；It can reduce the sampling of column grade in this way to protect
Circuit and the occupied area of column grade reading circuit are held, and bigger capacitance can be set on identical area.Difference
The structure of one group of reading circuit is shared in same row pixel unit in the prior art, the present invention uses adjacent parity column pixel list
The structure of member shared one group of column grade reading circuit and column grade sampling hold circuit, on the signal for reading entire pixel array, meeting
Encounter certain difficulty: because the reset of every a line empties, exposure was completed in the same time, i.e., a pair of of odd even of every a line
Column can be completed to reset in synchronization, and exposure, still, reading circuit is shared, therefore cannot read simultaneously the surprise in a line
Ordered series of numbers signal and even number column signal.If not using special dot structure, odd column is first read, then read even column, although reading
Circuit is the same, because signal sum is identical on the time including carrying out analog-to-digital conversion.But this needs to expose 2 times, that is, reads
After complete odd column, need to re-start primary identical exposure, to read even column.In this way, the frame per second of imaging sensor can be big
Width decline.Therefore the present invention is needed using the pixel cell structure for being different from the prior art, so that making adjacent odd even
Column pixel is read out sequentially by primary reset exposure.Specifically, the present invention in pixel unit structure in increase switch and
For storing the capacitor of electric signal, so as to reset exposure by primary as existing sensor, entire image is read.
As shown in Fig. 5, the pixel unit in the present invention uses such as flowering structure: since adjacent parity column pixel shares one
A column grade sampling hold circuit, by adjacent parity column wherein for two pixel units of a line in attached drawing 3, to the present invention
The mechanism of middle pixel unit is described: specifically by taking line n m column pixel unit and line n m+1 column pixel unit as an example into
Row explanation:
Line n m column pixel unit includes photodiode PDn,m, transmission control metal-oxide-semiconductor MT1_n, switch S01_n and electricity
Hold C01_n, line n m+1 column pixel unit includes photodiode PDn,m+1, transmission control metal-oxide-semiconductor MT2_n, switch S02_n
With capacitor C02_n, line n m column pixel unit and line n m+1 column pixel unit share and reset metal-oxide-semiconductor MR_n, amplification MOS
Pipe MF_n and row select metal-oxide-semiconductor Mrow_n.Wherein, n is integer, and 1≤n≤B；M is odd number, and 1≤m < A.
Specific connection relationship are as follows: photodiode PDn,mAnode be connected with ground level, cathode with transmit control metal-oxide-semiconductor
The drain electrode of MT1_n is connected；The source electrode of transmission control metal-oxide-semiconductor MT1_n and one end of capacitor C01_n and one end of switch SO1_n are total
With connection, the grid of transmission control metal-oxide-semiconductor MT1_n is connected with transmission of control signals TX01_n；The other end and ground of capacitor C01_n
Level is connected；The other end of switch S01_n and source electrode, the switch S02_n for amplifying the grid of metal-oxide-semiconductor MF_n, reset metal-oxide-semiconductor MR_n
One end connect jointly；Photodiode PDn,m+1Anode be connected with ground level, cathode with transmit control metal-oxide-semiconductor MT2_n leakage
Extremely it is connected；The source electrode of transmission control metal-oxide-semiconductor MT2_n is connect jointly with the other end of one end of capacitor C02_n and switch SO2_n,
The grid of transmission control metal-oxide-semiconductor MT2_n is connected with transmission of control signals TX02_n；The other end of capacitor C02_n and ground level phase
Even；The other end of switch S02_n and the one end for amplifying the grid of metal-oxide-semiconductor MF_n, the source electrode for resetting metal-oxide-semiconductor MR_n, switch S01_n
Common connection；The grid for resetting metal-oxide-semiconductor MR_n is connected with reset signal RST_n, resets drain electrode and the positive pole of metal-oxide-semiconductor MR_n
VDD is connected；The drain electrode of amplification metal-oxide-semiconductor MF_n is connected with positive pole VDD, and the source electrode and row for amplifying metal-oxide-semiconductor MF_n select metal-oxide-semiconductor
The drain electrode of Mrow_n, row select the grid of metal-oxide-semiconductor Mrow_n to be connected with row selects signal RS_n, and row selects the source electrode of metal-oxide-semiconductor Mrow_n to make
For line n pixel in image sensor array, the signal output end that m is arranged and m+1 column pixel unit is common.And so on, this hair
The output end of bright middle line n m+2 column and m+3 column pixel unit is connected to common output end.And it is defeated in same row
Outlet links together.
The structure of the pixel unit of two row parity columns adjacent in pixel array is identical as above-mentioned statement in the present invention, the
N+1 row m column and m+1 column pixel unit can be refering to shown in attached drawings 5, certainly, the structure of the pixel unit except attached drawing 5
It is consistent with above-mentioned statement.
Please continue to refer to attached drawing 5, the control signal of odd column is identical in every row pixel unit in pixel array in the present invention,
The control signal of even column is identical.Above-mentioned metal-oxide-semiconductor can be NMOS tube or PMOS tube simultaneously, and the source electrode of metal-oxide-semiconductor and leakage
Pole can be interchanged.
Attached drawing 6 is please referred to, pixel cell structure is shared based on parity column of the invention and realizes parity column and shares a column
The structure and domain of grade sampling hold circuit, being capable of substantially chip area required for downscaled images sensor readout circuit.Together
When, shared structure proposed by the present invention can lose again to avoid active region area caused by layout design rules, thus further
Area shared by entire reading circuit domain is reduced, principle is as shown in Figure 6.Every group of column grade sampling hold circuit in the prior art
Domain between can all have certain spacing, this is because to meet the production design rule of domain, such as upper left corner institute in attached drawing 6
Show, since there are two capacitors for tool in each column grade sampling hold circuit, for the capacitor I of storage reset signal and for storing light
The capacitor II of signal therefore in the prior art will be there are four mos capacitance, due to domain in two column grade sampling hold circuits
Production design rule, require to maintain a certain distance between each capacitor, these distances will occupy the part in domain
Area.And using the structure of the shared column grade sampling hold circuit of parity column in the present invention, i.e., adjacent parity column pixel unit is only
A column grade sampling hold circuit, corresponding two capacitors are needed, therefore only need to keep a gap between two mos capacitances
, such as the mos capacitance schematic diagram in the lower left corner and the upper right corner in attached drawing 6.That is, The present invention reduces between mos capacitance
The chip area that is wasted of gap, draw an equal amount of mos capacitance if necessary, then can cause to avoid such design rule
Space wastage.Therefore an equal amount of capacitance, chip area can be accomplished more to minimize.
The method for carrying out image output using cmos image sensor of the present invention, includes the following steps:
S01: the switch S01_n and switch S02_n in pixel array in line n pixel unit are simultaneously closed off, to pixel battle array
Pixel unit in column line n is resetted simultaneously；Wherein, n is integer, and 1≤n≤B；
S02: turning on the switch S02_n, maintains the reset signal of even column pixels unit in pixel array line n；
S03: being exposed the pixel unit in pixel array line n simultaneously, at this point, the optical signal after exposure is stored in
In photodiode；
S04: control signal TX01_n becomes high level, so that in line n in odd column pixel unit in photodiode
Optical signal transmission into capacitor C01_n, later read line n in odd column image；
S05: control signal TX02_n becomes high level, so that in line n in even column pixels unit in photodiode
Optical signal transmission into capacitor C02_n, later read line n in even column group image；
S06: odd column figure in line n and even column image are combined into line n image；
S07: repeating step S01-S06, carries out resetting exposure reading to all rows in pixel array, obtains complete figure
Picture.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit patent protection of the invention
Range, thus it is all with the variation of equivalent structure made by specification and accompanying drawing content of the invention, it similarly should be included in this
In the protection scope of invention appended claims.
Claims (9)
1. a kind of cmos image sensor, which is characterized in that compiled including pixel array, A/2 column grade sampling hold circuit, column selection
Code and driving circuit and production line analog-digital converter, the pixel array include B row A column pixel unit, the m column pixel list
Member and m+1 column pixel unit share a column grade sampling hold circuit, and the A/2 column grade sampling hold circuit is connected to institute
State column selection coding and driving circuit, the other end connection production line analog-digital converter of the column selection coding and driving circuit；
Wherein, A is even number more than or equal to 2, and B is the integer more than or equal to 1, and m is odd number, and 1≤m < A.
2. a kind of cmos image sensor according to claim 1, which is characterized in that line n m in the pixel array
Column pixel unit and line n m+1 column pixel unit reset exposure simultaneously, and are read out sequentially, wherein n is integer, and 1≤n
≤B。
3. a kind of cmos image sensor according to claim 2, which is characterized in that the cmos image sensor also wraps
Include A/2 column grade reading circuit, wherein m column pixel unit and m+1 column pixel unit share one in the pixel array
Column grade reading circuit.
4. a kind of cmos image sensor according to claim 3, which is characterized in that the line n m column pixel unit
Including photodiode PDn,m, transmission control metal-oxide-semiconductor MT1_n, switch S01_n and capacitor C01_n, the line n m+1 column picture
Plain unit includes photodiode PDn,m+1, transmission control metal-oxide-semiconductor MT2_n, switch S02_n and capacitor C02_n, the line n the
M column pixel unit and line n m+1 column pixel unit share reset metal-oxide-semiconductor MR_n, amplification metal-oxide-semiconductor MF_n and row and select metal-oxide-semiconductor
Mrow_n, specific connection relationship are as follows:
The anode of the photodiode PDn, m are connected with ground level, the drain electrode of cathode and the transmission control metal-oxide-semiconductor MT1_n
It is connected；The source electrode of the transmission control metal-oxide-semiconductor MT1_n and one end of the capacitor C01_n and one end of the switch SO1_n are total
With connection, the grid of the transmission control metal-oxide-semiconductor MT1_n is connected with transmission of control signals TX01_n；The capacitor C01_n's is another
One end is connected with ground level；The other end of the switch S01_n and the source for amplifying the grid of metal-oxide-semiconductor MF_n, reset metal-oxide-semiconductor MR_n
Pole, switch S02_n one end connect jointly；The anode of the photodiode PDn, m+1 are connected with ground level, cathode and transmission
The drain electrode for controlling metal-oxide-semiconductor MT2_n is connected；It is described transmission control metal-oxide-semiconductor MT2_n source electrode and the capacitor C02_n one end and
The other end of the switch SO2_n connects jointly, the grid and transmission of control signals TX02_ of the transmission control metal-oxide-semiconductor MT2_n
N is connected；The other end of the capacitor C02_n is connected with ground level；The other end and amplification metal-oxide-semiconductor MF_n of the switch S02_n
Grid, reset the source electrode of metal-oxide-semiconductor MR_n, one end of switch S01_n connects jointly；It is described reset metal-oxide-semiconductor MR_n grid with
Reset signal RST_n is connected, and the drain electrode for resetting metal-oxide-semiconductor MR_n is connected with positive pole VDD；The amplification metal-oxide-semiconductor MF_n
Drain electrode be connected with positive pole VDD, it is described amplification metal-oxide-semiconductor MF_n source electrode with go select the drain electrode of metal-oxide-semiconductor Mrow_n to be connected, institute
Stating row selects the grid of metal-oxide-semiconductor Mrow_n to be connected with row selects signal RS_n, and the row selects the source electrode of metal-oxide-semiconductor Mrow_n to pass as image
The signal output end that line n m is arranged in sensor array and line n m+1 column pixel unit is common.
5. a kind of cmos image sensor according to claim 4, which is characterized in that each column pixel in the pixel array
The signal output end of unit links together.
6. a kind of cmos image sensor according to claim 4, which is characterized in that every row pixel in the pixel array
The control signal of odd column is identical in unit, and the control signal of even column is identical.
7. a kind of cmos image sensor according to claim 4, which is characterized in that the metal-oxide-semiconductor in the pixel unit
It is NMOS tube.
8. a kind of cmos image sensor according to claim 4, which is characterized in that source electrode in the pixel array and
Drain electrode can be interchanged.
9. a kind of method for carrying out image output using cmos image sensor as claimed in claim 4, which is characterized in that including
Following steps:
S01: the switch S01_n and switch S02_n in pixel array in line n pixel unit are simultaneously closed off, to pixel array n-th
Pixel unit in row is resetted simultaneously；Wherein, n is integer, and 1≤n≤B；
S02: turning on the switch S02_n, maintains the reset signal of even column pixels unit in pixel array line n；
S03: being exposed the pixel unit in pixel array line n simultaneously, at this point, the optical signal after exposure is stored in photoelectricity
In diode；
S04: control signal TX01_n becomes high level, so that the light in line n in odd column pixel unit in photodiode
Signal is transmitted in capacitor C01_n, reads odd column image in line n later；
S05: control signal TX02_n becomes high level, so that the light in line n in even column pixels unit in photodiode
Signal is transmitted in capacitor C02_n, reads even column group image in line n later；
S06: odd column figure in line n and even column image are combined into line n image；
S07: repeating step S01-S06, carries out resetting exposure reading to all rows in pixel array, obtains complete image.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110146178A (en) * | 2019-04-29 | 2019-08-20 | 北京安酷智芯科技有限公司 | A kind of reading circuit and its working method |
| CN111918008A (en) * | 2020-08-05 | 2020-11-10 | 成都微光集电科技有限公司 | Image sensor |
| CN112714268A (en) * | 2020-08-21 | 2021-04-27 | 深圳市汇顶科技股份有限公司 | Image sensor, fingerprint detection device and electronic equipment |
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