CN115855271A - Reading circuit with large charge processing capacity and infrared thermal imager - Google Patents
Reading circuit with large charge processing capacity and infrared thermal imager Download PDFInfo
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- CN115855271A CN115855271A CN202310145779.5A CN202310145779A CN115855271A CN 115855271 A CN115855271 A CN 115855271A CN 202310145779 A CN202310145779 A CN 202310145779A CN 115855271 A CN115855271 A CN 115855271A
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Abstract
The invention provides a reading circuit with large charge processing capacity and an infrared thermal imager.A infrared detection module converts infrared light into current, inputs the current into an integral capacitor module for integration when a first MOS tube is conducted, obtains the integrated charge, and transfers the charge to a column-level integrator when a second MOS tube is conducted. The column-level integrator resets the column-level integrating capacitor when the third MOS transistor is switched on, receives charges through the column-level integrating capacitor, obtains a voltage signal, and outputs the voltage signal when the fourth MOS transistor is switched on. According to the invention, the third MOS transistor for resetting can be moved out of the pixel-level unit circuit, and the integral capacitor module in the pixel-level unit circuit is indirectly reset through the operational amplifier, so that the number of transistors in the pixel-level unit circuit is reduced, the area of the pixel accommodating the integral capacitor module is maximized, the integral charge quantity of the detector pixel is increased, and the temperature sensitivity of the infrared imager is improved.
Description
Technical Field
The invention belongs to the technical field of infrared thermal imaging, and particularly relates to a reading circuit with large charge processing capacity and an infrared thermal imager.
Background
The infrared focal plane detector assembly is an important photoelectric device for acquiring infrared thermal radiation information of a target scene and is an important component of an infrared thermal imager. The core component of the infrared focal plane detector assembly is an infrared focal plane detector chip set. The infrared Focal Plane detector chip set is formed by flip interconnection of an infrared Focal Plane Array (FPA) chip and a readout circuit chip through indium columns. The basic function of the readout circuit chip is to perform pre-amplification processing on the electrical signals converted by each pixel of the infrared detector array chip, and then serially read out through one or more output buffers (also called multiplexers).
The typical readout circuit mainly comprises an M × N input stage unit circuit array, a column stage sample-hold circuit, a row and column stage shift register, an output amplification stage and the like. In order to obtain dynamic continuous distribution information of target heat radiation, a high-performance readout circuit generally adopts a Snapshot (Snapshot) integration mode, and photosensitive current is subjected to integration processing through an integration capacitor in an input stage unit circuit.
The signal-to-noise ratio of the infrared detector follows the following law: under the conditions of constant background radiation and relatively unchanged photocurrent, the larger the integral charge amount is, the longer the integral time is, the larger the signal-to-noise ratio of the infrared detector is, and the higher the temperature sensitivity performance of the infrared thermal imager is.
Generally, the integrating capacitor occupies about 70% to 80% of the area of the input stage unit of the sensing circuit, which is the primary consideration in the design of the sensing circuit. Because the MOS capacitor has a higher cell capacitance, the MOS capacitor is generally used as an integrating capacitor in the input stage cell of the conventional sensing circuit. However, in the case where the area of the integrating capacitor occupies a relatively large area in a limited pixel area, it is difficult to further improve the temperature sensitivity performance of the infrared thermal imager.
Disclosure of Invention
In order to solve the above problems, the present invention provides a readout circuit with large charge handling capability and an infrared thermal imager.
In a first aspect of the present invention, there is provided a readout circuit having a large charge handling capability, comprising: a plurality of pixel-level unit circuits arranged in a matrix form and a plurality of column-level integrators respectively corresponding to the pixel-level unit circuits of a plurality of columns in the matrix;
the pixel level unit circuit comprises an infrared detection module, an integral capacitor module, a first MOS (metal oxide semiconductor) tube and a second MOS tube;
the infrared detection module is used for converting infrared light into current and inputting the current into the integration capacitor module for integration processing when the first MOS tube is conducted to obtain integrated charges;
the integration capacitor module is used for transferring the integrated charges to the column-level integrator when the second MOS tube is conducted;
the column-level integrator comprises a rail-to-rail operational amplifier, a third MOS tube, a fourth MOS tube and a column-level integrating capacitor;
the output end of the integrating capacitor module is connected with the negative input end of the rail-to-rail operational amplifier, and the column-level integrator is used for resetting the column-level integrating capacitor when the third MOS tube is switched on, receiving the integrated charge through the column-level integrating capacitor, obtaining a voltage signal, and outputting the voltage signal when the fourth MOS tube is switched on.
In one possible implementation manner, the infrared detection module comprises an N-on-P type infrared detector or a P-on-N type infrared detector.
In a possible implementation manner, in a case that the infrared detection module is the N-on-P type infrared detector, a reference voltage of the anode of the rail-to-rail operational amplifier is a power supply voltage.
In a possible implementation manner, in a case that the infrared detection module is the P-on-N type infrared detector, a reference voltage of the anode of the rail-to-rail operational amplifier is a ground voltage.
In a possible implementation manner, the integration capacitor module includes an MOS capacitor and an MIM capacitor connected in parallel, and the MIM capacitor and the MOS capacitor are arranged in an upper and lower three-dimensional layout.
In one possible implementation, the charge handling capability of the pixel-level cell circuit is represented by the formula Qmax = VDDA × (C _ MOS + C _ MIM), where Qmax is the maximum value of the integrated charge, VDDA is the supply voltage, C _ MOS is the capacitance value of the MOS capacitor, and C _ MIM is the capacitance value of the MIM capacitor.
In a possible implementation manner, after the third MOS transistor is turned on, the first MOS transistor is turned on, after the first MOS transistor is turned on, the second MOS transistor is turned on, and after the second MOS transistor is turned on, the fourth MOS transistor is turned on.
In a possible implementation manner, the third MOS transistor is connected in parallel with the column-level integrating capacitor and is connected across the negative input end and the output end of the rail-to-rail operational amplifier.
In one possible implementation, the rail-to-rail operational amplifier includes at least one set of NMOS differential pair structures and at least one set of PMOS differential pair structures.
In a second aspect of the present invention, there is provided an infrared thermal imager comprising: an infrared focal plane array chip and the readout circuit with large charge processing capacity.
According to the reading circuit with large charge processing capacity, the third MOS tube used for resetting is moved out of the pixel level unit circuit, the integration capacitor module in the pixel level unit circuit is indirectly reset through the operational amplifier performance, the number of transistors in the pixel level unit circuit is reduced, the area of the pixel containing the integration capacitor module is maximized, the MOS capacitor and the MIM capacitor which are connected in parallel and adopt the layout mode of an upper three-dimensional layout and a lower three-dimensional layout are used as the integration capacitors, the integration charge quantity of the pixel of the detector is improved, and the temperature sensitivity performance of the infrared imager is improved. In addition, the integrated charges can be completely converted into voltage signals by using the rail-to-rail operational amplifier and the column-level integrating capacitor, high linearity is realized in a full voltage range, and the performances of a reading circuit and an infrared thermal imager are improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts,
FIG. 1 is a schematic diagram of a pixel level cell circuit according to the present invention;
FIG. 2 is a schematic diagram of a column level integrator provided in the present invention;
FIG. 3 is a schematic diagram of a rail-to-rail operational amplifier provided in the present invention;
FIG. 4 is a timing diagram of signals provided by the present invention;
fig. 5 is a schematic view of an infrared thermal imager provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In one possible implementation manner, in order to further improve the temperature sensitivity performance of the infrared thermal imager, the present invention provides a readout circuit with a large charge handling capability, where the readout circuit with a large charge handling capability includes: a plurality of pixel-level unit circuits arranged in a matrix form and a plurality of column-level integrators respectively corresponding to the pixel-level unit circuits of a plurality of columns in the matrix;
the pixel-level unit circuit comprises an infrared detection module, an integral capacitor module, a first MOS (metal oxide semiconductor) tube and a second MOS tube;
the infrared detection module is used for converting infrared light into electric charge and inputting the electric charge into the integration capacitor module for integration processing when the first MOS tube is conducted;
the integration capacitor module is used for transferring the integrated charges to the column-level integrator when the second MOS tube is conducted;
the column-level integrator comprises a rail-to-rail operational amplifier, a third MOS tube, a fourth MOS tube and a column-level integrating capacitor;
the output end of the integrating capacitor module is connected with the negative input end of the rail-to-rail operational amplifier, and the column-level integrator is used for resetting the column-level integrating capacitor when the third MOS tube is switched on, receiving the integrated charge through the column-level integrating capacitor, obtaining a voltage signal, and outputting the voltage signal when the fourth MOS tube is switched on.
According to the reading circuit with large charge processing capacity, the third MOS tube for resetting is moved out of the pixel level unit circuit, the integral capacitor module in the pixel level unit circuit is indirectly reset through the operational amplifier performance, the number of transistors in the pixel level unit circuit is reduced, the area of the pixel area for accommodating the integral capacitor module is maximized, the integral charge quantity of the detector pixel is improved, and the temperature sensitivity performance of the infrared imager is improved. In addition, the integrated charges can be completely converted into voltage signals by using a rail-to-rail operational amplifier and a column-level integrating capacitor, high linearity is realized in a full voltage range, and the performances of a reading circuit and an infrared thermal imager are improved.
Fig. 1 is a schematic diagram of a pixel-level unit circuit provided by the present invention, where the pixel-level unit circuit includes an infrared detection module, an integration capacitor module, a first MOS transistor M1 and a second MOS transistor M2, the infrared detection module is connected to a source of the first MOS transistor M1, the integration capacitor module is connected to a drain of the first MOS transistor M1 and a source of the second MOS transistor M2, a drain of the second MOS transistor M2 is an output terminal OUT1 of the pixel-level unit circuit, a gate of the first MOS transistor M1 is connected to a signal INT, and a gate of the second MOS transistor M2 is connected to a READ signal READ. The infrared detection module is configured to convert infrared light into current, that is, a photosensitive current, and when the first MOS transistor M1 is turned on, the current flows into the integration capacitor module to perform integration processing, for example, when the signal INT of the gate of the first MOS transistor M1 is at a high level, the first MOS transistor M1 is turned on, so that the integration capacitor module can perform integration processing on the photosensitive current. Further, when the second MOS transistor M2 is turned on, the integrated charge may be transferred to the column integrator, that is, the column integrator corresponding to the column of the pixel unit circuit, for example, when the READ signal READ at the gate of the second MOS transistor M2 is at a high level, the second MOS transistor M2 is turned on, and the integrated charge may be output to the column integrator through the output terminal OUT1 of the pixel unit circuit.
In one possible implementation, as shown in fig. 1, the infrared detection module includes an N-on-P type infrared detector, or a P-on-N type infrared detector. If an N-on-P type infrared detector is used, the N pole of the N-on-P type infrared detector is connected with the source electrode of the first MOS tube M1, and the P pole of the N-on-P type infrared detector is connected with the common electrode SUBPV. If a P-on-N type infrared detector is used, the P pole of the P-on-N type infrared detector is connected with the source electrode of the first MOS tube M1, and the N pole of the P-on-N type infrared detector is connected with the common electrode SUBPV.
In a possible implementation manner, as shown in fig. 1, the integration capacitor module includes a MOS capacitor C _ MOS and a MIM capacitor C _ MIM connected in parallel, and the MIM capacitor C _ MIM are arranged in an upper and lower three-dimensional layout. That is, when setting up the position of two electric capacities, can make two electric capacities set up side by side in vertical direction to further reduce the area occupied of two electric capacities, increase integral capacitance's area promotes the integral charge volume, thereby promotes infrared imager's temperature sensitivity performance. One end of each of the two capacitors of the integrating capacitor module is grounded, and the other end of each capacitor is connected with the drain electrode of the first MOS transistor M1 and the source electrode of the second MOS transistor M2.
Fig. 2 is a schematic diagram of a column level integrator provided in the present invention. As shown in fig. 2, the column integrator includes a rail-to-rail operational amplifier a, a third MOS transistor M3, a fourth MOS transistor M4, and a column integrating capacitor C3. The output end OUT1 of the integrating capacitor module is connected with the negative input end Vin-of the rail-to-rail operational amplifier A, and the positive input end Vin + of the rail-to-rail operational amplifier A is connected with a reference voltage Vref.
In one possible implementation, as shown in fig. 2, the third MOS transistor M3 is connected in parallel with the column-level integrating capacitor C3, and is connected across the negative input terminal Vin-and the output terminal of the rail-to-rail operational amplifier. The fourth MOS transistor M4 is disposed between the output terminal of the rail-to-rail operational amplifier a and the output terminal of the column-stage integrator.
In a possible implementation manner, the column-level integration capacitor C3 is reset when the third MOS transistor M3 is turned on, in an example, when the gate of the third MOS transistor M3 is connected to the reset signal RST1, and the RST1 is at a high level, the third MOS transistor M3 may be turned on, so that the column-level integration capacitor C3 is reset. For example, during the reset process, the column-level integrating capacitor C3 discharges the charges across the electrodes, for example, discharges the charges introduced by the previous pixel-level unit circuit, and prepares to receive the charges introduced by the current pixel-level unit circuit.
In a possible implementation manner, the column-level integrating capacitor C3 may receive charges introduced by the integrating capacitor module, so that a potential difference is formed between two ends of the column-level integrating capacitor C3 to obtain a voltage signal. Moreover, the electric charges are converted into voltage signals through the column-level integrating capacitor C3, and the linearity of the voltage signals is improved. Further, the voltage signal may be output when the fourth MOS transistor is turned on, in an example, a gate of the fourth MOS transistor is connected to the signal Col _ SW, and when the signal Col _ SW is at a high level, the fourth MOS transistor is turned on, and the output end OUT of the column-level integrator outputs the voltage signal, for example, to an on-chip output bus. After the voltage signal is output, a process of receiving the charge of the next pixel level unit circuit, converting the charge into the voltage signal, and outputting the voltage signal may be performed.
In a possible implementation manner, the reference voltage Vref to which the positive input terminal Vin + of the rail-to-rail operational amplifier a is connected can be determined according to the type of the infrared detection module. And under the condition that the infrared detection module is the N-on-P type infrared detector, the reference voltage of the anode of the rail-to-rail operational amplifier can be set as a power supply voltage. In a case where the infrared detection module is the P-on-N type infrared detector, a reference voltage of an anode of the rail-to-rail operational amplifier may be set to a ground voltage.
In a possible implementation manner, before each pixel-level unit circuit performs charge integration, the integrating capacitor module and the column-level integrating capacitor C3 may be reset, as described above, when the third MOS transistor M3 is turned on, the column-level integrating capacitor C3 may be reset, and at the same time, the voltage of the positive input terminal Vin + of the rail operational amplifier a is equal to or similar to the voltage of the negative input terminal Vin-, so that the voltage at the positive input terminal Vin + is approximately equal to the reference voltage Vref, and when the second MOS transistor M2 is turned on, the potential difference between the integrating capacitor module and the negative input terminal Vin-is approximately equal to the reference voltage Vref, thereby resetting the integrating capacitor module is implemented.
In the example, if the IR detection module is a P-on-N IR detector, the reference voltage at the positive input terminal Vin + of rail-to-rail operational amplifier A is ground voltage GNDA, so that the voltage at the negative input terminal Vin-is also ground voltage GNDA. After the first MOS tube is conducted, the photosensitive current of the P-on-N type infrared detector can charge the MOS capacitor C _ MOS and the MIM capacitor C _ MIM of the integrating capacitor module, so that the integrating capacitor module reaches or is close to a power supply voltage VDDA, and after the second MOS tube is conducted, the voltage of the negative input end Vin-of the rail-to-rail operational amplifier A is equal to or close to a grounding voltage GNDA, therefore, the potential difference between the integrating capacitor module and the negative input end Vin-of the rail-to-rail operational amplifier A is equal to or approximately equal to the power supply voltage VDDA, so that the integrated charge in the integrating capacitor module is transferred to a column-level integrator, for example, a column-level integrating capacitor C3 in the column-level integrator to form a voltage signal, and the voltage of the integrating capacitor module is reset to the grounding voltage GNDA.
In the example, if the infrared detection module is an N-on-P type infrared detector, the reference voltage at the positive input terminal Vin + of the rail-to-rail operational amplifier A is the supply voltage VDDA, so that the voltage at the negative input terminal Vin-is also the supply voltage VDDA. After the first MOS transistor is turned on, the photo-sensitive current of the N-on-P type infrared detector can discharge the charges in the MOS capacitor C _ MOS and the MIM capacitor C _ MIM of the integrating capacitor module with the voltage equal to or approximately equal to the power supply voltage VDDA, for example, to reach or approximately reach the ground voltage GNDA, and after the second MOS transistor is turned on, the potential difference between the integrating capacitor module and the negative input terminal Vin of the rail-to-rail operational amplifier A is equal to or approximately equal to the power supply voltage VDDA because the voltage of the negative input terminal Vin-of the rail-to-rail operational amplifier A is equal to or approximately equal to the power supply voltage VDDA, so that the charges integrated in the integrating capacitor module are transferred to the column-level integrator, for example, the column-level integrating capacitor C3 in the column-level integrator, to form a voltage signal, and the voltage of the integrating capacitor module is reset to the power supply voltage VDDA.
In one possible implementation, according to the above reset and integration process, the charge handling capability of the pixel level cell circuit is represented by equation (1),
Qmax=VDDA×(C_MOS+C_MIM) （1）
qmax is the maximum value of the integrated charge, that is, the charge amount obtained by integrating the voltage of the integrating capacitor module with the power supply voltage VDDA. VDDA is a power supply voltage, C _ MOS is a capacitance value of the MOS capacitor, and C _ MIM is a capacitance value of the MIM capacitor.
In one possible implementation manner, in order to improve the charge processing capability of the pixel-level unit circuit, the maximum value of the integrated charge is improved, so that the voltages of the positive input terminal Vin + and the negative input terminal Vin-of the rail-to-rail operational amplifier a are close to or almost equal, and thus the charge processing capability of the pixel-level unit circuit can almost reach the maximum value Qmax of the integrated charge.
Fig. 3 is a schematic diagram of a rail-to-rail operational amplifier provided by the present invention. As shown in fig. 3, the rail-to-rail operational amplifier a includes at least one set of NMOS differential pair structures and at least one set of PMOS differential pair structures. In an example, the at least one set of NMOS differential pair structures includes a differential pair structure composed of NMOS transistors MN1 and MN2, a differential pair structure composed of NMOS transistors MN3 and MN4, and a differential pair structure composed of NMOS transistors MN5 and MN 6. The positive input end Vin + of the rail-to-rail operational amplifier A is a grid electrode of the NMOS transistor MN1, and the negative input end Vin-of the rail-to-rail operational amplifier A is a grid electrode of the NMOS transistor MN 2. The grid electrodes of the NMOS tubes MN5 and MN6 are connected with the drain electrode of the NMOS tube MN3, and the source electrodes of the NMOS tubes MN5 and MN6 are grounded. The gates of the NMOS transistors MN3 and MN4 are connected to the bias voltage VBIAS5. The source electrode of the NMOS tube MN3 is connected with the drain electrode of the NMOS tube MN5, and the source electrode of the NMOS tube MN4 is connected with the drain electrode of the NMOS tube MN 6. The drain of the NMOS transistor MN4 is connected to the output terminal Vout of the rail operational amplifier a.
In an example, the at least one set of PMOS differential pair structures includes a differential pair structure composed of PMOS transistors MP1 and MP2, a differential pair structure composed of PMOS transistors MP3 and MP4, and a differential pair structure composed of PMOS transistors MP5 and MP 6. The grid electrode of the PMOS tube MP1 is connected with the positive electrode input end Vin + of the rail-to-rail operational amplifier A, the grid electrode of the PMOS tube MP2 is connected with the negative electrode input end Vin-of the rail-to-rail operational amplifier A, the source electrodes of the PMOS tubes MP1 and MP2 are connected with the drain electrode of the NMOS tube MN7, the grid electrode of the NMOS tube MN7 is connected with the bias voltage VBIAS2, and the source electrode of the NMOS tube MN7 is grounded. The drain electrodes of the PMOS transistors MP1 and MP2 are connected to the source electrode of the PMOS transistor MP7, the gate electrode of the PMOS transistor MP7 is connected to the bias voltage VBIAS1, and the drain electrode of the PMOS transistor MP7 is connected to the power supply voltage VDDA. The grid electrodes of the PMOS tubes MP3 and MP4 are connected with a bias voltage VBIAS3, the drain electrodes are connected with a power supply voltage VDDA, the source electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP5 and the drain electrode of the NMOS tube MN2, and the source electrode of the PMOS tube MP4 is connected with the drain electrode of the PMOS tube MP6 and the drain electrode of the NMOS tube MN 1. The gates of the PMOS transistors MP5 and MP6 are connected to the bias voltage VBIAS4, the source of the PMOS transistor MP5 is connected to the drain of the NMOS transistor MN3 and the gates of the NMOS transistors MN5 and MN6, and the PMOS transistor MP6 is connected to the output terminal Vout of the rail operational amplifier a.
In one possible implementation, based on the above connection relationship, when the reference voltage is the power voltage due to the input common mode voltage of the NMOS differential pair structure, the negative input terminal Vin-of the rail-to-rail operational amplifier a may be equal to or very close to the power voltage. Due to the input common mode voltage of the PMOS differential pair structure, the negative input terminal Vin-of the rail-to-rail operational amplifier A can be equal to or very close to the ground voltage when the reference voltage is the ground voltage.
FIG. 4 is a timing diagram of signals provided by the present invention. As shown in fig. 4, the reset signal RST1 connected to the third MOS transistor M3 is first raised to a high level, the signal INT connected to the first MOS transistor M1 is raised to a high level after the reset signal RST1 is lowered to a low level, the signal READ connected to the second MOS transistor M2 is raised to a high level after the signal INT is lowered to a low level, and the signal Col _ sw connected to the fourth MOS transistor M4 is raised to a high level after the signal READ is lowered to a low level.
In a possible implementation manner, based on the timing sequence of the signals, the turn-on sequence of each MOS transistor is as follows: and after the third MOS tube is conducted, the first MOS tube is conducted, after the first MOS tube is conducted, the second MOS tube is conducted, and after the second MOS tube is conducted, the fourth MOS tube is conducted.
In a possible implementation manner, after the third MOS transistor is turned on, the column-level integrating capacitor C3 is reset, and after the reset, the third MOS transistor may be turned off, and then, the first MOS transistor is turned on. After the first MOS tube is conducted, photosensitive current generated by the infrared detection module carries out charge integration processing on an MOS capacitor C _ MOS and an MIM capacitor C _ MIM of the integration capacitor module, after integration is completed, the first MOS tube is turned off, then the second MOS tube is conducted, so that the potential difference between the integration capacitor module and a negative electrode input end Vin-of the rail-to-rail operational amplifier A is approximately equal to a power supply voltage VDDA, charges in the integration capacitor module are transferred to a column-level integration capacitor C3, a voltage signal is formed, and the integration capacitor module is reset. Then, the second MOS transistor is turned off, and the fourth MOS transistor is turned on, so that the column-level integrator outputs the voltage signal, for example, to an on-chip output bus.
According to the reading circuit with large charge processing capacity, the third MOS tube used for resetting is moved out of the pixel level unit circuit, the integration capacitor module in the pixel level unit circuit is indirectly reset through the operational amplifier performance, the number of transistors in the pixel level unit circuit is reduced, the area of the pixel containing the integration capacitor module is maximized, the MOS capacitor and the MIM capacitor which are connected in parallel and adopt the layout mode of an upper three-dimensional layout and a lower three-dimensional layout are used as the integration capacitors, the integration charge quantity of the pixel of the detector is improved, and the temperature sensitivity performance of the infrared imager is improved. In addition, the integrated charges can be completely converted into voltage signals by using a rail-to-rail operational amplifier and a column-level integrating capacitor, high linearity is realized in a full voltage range, and the performances of a reading circuit and an infrared thermal imager are improved.
Experiments prove that: at 30X 30um 2 An input stage reading circuit in the pixel area and a column-level integrating circuit with a rail-to-rail operational amplifier realize that the charge processing capacity is 76Me-, compared with the 36 Me-charge processing capacity in the related technology, under the same photocurrent condition, the integration time is prolonged by about 2.16 times, the signal-to-noise ratio is improved by about 1.5 times, and the detection rate of the long-wave infrared detector is improved by about 1.5 times. The reading circuit improves the electrostatic discharge protection capability and enhances the reliability of the reading circuit.
The invention also provides an infrared thermal imager, comprising: an infrared focal plane array chip and the readout circuit with large charge processing capacity.
Fig. 5 is a schematic diagram of an infrared thermal imager provided by the present invention, which includes a readout circuit (i.e., a readout circuit chip) with large charge handling capability, and an infrared focal plane array chip, where the infrared focal plane array chip is used as an infrared detector. The readout circuit chip comprises pixel level unit circuits arranged in a matrix form, the pixel level unit circuits are connected with each pixel of the infrared focal plane array chip through an interconnection indium ball, and the readout circuit chip further comprises an output port used for outputting the voltage signals.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A readout circuit having a large charge handling capability, comprising: a plurality of pixel-level unit circuits arranged in a matrix form and a plurality of column-level integrators respectively corresponding to the pixel-level unit circuits of a plurality of columns in the matrix;
the pixel-level unit circuit comprises an infrared detection module, an integral capacitor module, a first MOS (metal oxide semiconductor) tube and a second MOS tube;
the infrared detection module is used for converting infrared light into current and inputting the current into the integration capacitor module for integration processing when the first MOS tube is conducted, so as to obtain integrated charges;
the integration capacitor module is used for transferring the integrated charges to the column-level integrator when the second MOS tube is conducted;
the column-level integrator comprises a rail-to-rail operational amplifier, a third MOS tube, a fourth MOS tube and a column-level integrating capacitor;
the output end of the integrating capacitor module is connected with the negative input end of the rail-to-rail operational amplifier, and the column-level integrator is used for resetting the column-level integrating capacitor when the third MOS tube is switched on, receiving the integrated charge through the column-level integrating capacitor, obtaining a voltage signal, and outputting the voltage signal when the fourth MOS tube is switched on.
2. The readout circuit with large charge handling capability of claim 1, wherein the infrared detection module comprises an N-on-P type infrared detector, or a P-on-N type infrared detector.
3. The readout circuit with large charge handling capability according to claim 2, wherein in the case that the infrared detection module is the N-on-P type infrared detector, the reference voltage of the anode of the rail-to-rail operational amplifier is a power supply voltage.
4. The readout circuit with large charge handling capability according to claim 2, wherein in the case that the infrared detection module is the P-on-N type infrared detector, the reference voltage of the anode of the rail-to-rail operational amplifier is a ground voltage.
5. The readout circuit with large charge handling capability according to claim 2, wherein the integrating capacitor module comprises a MOS capacitor and a MIM capacitor connected in parallel, and the MIM capacitor and the MOS capacitor are arranged in an upper and lower three-dimensional layout.
6. The readout circuit with large charge handling capability of claim 5, wherein the charge handling capability of the pixel-level cell circuit is expressed by the formula Qmax = VDDA x (C _ MOS + C _ MIM), where Qmax is the maximum value of the integrated charge, VDDA is the supply voltage, C _ MOS is the capacitance value of the MOS capacitor, and C _ MIM is the capacitance value of the MIM capacitor.
7. The readout circuit with large charge handling capability according to claim 1, wherein the first MOS transistor is turned on after the third MOS transistor is turned on, the second MOS transistor is turned on after the first MOS transistor is turned on, and the fourth MOS transistor is turned on after the second MOS transistor is turned on.
8. A readout circuit with large charge handling capability as claimed in claim 1 wherein the third MOS transistor is connected in parallel with the column-level integrating capacitor and connected across the negative input terminal and the output terminal of the rail-to-rail operational amplifier.
9. The large charge handling capability readout circuit of claim 1 wherein the rail-to-rail operational amplifier comprises at least one set of NMOS differential pair structures and at least one set of PMOS differential pair structures.
10. An infrared thermal imager, comprising: an infrared focal plane array chip and a readout circuit having a large charge handling capability according to any one of claims 1 to 9.
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