JP2006223006A - Signal transfer apparatus, imaging apparatus and radiation image pickup system using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal transfer apparatus, etc. of a high S/N ratio and high read speed suitable for use in multiple pixels of a photoelectric conversion circuit. <P>SOLUTION: In the signal transfer apparatus comprising a plurality of terminals 112 connected to a plurality of signal sources and a read circuit unit 103 for converting signals inputted from the terminals 112 into series signals and outputting the resulting series signals, the read circuit unit 103 comprises first operational amplifiers E1-E3 connected to each terminal and second operational amplifiers B1-B3 for receiving outputs of the first operational amplifiers, each of the first operational amplifiers comprises an inverting input terminal connected to a corresponding terminal, an outout terminal with an integral capacitor Cf1 and a switch S<SB>RES1</SB>-S<SB>RES3</SB>connected in parallel between it and the inverting input terminal and a non-inverting input terminal supplied with a reference voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a signal transfer device, an imaging device using the signal transfer device, and a radiation imaging system, and particularly to an X-ray detector for medical treatment and internal nondestructive inspection, and an image input unit of office equipment such as a copying machine and a facsimile. It can be suitably used for a photoelectric conversion device that can be used.

  At present, a so-called film system in which radiation imaging apparatuses used for medical diagnosis are exposed to a human body, the transmitted radiation is converted into visible light by a phosphor, and exposed to a film is the mainstream.

  However, in recent years for reasons such as improved diagnostic efficiency resulting from the immediacy of image information acquisition that cannot be obtained by conventional film methods that require development processing steps, ease of image transmission necessary for recording, management and remote medical diagnosis, etc. The demand for “digitalization of X-ray image information” is increasing, and recently, an X-ray imaging apparatus using a CCD solid-state imaging element or an amorphous silicon photoelectric conversion element instead of a film has been proposed.

  FIG. 29 is a diagram showing an example of a two-dimensional photoelectric conversion apparatus applicable to the X-ray imaging apparatus described in JP-A-9-307698.

In FIG. 29, 101 indicates a photoelectric conversion circuit unit, 110 is a light receiving region for converting incident light into signal charges, 111 is an interelectrode capacitance for storing signal charges photoelectrically converted in the light receiving region 110, and S _1. the photoelectric conversion element _-1 to S _3-3 are, each having a light-receiving region 110 and the inter-electrode capacitance 111, M1, M2, M3 is the matrix signal wire, T _1-1 through T _3-3 photoelectric conversion elements S _1- switching elements for transferring signal charges formed in ₁ to S _3-3 to matrix signal wirings M1, M2, M3, G1, G2, G3 are gate driving line for driving the switching element T _1-1 through T _3-3 , C1, C2, and C3 are load capacitances of the matrix signal wirings M1, M2, and M3. Reference numeral 102 denotes a shift register as a gate line driving circuit unit for applying a driving signal to the gate driving wirings G1 to G3. Reference numeral 107 denotes a bias power source for the photoelectric conversion element.

_{Reference numeral 103} denotes a read circuit unit which converts parallel signals transferred from the matrix signal wirings M1 to M3 into serial signals and outputs them. S _RES1 , S _RES2 and S _RES3 are resets of the load capacitors C1, C2 and C3. A switch, CRES is a control signal applied to S _RES1 , S _RES2 , S _RES3 , and A1 to A3 are buffers for impedance conversion of output signals from the matrix signal wirings with the matrix signal wirings M1 to M3 connected to the normal input terminals. Amplifier, Sn1 to Sn3 are sampling switches for sampling the output signals output through the buffer amplifiers A1 to A3, SMPL is a voltage pulse applied to the sampling switches Sn1 to Sn3, C _{L1 to} C _L3 are sampling capacitors, and B1 to B3 are sampling Output signal is input to the forward input terminal and impedance conversion is performed. Buffer amplifier, Sr1-Sr3 the reading switches sequentially reading the output of the buffer amplifier B1~B3 as a serial signal, 104 is a shift register as a reading switch driving circuit unit, 105 is an output buffer amplifier.

  An A / D conversion circuit unit 106 converts an analog signal into a digital signal.

  Note that FIG. 29 shows a 3 × 3 = 9 pixel two-dimensional photoelectric conversion device for the sake of simplicity, but an actual photoelectric conversion device may be configured with more pixels depending on the application.

  FIG. 30 is a timing chart illustrating the operation of the photoelectric conversion device in FIG.

The signal charges photoelectrically converted by the photoelectric conversion elements S _1-1 to S _3-3 is a period of time accumulated in inter-electrode capacitor 111 in the photoelectric conversion element. Then, when the first voltage pulse for transfer from the shift register 102 to the gate driving line G1 is applied t1 hours, and ON the switching element T _1-1 through T _1-3, the first row of the photoelectric conversion elements S _{1- The} signal charges stored in _{1 to} S _1-3 are transferred to the load capacitors C1, C2, and C3 of the matrix signal wirings M1, M2, and M3, respectively, and the signal charges are transferred to the load capacitors C1, C2, and C3, respectively. If the subsequent potentials are V1, V2, and V3, respectively, the potentials V1, V2, and V3 differ depending on the signal charge amount. FIG. 30 shows a case where each signal charge amount is different. The operation so far is referred to as transfer operation.

The signal charges of the matrix signal wirings M1 to M3 are impedance-converted by the buffer amplifiers A1 to A3 in the reading circuit unit 103, respectively. Thereafter, the sampling switches Sn1 to Sn3 are turned on for t2 time by the SMPL pulse shown in the figure, and the signal charges are transferred to the sampling capacitors C _{L1 to} C _L3 . This operation is called sampling operation.

Subsequently, the readout switches Sr1 to Sr3 are sequentially turned on by t3 hours by the readout pulses Sp1 to Sp3 from the sequential shift register 104, so that the parallel signal charges transferred to the sampling capacitors C _{L1 to} C _L3 are transferred to the respective buffers. After impedance conversion by the amplifiers B <b> 1 to B <b> 3, it is read out as a serial signal from the final output amplifier 105 and further digitized by the A / D conversion circuit unit 106. This operation is called a read operation.

After that, the control signal CRES is applied to the reset switches S _{RES1 to} S _RES1 for t4 hours to reset the load capacitors C1 to C3 and prepare for the read operation of the next row. This operation is called a reset operation.

Similarly, by sequentially driving the gate driving line G2, G3 from the shift register 102, all the pixel data of the photoelectric conversion elements S _2-1 to S _3-3 are repeatedly read.

Load capacity C1~C3 of each matrix signal wire M1~M3 shown in FIG. 29, actually at the intersection between the gate electrode and the signal line M1~M3 side electrode of the switching element T _1-1 through T _3-3 It is comprised by the capacity | capacitance (Cgs) between electrodes formed. For example, the load capacitance C1 is the signal lines 3 connected to the M1 switching elements T _1-1, T _2-1, the sum of Cgs of T _3-1. The same applies to the load capacities C2 and C3. That is, when the pixel array of the two-dimensional photoelectric conversion circuit unit is m rows × n columns, the load capacitance values Ci (i = 1 to n) of the matrix signal wirings Mi (i = 1 to n) are expressed by the following general formula. Is done.

Ci = Cgs × m (1)
The signal charge accumulated in the interelectrode capacitance 111 in the photoelectric conversion element is transferred to the load capacitance Ci (i = 1 to n) of each matrix signal wiring Mi (i = 1 to n) by the transfer operation described above. At this time, the potential Vi of the load capacitance Ci is defined as Cs for the interelectrode capacitance in the photoelectric conversion element and Qi for the signal charge.
Vi = Qi / (Cs + Ci) = Qi / (Cs + mCgs) (2)
It becomes. The potential Vs of the interelectrode capacitance Cs before transfer is
Vs = Qi / Cs (3)
Therefore, the signal voltage Vi after the transfer is reduced by the load capacitance Ci of the matrix signal wiring. Although depending on the size of the photoelectric conversion circuit unit 101, Cgs itself is small as it is, and if the pixel arrangement is as small as 3 × 3 as in the example of FIG. 29, the influence of the load capacitance Ci is small, but the number of pixels is small. When it increases, it cannot be ignored. For example, the size of the photoelectric conversion circuit part of a medical radiation imaging apparatus is required to be about 40 cm × 40 cm when taking an example of an apparatus for imaging the lung, and if formed with a pixel pitch of 100 μm, The number is enormous as 4000 × 4000 = 16 million. Here, when Cs = 3 pF and Cgs = 0.05 pF are used as general numerical values when the switching element described in Japanese Patent Laid-Open No. 9-307698 is formed of an amorphous silicon TFT, the potential Vs and the potential Vi are used. The ratio of Vs: Vi = 1 / Cs: 1 / (Cs + 4000Cgs) = 1: 1/68 (4)
Thus, it can be seen that the load capacity becomes dominant. Thus, the compression of the potential of the signal charge by the transfer operation is disadvantageous in terms of S / N in the subsequent read operation.

That is, in the readout circuit unit 103 in FIG. 29, voltage noise after the sampling switches Sn1 to Sn3 is represented by Vn (Vn is thermal noise caused by the ON resistances of the sampling switches Sn1 to Sn3 and the readout switches Sr1 to Sr3 and the buffer amplifiers B1 to B1). B3 and the mean square of the noise of the output amplifier 105)), the S / N ratio is Vi / Vn. Therefore, compared with the case where the signal voltage is not compressed by the transfer operation, it is about 36 dB. It can also be seen that S / N deteriorates. In the readout circuit unit 103, thermal noise caused by the ON resistances of the reset switches S _{RES1 to} S _RES3 and noise of the buffer amplifiers A1 to A3 exist in addition to the above Vn, but these are equivalent to Vi. This is omitted in the discussion of S / N.

  A photoelectric conversion device that can improve the S / N problem is shown in FIG. In FIG. 31, R7 and R8 are resistance elements, D1 to D3 are matrix signal wirings M1 to M3 connected to normal input terminals, and output signals from the respective matrix signal wirings are amplification factors G determined by the resistors R7 and R8. It is a non-inverting amplifier that amplifies.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  FIG. 31 shows an example in which the photoelectric conversion circuit unit 101 includes 3 × 3 = 9 pixels, as in FIG. 29. The difference from FIG. 29 is that the buffer amplifiers A1 to A3 connected to the matrix signal wires M1 to M3 in the read circuit unit 103 have non-inverting amplifiers D1 to D1 having amplification factors G determined by the resistors R7 and R8. It is a point changed to D3.

  Similarly, when S / N is discussed, the photoelectrically converted signal charges Qi are transferred to the load capacitors C1 to C3 of the matrix signal wirings M1 to M3, and the potentials V1 to V3 of the load capacitors C1 to C3 are the same as in FIG. It becomes a value represented by the formula (2). Here, in the case of FIG. 31, the signal voltages V1 to V3 of the load capacitors C1 to C3 connected to the normal input terminals by the non-inverting amplifiers D1 to D3 are amplified by G times and output. That is, when the pixel configuration is generalized as a two-dimensional photoelectric conversion device of m rows × n columns, the output voltage Vout is expressed as follows.

Vout = G × Vi = G × Qi / (Cs + Ci)
= G × Qi / (Cs + mCgs) (i = 1 to n) (5)
Here, when the amplification factor G of the non-inverting amplifiers D1 to D3 is set, for example, as follows, G = 1 + (R8 / R7) = 1 + (mCgs / Cs) (6)
The output voltage Vout is equal to equation (3) as in equation (7).

Vout = Qi / Cs = Vs (7)
That is, it can be seen that the signal voltage compression problem due to the transfer operation is solved and the S / N is improved as compared with the equation (2). Here, for simplicity of explanation, a value represented by the equation (6) is used as the amplification factor G. However, the amplification factor may be any value as long as G> 1. Further, it is obvious that it is advantageous for S / N to take G as large as possible.

However, in the example shown in FIG. 31, there is room for improvement in terms of versatility when the same readout circuit unit is used in combination with a two-dimensional photoelectric conversion circuit unit having a different pixel arrangement. That is, the readout circuit unit 103 has the same photoelectric conversion element unit and the same photoelectric conversion efficiency (generates the same signal charge Qi for the same light amount), but the pixel arrangement is k rows × l columns and m rows × n columns. When applied to two different types of photoelectric conversion circuit units, according to the equation (5), each output voltage is Vout = G × Qi / (Cs + kCgs) (8)
Vout ′ = G × Qi / (Cs + mCgs) (9)
As a result, the signal output differs depending on the load capacitance value of the matrix signal wiring. This is because, for example, in a conventional film type X-ray imaging apparatus, even when the film size is changed depending on the part to be imaged, the same dynamic range and S / N can be obtained if the film sensitivity and the X-ray exposure amount are the same. However, because it is extremely versatile, there is a difference in the performance of these photoelectric conversion devices depending on the model, so a dedicated readout circuit unit with a fixed amplification factor G appropriate for each model with a different pixel arrangement is prepared. This means that it is necessary to provide means for setting the gain G in a circuit for each model. In the former case, it is practically impossible and uneconomical to prepare individual readout circuit units for all models including those to be commercialized in the future. The latter also causes an increase in cost, such as a complicated circuit.

  In addition to the above-described problems, in the case of providing an integration capacitor between the inverting input terminal and the output terminal of a conventionally known operational amplifier, it is difficult to sufficiently shorten the reset time of the integration capacitor. There is room for further improvement in order to improve the operation speed of the signal transfer apparatus.

  An object of the present invention is to provide a highly versatile signal transfer apparatus, an imaging apparatus using the same, and a radiation imaging system.

  In addition, another object of the present invention is to provide a signal transfer device, a signal processing device, an imaging device using the same, and radiation that are excellent in S / N, increase the readout speed, and are suitable for increasing the number of pixels in the photoelectric conversion circuit section. To provide an imaging system.

A signal transfer apparatus according to the present invention includes a plurality of terminals connected to a plurality of signal sources, and a read circuit unit that converts a signal input from the plurality of terminals into a serial signal and outputs the serial signal. In
The readout circuit unit includes a first operational amplifier connected to the terminal, a sampling switch that samples an output signal output through the first operational amplifier, and a sampling capacitor that stores the sampled output signal. A read switch for sequentially reading out the stored output signal as a serial signal from the sampling capacitor, and a second operational amplifier for receiving the serial signal, the first operational amplifier corresponding to the terminal And an inverting input terminal to which a reference voltage is supplied, and an output terminal. An integration capacitor is provided between the inverting input terminal and the output terminal of the first operational amplifier. A reset switch is connected in parallel, and the second operational amplifier is connected to the sampling capacitor via the readout switch. A non-inverting input terminal to which a reference voltage is supplied, and an output terminal. An integration capacitor and a reset switch are connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier. It is connected.

The signal transfer device of the present invention is a signal transfer device having an operational amplifier.
The operational amplifier includes an inverting input terminal connected to the corresponding terminal, a normal input terminal supplied with a reference voltage, and an output terminal, and the inverting input terminal and the output terminal of the operational amplifier, The integration capacitor and the reset switch are connected in parallel between
A switching circuit that charges and discharges the phase compensation capacitance of the operational amplifier and a control circuit that controls the switching circuit according to the operation of the reset switch of the operational amplifier are provided.

An imaging device of the present invention includes a circuit unit having a conversion element that converts at least one of incident light or radiation into an electric signal, and a signal transfer circuit unit that transfers a signal from the circuit unit. In the imaging device,
The signal transfer circuit unit includes a first operational amplifier connected to the circuit unit, a sampling switch for sampling an output signal output through the first operational amplifier, and a sampling capacitor for storing the sampled output signal A read switch that sequentially reads out the stored output signal as a serial signal from the sampling capacitor, and a second operational amplifier that receives the serial signal, wherein the first operational amplifier includes the circuit unit. And an inverting input terminal to which a reference voltage is supplied, and an output terminal. An integration capacitor is provided between the inverting input terminal and the output terminal of the first operational amplifier. A reset switch is connected in parallel, and the second operational amplifier is connected to the sampling capacitor via the readout switch. A non-inverting input terminal to which a reference voltage is supplied and an output terminal, and an integration capacitor and a reset switch are connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier It is characterized by being.

The image pickup apparatus of the present invention includes a circuit unit having a conversion element that converts at least one of incident light or radiation into an electric signal, and a signal transfer circuit unit that transfers a signal from the circuit unit. In the imaging apparatus provided,
The signal transfer circuit unit includes an operational amplifier connected to the circuit unit, and the operational amplifier includes an inverting input terminal connected to the circuit unit, a normal input terminal to which a reference voltage is supplied, and an output And an integrating capacitor and a reset switch are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier,
The operational amplifier is characterized in that a capacitor and a reset switch are further connected in parallel to the integration capacitor connected between the inverting input terminal and the output terminal of the operational amplifier.

  In the present invention, since the signal wiring is connected to the inverting input terminal of the operational amplifier, the potential is equal to the normal input terminal voltage of the operational amplifier. Therefore, the signal charge output from the signal source is accumulated in the integration capacitor connected between the inverting input terminal and the output terminal of the operational amplifier, and the output voltage is the signal charge amount and the capacitance value of the integration capacitor. Is uniquely determined. Therefore, since the output voltage of the operational amplifier does not depend on the load capacitance of the signal wiring, for example, it can be applied universally to photoelectric conversion circuit units having various pixel arrays.

  In addition, since the signal charge output from the first operational amplifier is further input to another operational amplifier, the output signal charge is appropriately subjected to, for example, impedance conversion or input to another operational amplifier according to the application. It is also possible to amplify the signal.

  Further, in the present invention, the integration capacitor can be reset at high speed by controlling the switching circuit that charges and discharges the phase compensation capacitor of the operational amplifier according to the operation of the reset switch.

  As described above, according to the present invention, the signal output voltage of the readout circuit unit does not depend on the load capacitance of the signal wiring, and is output from the first operational amplifier at the first stage of the readout circuit unit. By further inputting the obtained signal to the operational amplifier, it is possible to, for example, impedance-convert the output signal charge according to the application, or to amplify the signal by inputting it to another operational amplifier. A signal transfer device can be provided.

  Further, according to the present invention, since the capacitive element connected in series to the output terminal of the first operational amplifier of the readout circuit section acts to allow only the AC component of the signal to pass through, for example, KTC noise generated during the reset operation is reduced. It is possible to provide a canceled high S / N photoelectric conversion device and a signal transfer device whose current consumption does not change depending on the signal level.

  In addition, according to the present invention, since a low-pass filter is formed by a resistor element and a capacitor element connected in series to the first operational amplifier of the readout circuit unit, a noise component in a high frequency region above the signal pass band is cut off. A high S / N signal transfer apparatus can be provided.

  Further, according to the present invention, the operational amplifier that controls the serial conversion output of the readout circuit section directly reads out the signal charge stored in the sampling capacitor to the integration capacitor, so that the number of operational amplifiers required for serial conversion is reduced. It is possible to reduce the power consumption of the system, and it is possible to provide a high S / N signal transfer apparatus in which the dark power component increases and the fixed pattern noise does not increase due to heat generation.

  In addition, according to the present invention, by providing a plurality of operational amplifiers that control the serial conversion output of the readout circuit unit, high-speed readout is possible, and a signal transfer device suitable for high-definition still image output and moving image output is provided. Is possible.

  In addition, according to the present invention, since the readout circuit section has means for changing the amplification factor by an external control signal, the gain of the signal output can be corrected, and a sufficient dynamic range can be obtained for various applications with different signal charge amounts. It is possible to provide a highly versatile photoelectric conversion device possessing In addition, it is possible to provide a signal transfer device having a uniform output at a low cost by correcting output variations of the photoelectric conversion elements.

  In the signal charge readout circuit according to the present invention, the phase of the operational amplifier is reset during a period of resetting the integration capacitor for reading the signal charge connected between the inverting operational amplifier and the inverting input terminal and the output terminal of the operational amplifier. Since it has a switching circuit for forcibly charging and discharging the compensation capacity and a control circuit for controlling the switching circuit, the reset time can be shortened. For example, in a multi-pixel such as a two-dimensional photoelectric conversion device that handles moving images, A signal transfer device suitable for a photoelectric conversion device that requires high-speed signal readout can be provided.

  According to the present invention, the signal output voltage of the read circuit unit does not depend on the load capacitance of the signal wiring, and further, the signal output from the first operational amplifier in the first stage of the read circuit unit is further processed by the operational amplifier. It is possible to provide an imaging device that can also output the signal charge as appropriate according to the application, for example, by impedance conversion, or input to another operational amplifier to amplify the signal. It becomes.

  Further, according to the present invention, since the capacitive element connected in series to the output terminal of the first operational amplifier of the readout circuit section acts to allow only the AC component of the signal to pass through, for example, KTC noise generated during the reset operation is reduced. It is possible to provide a canceled high S / N photoelectric conversion device and an imaging device whose current consumption does not change depending on the signal level.

  In addition, according to the present invention, since a low-pass filter is formed by a resistor element and a capacitor element connected in series to the first operational amplifier of the readout circuit unit, a noise component in a high frequency region above the signal pass band is cut off. A high S / N imaging device can be provided.

  Further, according to the present invention, the operational amplifier that controls the serial conversion output of the readout circuit section directly reads out the signal charge stored in the sampling capacitor to the integration capacitor, so that the number of operational amplifiers required for serial conversion is reduced. It is possible to reduce the power consumption of the system, and it is possible to provide a high S / N imaging device in which the dark power component is increased and the fixed pattern noise is not increased due to heat generation.

  In addition, according to the present invention, by providing a plurality of operational amplifiers that control the serial conversion output of the readout circuit unit, high-speed readout is possible, and an imaging apparatus suitable for high-definition still image output and moving image output is provided. It becomes possible.

  In addition, according to the present invention, since the readout circuit section has means for changing the amplification factor by an external control signal, the gain of the signal output can be corrected, and a sufficient dynamic range can be obtained for various applications with different signal charge amounts. It is possible to provide a highly versatile photoelectric conversion device possessing In addition, the output variation of the photoelectric conversion element is corrected, and an imaging apparatus having a uniform output can be provided at a low cost.

  In the signal charge readout circuit according to the present invention, the phase of the operational amplifier is reset during a period of resetting the integration capacitor for reading the signal charge connected between the inverting operational amplifier and the inverting input terminal and the output terminal of the operational amplifier. Since it has a switching circuit for forcibly charging and discharging the compensation capacity and a control circuit for controlling the switching circuit, the reset time can be shortened. For example, in a multi-pixel such as a two-dimensional photoelectric conversion device that handles moving images, An imaging device suitable for a photoelectric conversion device that requires high-speed signal readout can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram of a signal transfer apparatus according to a first embodiment of the present invention. In FIG. 1, 112 is a plurality of terminals connected to a plurality of signal wirings connected to a signal source, 103 is a readout circuit unit that converts parallel signals transferred via the terminals 112 into serial signals and outputs them, E1 to E3 are a plurality of operational amplifiers connected to the respective terminals 112, and the first operational amplifier which is the first stage with respect to the terminal 112, and Cf1 is between the inverting input terminal and the output terminal of the first operational amplifiers E1 to E3. , S _{RES1 to} S _RES3 are first reset switches of the respective first integration capacitors Cf1, CRES is a control signal applied to S _RES1 , S _RES2 and S _RES3 , and VREF1 is a first operational amplifier E1 A first reference voltage with a non-inverting input terminal of E3 to E3, Sn1 to Sn3 are sampling switches for sampling output signals output through the first operational amplifiers E1 to E3, SMPL Is a voltage pulse applied to the sampling switches Sn1 to Sn3, C _{L1 to} C _L3 are sampling capacitors, B1 to B3 are buffer amplifiers for impedance conversion of signal charges accumulated in the sampling capacitors C _{L1 to} C _L3 , and Sr1 to Sr3 are buffers A read switch for sequentially reading out the outputs of the amplifiers B1 to B3 as a serial signal, 104 is a read switch driving circuit unit (shift register: SR2), 105 is an output buffer amplifier, and 113 is an output signal output from the output buffer amplifier 105 Is a terminal for connecting to other circuits depending on the application.

  Reference numeral 106 denotes an A / D conversion circuit unit. In this embodiment, an output signal from the readout circuit unit 103 is connected to the A / D conversion circuit unit, but this is not restrictive. For example, the A / D conversion circuit unit 106 is included in the reading circuit unit 103 and can be connected to a processing circuit such as a memory via the terminal 113.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(Second Embodiment)
FIG. 2 is a circuit diagram of an imaging apparatus according to the second embodiment of the present invention. In FIG.
101 denotes a photoelectric conversion circuit section, 110 light receiving region for converting incident light into a signal charge, 111 inter-electrode capacitor for accumulating signal charges photoelectrically converted by the light receiving region 110, S _1-1 to S the photoelectric conversion element _3-3 each having a light-receiving region 110 and the inter-electrode capacitance 111, M1, M2, M3 is the matrix signal lines as signal lines, T _1-1 through T _3-3 photoelectric conversion elements S _1- switching elements for transferring signal charges formed in ₁ to S _3-3 to matrix signal wirings M1, M2, M3, G1, G2, G3 are gate driving line for driving the switching element T _1-1 through T _3-3 , C1, C2, and C3 are load capacitances of the matrix signal wirings M1, M2, and M3. Examples of the photoelectric conversion element include a MIS type or PIN type thin film photoelectric conversion element using a hydrogenated amorphous silicon film, a PN photodiode using single crystal silicon, and the like. As the switching element, a thin film transistor using amorphous silicon, polycrystalline silicon, single crystal silicon, or the like, or a well-known MOS transistor can be used.

  Reference numeral 102 denotes a driving circuit unit (shift register: SR1) that applies a driving signal to the gate driving wirings G1 to G3. Reference numeral 103 denotes a read circuit unit. Reference numeral 107 denotes a bias power source for the photoelectric conversion element.

  When the photoelectric conversion element or the switching element is formed of a thin film element, the drive circuit section may be composed of at least one LSI chip using single crystal silicon, and the readout circuit section is similarly made of transistor single crystal silicon. It is preferable to use at least one LSI chip used.

  Note that FIG. 2 shows a 3 × 3 = 9 pixel two-dimensional photoelectric conversion device for the sake of simplicity, but an actual imaging device is configured with a larger number of pixels depending on the application.

  In the present embodiment, each of the matrix signal wirings M1 to M3 is connected to two operational amplifiers such as (E1, B1), (E2, B2), (E3, B3). The number is determined as appropriate, and is not limited to the number in the present embodiment, and there may be other operational amplifiers.

  Hereinafter, in all the embodiments, the number of operational amplifiers is not limited to that of the embodiments, and there may be other operational amplifiers in the circuit other than those illustrated.

FIG. 3 is a timing chart for explaining the operation of the imaging apparatus according to the present embodiment.
3, when the first of the voltage pulse for transfer gate driving line G1 from the shift register SR1 where a gate line driving circuit 102 is applied to the time t1, the switching element T _1-1, T _{1 -2,} T _1-3 is turned ON, the first row of the photoelectric conversion elements S _1-1, S _1-2, S _1-3 and the matrix signal wirings M1~M3 conducts. Since the matrix signal wirings M1 to M3 are connected to the inverting input terminals (−) of the first operational amplifiers E1 to E3, the potentials V1 to V3 of the matrix signal wirings M1 to M3 are set to the normal input terminal voltage VREF1. equal. Therefore the photoelectric conversion elements S _1-1 by the above transfer operation, S _1-2, the signal charges of the S _1-3 is transferred to the integrator integrating capacitor Cf1, the output voltage Vo1~Vo3 of the first operational amplifier E1~E3 Each When the signal charge amount is Qi (i = 1 to 3), it changes as follows.

Voi = VREF1-Qi / Cf1 (i = 1-3) (10)
As is clear from the comparison between the above expression (10) and the above expression (5), the output voltage of the imaging device according to the present invention does not depend on the load capacitances C1 to C3 of the matrix signal wiring. Here, for example, when the capacitance value of the integration capacitor Cf1 is made equal to the interelectrode capacitance Cs in the photoelectric conversion element, the output voltage becomes the expression (11), and the signal component Qi / Cs = Vs becomes equal to the expression (7). That is, even in the above configuration, the S / N with respect to the latter-stage noise is not deteriorated.

Voi = VREF1-Qi / Cs = VREF1-Vs (11)
Here, for simplicity, Cf1 = Cs, but this is not restrictive. For example, if Cf1 <Cs, the signal voltage is further increased, and the S / N with respect to the latter-stage noise becomes more advantageous.

The subsequent operation is the same as that of the conventional example shown in FIG. 30, and the sampling switches Sn1 to Sn3 are turned ON for t2 time by the SMPL pulse, and the signal is transferred to the sampling capacitors C _{L1 to} C _L3 . Subsequently, the read switches Sr1 to Sr3 are sequentially turned on for every t3 time by the read pulses Sp1 to Sp3 from the shift register SR2 which is the sequential read switch drive circuit unit 104, whereby the buffer amplifiers B1 to B3 are turned on. Through the output buffer amplifier 105 and digitized by the A / D conversion circuit unit 106. Thereafter, the control signal CRES is applied to the reset switches S _{RES1 to} S _RES3 for t4 hours to reset the integration capacitor Cf1 and prepare for the read operation of the next row. Hereinafter Similarly, by sequentially driving the gate driving line G2, G3 from the shift register 102, repeatedly read all the pixel data of the photoelectric conversion elements S _2-1 to S _3-3.

  As described above, according to the present embodiment, the matrix signal wirings M1 to M3 are connected to the inverting input terminals of the first operational amplifiers E1 to E3, so that the load capacitors C1 to C1 of the matrix signal wirings M1 to M3 are connected. Since the signal charge is transferred to the integration capacitor Cf1 without depending on C3, the reading circuit unit 103 can be commonly applied to photoelectric conversion circuit units having various pixel arrays.

  Further, according to the present embodiment, the signal charge output from the first operational amplifier is further input to another operational amplifier (buffer amplifiers B1 to B3 in the present embodiment), and therefore the output signal charge is appropriately used. It became possible to perform impedance conversion according to. In addition to the buffer amplifiers B1 to B3, it is possible to amplify the signal charge output from the first operational amplifier by arranging another operational amplifier, for example.

  The signal source used in the present invention, including the embodiments described above and the following embodiments, includes a conversion element that generates a charge by receiving light and / or radiation, and a sensor that generates a signal by sensing heat. And a sensor that senses sound and emits a signal.

  When a conversion element that generates light by receiving light and / or radiation is used as a signal source as in an imaging device, a CMOS, CCD, bipolar, or thin film is used as a circuit unit having the conversion element. A type image sensor can be used.

  In the case of capturing an image of radiation such as X-rays, an imaging device can be configured by combining a light emitting body called a phosphor or scintillator that receives visible radiation and emits visible light with a photoelectric conversion element. Specifically, a radiation imaging apparatus can be configured by providing a light emitter such as cesium iodide or gadolinium sulfide oxide on a circuit substrate on which a pixel array including a thin film photoelectric conversion element and a thin film transistor is formed.

  In the imaging apparatus and radiation imaging system of the present invention, radiation includes X-rays, α, β, γ rays, and the like, and light is electromagnetic waves in a wavelength region that can be detected by a photoelectric conversion element, and includes visible light.

(Third embodiment)
FIG. 4 is a circuit diagram of a signal transfer apparatus showing a third embodiment of the present invention. In FIG. 4, R9, R10, R11, and R12 are resistance elements, and K1, K2, and K3 are inverted when the output signals from the first operational amplifiers E1, E2, and E3 are connected to the inverting input terminal via the resistance element R9. A second operational amplifier VREF2 ′ having a resistance element R10 connected between the input terminal and the output terminal, VREF2 ′ is set to the normal input terminals of the second operational amplifiers E1 to E3 via the resistance elements R11 and R12. 2 reference voltage. In this configuration, a voltage obtained by dividing the reference power source VREF2 ′ by the resistance elements R11 and R12 is applied to the normal input terminal of the second operational amplifier. The amplification factor H of the second operational amplifiers K1 to K3 is a value determined by the resistance elements R9 and R10.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(Fourth embodiment)
FIG. 5 is a circuit diagram of an imaging apparatus according to the fourth embodiment of the present invention. In FIG. 5, a 3 × 3 = 9 pixel two-dimensional photoelectric conversion device is shown for the sake of simplicity, but an actual imaging device is configured with a larger number of pixels depending on the application. Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The circuit configuration shown in FIG. 5 is different from the circuit configuration of FIG. 2 in that inverting operational amplifiers K1 to K3 having an amplification factor H are formed between the first operational amplifiers E1 to E3 and the buffer amplifiers B1 to B3. A plurality of inverting operational amplifiers are provided.

  By using the configuration of the present embodiment, an imaging apparatus that amplifies and outputs the output signals from the first operational amplifiers E1 to E3 without depending on the load capacitors C1 to C3 of the matrix signal wirings M1 to M3. It became possible to provide.

(Fifth embodiment)
FIG. 6 is a circuit diagram of a signal transfer apparatus showing a fifth embodiment of the present invention. In FIG. 6, CC1 to CC3 are capacitive elements that allow only the AC component of the signal to pass between the output terminals of the first operational amplifiers E1 to E3 and the sampling switches Sn1 to Sn3, and F1 to F3 are capacitive elements at the inverting input terminal. The second operational amplifier to which CC1 to CC3 are connected, Cf2 is a second integration capacitor connected between the inverting input terminal and the output terminal of each of the second operational amplifiers F1 to F3, and Sd1, Sd2, and Sd3 are the respective integration capacitors. A second reset switch that resets Cf2, DRES is a pulse signal that controls the second reset switches Sd1 to Sd3, and VREF2 is a reference voltage that is set at the normal input terminals of the second operational amplifiers F1 to F3.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(Sixth embodiment)
FIG. 7 is a circuit diagram of an imaging apparatus according to the sixth embodiment of the present invention. Although FIG. 7 shows a two-dimensional photoelectric conversion device with 3 × 3 = 9 pixels for the sake of simplicity, an actual imaging device is configured with more pixels depending on the application.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The circuit configuration shown in FIG. 7 is different from the circuit configuration shown in FIG. 5 in that capacitive elements CC1 to CC3 are arranged instead of the resistance elements R9 and R10 constituting the second operational amplifiers K1 to K3 in FIG. The amplifiers F1 to F3 are formed. In FIG. 7, one electrode of each of the capacitive elements CC1 to CC3 is connected to the output terminals of the first operational amplifiers E1 to E3, and the other electrode is connected to the inverting input terminals (−) of the second operational amplifiers F1 to F3. .

  FIG. 8 is a timing chart for explaining the operations of the first operational amplifiers E1 to E3 to the second operational amplifiers F1 to F3 and the second reset switches Sd1 to Sd3 of the imaging apparatus of FIG.

In a reset operation in preparation for the reading of the next row after the reading of a certain row is completed, the control signal CRES is applied, the first reset switches S _{RES1 to} S _RES3 are turned on, and both ends of the first integration capacitor Cf1 are short-circuited. Thus, the signal charge of the previous row accumulated in the first integration capacitor Cf1 is reset. At this time, since the first operational amplifiers E1 to E3 operate as voltage followers, the potential of the output terminal P1 becomes VREF1. However, the output voltage at this time fluctuates due to thermal noise due to the ON resistance of the reset switches S _{RES1 to} S _RES3 , and this fluctuation occurs at the moment when the reset period ends and the first reset switches S _{RES1 to} S _RES3 are turned off. It accumulates in the first integration capacitor Cf1 and remains as so-called KTC noise. The KTC noise Rn (Vrms) depends only on the capacitance value of the first integration capacitor Cf1, and is expressed by the following equation.

Rn = (KT / Cf1) ^1/2 (12)
Here, K is a Boltzmann constant, T is an absolute temperature, and Cf1 is a capacitance value of the first integration capacitor. On the other hand, KTC noise caused by the ON resistance of the switching element even when transferring a signal charge by the switching element T _1-1 through T _3-3 from the inter-electrode capacitance Cs of the photoelectric conversion elements S _1-1 to S _3-3 Generated due to thermal noise that is transmitted and superimposed on the signal charge. Here, for example, if Cf1 = Cs as in the first embodiment, the noise amounts of both are equal, and the reset noise (KTC noise) of the first integration capacitor Cf1 cannot be ignored. If Cf1> Cs, the reset noise of the first integration capacitor Cf1 itself becomes small, but at this time, the signal voltage Qi / Cf1 also becomes small, so the S / N is not improved. In the waveform P1 of FIG. 8 (the waveform of the output terminal P1), the amount of deviation from the first reference voltage VREF1 after the control signal CRES is turned off (described as an error in FIG. 8) is due to the reset noise of the first integration capacitor Cf1. Is.

  On the other hand, the reset switches Sd1 to Sd3 connected between the inverting input terminals (−) and the output terminals of the second operational amplifiers F1 to F3 are controlled by the pulse signal DRES, and the pulse signal DRES is turned on almost simultaneously with the control signal CRES. Then, it is turned off after the control signal CRES. During a period in which the pulse signal DRES is applied, the reset switches Sd1 to Sd3 are turned ON to reset the second integration capacitor Cf2, the second operational amplifiers F1 to F3 perform a voltage follower operation, and the potential of the output terminal P2 is VREF2. It becomes. Immediately after the control signal CRES is turned off, the pulse signal DRES is turned on, so that the potential of the output terminal P2 does not change, and reset noise of the first integration capacitor Cf1, which is a DC component, is accumulated in the capacitive elements CC1 to CC3. This state is maintained even if the pulse signal DRES is turned OFF, and then the second calculation is performed in response to the gate drive pulse G2 being applied by the transfer operation of the next row and the signal charge being transferred to the first integration capacitor Cf1. The output voltage P2 of the amplifiers F1 to F3 (the output voltage of the output terminal P2) changes. The potentials of the output terminals P1 and P2 (shown as P1 and P2) at this time are respectively expressed by the following equations.

P1 = VREF1-Qi / Cf1 + Rn (13)
P2 = VREF2 + (Qi / Cf1) × (CCi / Cf2) (14)
(I = 1 to 3)
Here, the reset noise Rn of the first integration capacitor Cf1 is added to the equation (13).

  Comparing the equations (13) and (14), it can be seen that only the AC component of the signal appears in the output voltages of the second operational amplifiers F1 to F3, and the reset noise of the first integration capacitor Cf1 is cancelled. Further, as is clear from the equation (14), the signal voltage is gained by the ratio between the capacitive elements CC1 to CC3 and the second integration capacitor Cf2. Here, if CCi (i = 1 to 3)> Cf2, the S / N for the noise after the sampling switches Sn1 to Sn3 becomes more advantageous. Note that reset noise (KTC noise) of the second integration capacitor Cf2 is actually superimposed on the output voltage P2 (voltage at the output terminal P2), but the amount of noise becomes Cf2 / CCi when converted to input, As described above, since the gains of the second operational amplifiers F1 to F3 are determined only by the capacitance ratio, the capacitance value of the second integration capacitor Cf2 can be made sufficiently larger than that of the first integration capacitor Cf1, and as a result, The reset noise of the two integration capacitor Cf2 can be ignored. Therefore, this is omitted in the equation (14).

  The subsequent operation is the same as in FIG.

  As described above, according to this embodiment, in the readout circuit unit 103, the capacitive element CC1 that allows only the AC component of the signal to pass between the output terminals of the first operational amplifiers E1 to E3 and the sampling switches Sn1 to Sn3. ~ CC3 and the second operational amplifiers F1 to F3 are connected, and the second reset switches Sd1 to Sd3 are arranged between the inverting input terminals and the output terminals of the second operational amplifiers F1 to F3, so that the signal charges are transferred. Since the reset noise of the first integration capacitor Cf1 can be removed, a high S / N photoelectric conversion device can be provided.

  Here, when the fourth embodiment and the sixth embodiment of the present invention are compared, the configuration shown in the fourth embodiment is effective in itself, but for the reasons shown in the following 1) and 2), the configuration shown in FIG. As in the case of the two operational amplifiers F1 to F3, an operational amplifier having a configuration in which a signal is transmitted by a capacitive element instead of a resistive element is a more preferable configuration.

  1) With the configuration of FIG. 7, the reset noise of CF1 can be removed.

  As is clear from FIG. 5, the outputs of the first operational amplifiers E1 to E3 in the first stage are connected to the second operational amplifiers K1 to K3 in the subsequent stage through the resistance element R9, so that a direct current component can pass therethrough. Therefore, the reset noise Rn of the first integration capacitor Cf1 superimposed on the outputs of the first stage operational amplifiers E1 to E3 as shown in the equation (13) is also amplified by the second stage second operational amplifiers K1 to K3. Therefore, it is disadvantageous in terms of S / N, and a separate noise cancellation circuit is required.

Rn = (KT / Cf1) ^1/2 (12)
P1 = VREF1 − Qi / Cf1 + Rn (13)
The output voltages P1 of the first operational amplifiers E1 to E3 in the first stage shown by the equation (13) are amplified as follows by the second operational amplifiers K1 to K3 and F1 to F3 in the subsequent stages in FIGS. .

That is, in the configuration of FIG. 7, the output voltage P2 of the operational amplifiers F1 to F3 in the next stage is
P2 = VREF2 + (Qi / Cf1) x (CCi / Cf2) (i = 1 to 3) (14)
On the other hand, in the configuration of FIG. 5, if the output voltages P2 of the second operational amplifiers K1 to K3 in the next stage are R11 and R12 equal to R9 and R10, respectively.
P2 = (R10 / R9) x (VREF2 '-VREF1) + (R10 / R9) x (Qi / Cf1 + Rn) (15)
It is expressed. Comparing the equations (14) and (15), it can be seen that the reset noise Rn of the integration capacitor Cf1 is multiplied by the gain (R10 / R9) and appears in the output in the configuration of FIG.
In addition, in the equations (14) and (15)
CCi / Cf2 = R10 / R9 (i = 1 to 3) (16)
VREF2 = (R10 / R9) x (VREF2 '-VREF1) (17)
When the capacitance value, the resistance value, and the reference voltage VREF2 ′ are determined so as to be equal to each other, an equal output voltage is obtained for the same signal charge Qi. FIGS. 9 and 10 show the outputs P1 of the first operational amplifiers E1 to E3 in the first stage shown in FIGS. 5 and 7, respectively, and the output voltages P2 from the second operational amplifiers K1 to K3 and F1 to F3 in the subsequent stages. FIG.

  2) With the configuration of FIG. 7, the current consumption of the system does not change even with an arbitrary signal level.

In the configuration of FIG. 5, a current flows through the potential difference between both ends of a resistor R9 connected between the output terminals of the first operational amplifiers E1 to E3 in the first stage and the inverting input terminals of the second operational amplifiers K1 to K3 in the next stage. The value changes. That is, the inverting input terminal voltage of the second operational amplifiers K1 to K3 in the next stage is equal to the normal input terminal voltage, and the voltage obtained by dividing the second reference voltage VREF2 ′ by the resistors R11 and R12 is always applied and does not change. . On the other hand, since the voltage at the other end of the resistor R9 varies with the signal charge Qi as shown in the equation (13), the signal current component i9 flowing through the resistor R9 is
i9 = (1 / R9) x (Qi / Cf1) (18)
It is expressed. This means that, for example, in an imaging apparatus, the current consumption of the system increases when the image to be captured is bright and decreases when the image is dark.

  In the present embodiment, the case of 3 × 3 pixels is shown for simplicity, but the medical X-ray imaging apparatus described above has 4000 columns of matrix signal wirings. For this reason, even if the current change per one matrix signal wiring is slight, it becomes a large current change as a whole, which is not preferable.

  As described above, when a plurality of operational amplifiers are connected in cascade to amplify a signal charge, each inverting operational amplifier is connected via a capacitive element as in the sixth embodiment of the present invention, and the charge is moved. It is effective to allow signal transmission. Although the above example has been described using an example in which two stages of inverting operational amplifiers are cascade-connected, the number of inverting operational amplifiers to be cascade-connected is not limited to this.

(Seventh embodiment)
FIG. 11 is a circuit diagram of a signal transfer apparatus showing a seventh embodiment of the present invention. In FIG. 11, R1 to R3 are resistance elements arranged between the first operational amplifiers E1 to E3 and the capacitive elements CC1 to CC3, and R4 to R6 are sampling switches Sn1 to Sn3 and sampling capacitors C _{L1 to} C _L3 . It is a resistance element arranged between them.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(Eighth embodiment)
FIG. 12 is a circuit diagram of an imaging apparatus according to the second embodiment of the present invention. 12 is different from FIG. 7 in that resistance elements R1 to R3 and resistance elements R4 to R6 are arranged.

  In general, random noise can be defined as a collection of noises having various frequency components, and the total amount of noise observed is a value obtained by integrating fluctuation from an average value per unit frequency in the passband of the system. Therefore, a detection system having a frequency band higher than necessary, that is, a frequency band higher than a pass band sufficient for transferring signal charges obtained by photoelectric conversion may deteriorate the S / N of the system.

In FIG. 12, the noise of the first operational amplifiers E1 to E3 is limited by the bandwidth of the operational amplifier itself and appears at its output. This noise first appears at the moment when the first reset switches S _{RES1 to} S _RES3 are turned off. Terminated at CC1 to CC3. When the signal charge is transferred, it is superimposed on the signal voltage again and further subjected to the band limitation of the second operational amplifiers F1 to F3, and then stored in the sampling capacitors C _{L1 to} C _L3 . Since the above events are independent events, noise charges of √2 times the noise of the first operational amplifiers E1 to E3 are accumulated on the sampling capacitors C _{L1 to} C _L3 . Further, the noises of the second operational amplifiers F1 to F3 are also terminated by the sampling capacitors C _{L1 to} C _L3 due to their own band limitation. The amount of noise accumulated on the sampling capacitors C _{L1 to} C _L3 is sufficient if the bands of the first operational amplifiers E1 to E3 and the second operational amplifiers F1 to F3 are optimally designed with respect to the pass band of the signal. However, when an operational amplifier is actually designed and manufactured, it is not easy to make a desired band with a simple configuration and high accuracy. Therefore, in the present embodiment, the resistance elements R1 to R3 and the capacitive elements CC1 to CC3 constitute a first low-pass filter having a desired cutoff frequency fc1 (Hz), and the band of the first operational amplifiers E1 to E3 is limited. is doing. Further, the resistance elements R4 to R6 and the sampling capacitors C _{L1 to} C _L3 constitute a second low-pass filter having a desired cutoff frequency fc2 (Hz), and the band of the second operational amplifiers F1 to F3 is limited. Yes. Here, the cut-off frequencies fc1 and fc2 are each expressed by the following equations.

fc1 = 1 / (2πCCi · Ri) (i = 1 to 3) (19)
fc2 = 1 / (2πC _Li · Rj) (i = 1 to 3, j = 4 to 6) (20)
As described above, according to the present embodiment, the capacitive element and the first-order low-pass filter can be easily configured by inserting the resistance element, and the high-frequency noise component of each operational amplifier can be cut off. It is possible to provide a high S / N photoelectric conversion device without conversion.

(Ninth embodiment)
The KTC noise described above and the thermal noise generated by the transistor elements and resistance elements constituting the operational amplifier depend on the absolute temperature T. In addition, it is known that when the ambient temperature rises, the dark current component increases in the photoelectric conversion circuit section and becomes fixed pattern noise, both of which are factors that degrade S / N. Therefore, it is required to suppress the power consumption of the apparatus itself and to minimize heat generation. Here, taking the above-mentioned chest X-ray imaging apparatus having 4000 × 4000 pixels as an example, since there are 4000 rows of matrix signal wirings, the total number of operational amplifiers connected thereto is a huge number, and a readout circuit The unit 103 serves as a main heat source of the photoelectric conversion device, and power saving is required.

  FIG. 13 is a circuit diagram of a signal transfer apparatus showing a ninth embodiment of the present invention. In FIG. 13, H1 is a third operational amplifier in which the common outputs of the read switches Sr1 to Sr3 are connected to the inverting input terminal, and Cf3 is a first operational amplifier connected between the inverting input terminal and the output terminal of the third operational amplifier H1. 3 is an integration capacitor, St1 is a third reset switch for resetting the integration capacitor Cf3, Sx1 is a drive pulse for controlling the reset switch St1, and VREF3 is a third reference voltage set at the normal input terminal of the third operational amplifier H1. .

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(10th Embodiment)
FIG. 14 is a circuit diagram of an imaging apparatus according to the tenth embodiment of the present invention. Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

14 is different from FIG. 12 in that the buffer amplifiers B1 to B3 connected immediately after the sampling capacitors C _{L1 to} C _L3 are deleted, and the sampling capacitors C _{L1 to} C _L3 are directly connected to the read switches Sr1 to Sr3. In addition, the number of operational amplifiers in the blocks connected to the matrix signal wirings M1 to M3 and processing signals in parallel is reduced from three to two per line, and the last after the read switches Sr1 to Sr3. The output buffer amplifier 105 is replaced with the third operational amplifier H1.

  With the above configuration, one operational amplifier is reduced per line. For example, when a chest X-ray imaging apparatus is taken as an example, 4000 analog operational amplifiers are conveniently reduced, resulting in a great power saving effect. .

  The read operation after sampling according to the present embodiment will be described with reference to the timing chart of FIG. The operation before sampling is the same as that in the sixth embodiment shown in FIG.

The third reset switch St1 is turned ON for t5 hours between the readout pulses of the readout readout pulses Sp1 to Sp3 by the drive pulse Sx1, thereby resetting the third integration capacitor Cf3. Since the third operational amplifier H1 operates as a buffer amplifier while the third reset switch St1 is ON, its output voltage Vout is equal to the third reference voltage VREF3. After the sampling operation is completed, the read operation is started. The first read pulse Sp1 is applied, and the signal charge accumulated in the sampling capacitor C _L1 is read out to the third integration capacitor Cf3. When the reading of the first signal charge is completed, the third reset switch St1 is once turned ON, and the third integration capacitor Cf3 is reset. Next, the second signal accumulated in the sampling capacitor C _L2 by the second readout pulse Sp2 is again read out to the third integration capacitor Cf3, and this operation is repeated thereafter. The output voltage Vout at this time is expressed by the following equation.

Vout = {(1 + Cf3 / C Li) VREF3- (Cf3 / C Li) VREF2}
_{- (Cf3 / C Li) (} CCi / Cf2) (Qi / Cf1) (i = 1~3) (21)
In the above equation, the second term is a signal component, Qi is the signal charges generated in the photoelectric conversion elements S _1-1 to S _3-3. The first term in the above equation indicates the output voltage level in the dark, but the selection of the second reference voltage VREF2 and the third reference voltage VREF3 is arbitrary within the range allowed by the dynamic range. For example, if VREF2 = VREF3, the first term becomes VREF3, and equation (21) can be simplified. Further, it is possible to apply a gain ratio Cf3 / C _Li also third integral capacitor Cf3 and the sampling capacitor C _Li in the third operational amplifier H1 As apparent from the above equation.

As described above, according to the present embodiment, in the readout circuit unit, the sampling capacitor C _Li is directly connected to the readout switch, and the signal is read out from the common output of the readout switch to the integration capacitor of the operational amplifier. The number of operational amplifiers connected to each matrix signal wiring and processing signals in parallel is reduced, and an imaging device with low power consumption can be provided.

(Eleventh embodiment)
FIG. 16 is a circuit diagram of a signal transfer apparatus showing an eleventh embodiment of the present invention. In FIG. 16, Cf10 is an integration capacitor as an integration capacitor connected in parallel with the first integration capacitor Cf1 connected to the first operational amplifiers E1 to E3, Sg is a switch for turning ON / OFF the integration capacitor Cf10, GAIN Is an external control signal for controlling the switch Sg.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(Twelfth embodiment)
FIG. 17 is a circuit diagram of an imaging apparatus according to the twelfth embodiment of the present invention. Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  17 is different from FIG. 14 in that an integration capacitor Cf10 connected to the first operational amplifiers E1 to E3 and a switch Sg that is turned ON / OFF by an external control signal GAIN are connected in parallel. is there.

  Therefore, the present embodiment is different from the other embodiments in that the integrating capacitor Cf10 and the switch Sg act to vary the signal gain. That is, the output voltages Voi and Voi ′ (i = 1 to 3) of the first operational amplifiers E1 to E3 when Sg is turned ON / OFF by the external control signal GAIN are expressed as follows, where the signal charge is Qi. Is done.

Voi = VREF1-Qi / (Cf1 + Cf10)
(I = 1 to 3) (22)
Voi ′ = VREF1-Qi / Cf1 (i = 1-3) (23)
As apparent from the comparison between the two equations, when the switch Sg is turned ON, the integration capacitor Cf1 and the integration capacitor Cf10 are connected in parallel, so that the signal voltage impedance-converted by the first operational amplifiers E1 to E3 with respect to the same signal charge Qi. Since the signal becomes smaller, the signal gain can be changed.

  As shown in the present embodiment, the function of varying the signal gain is effective in using a wide dynamic range. That is, for example, in a higher-definition photoelectric conversion device, the pixel charge is reduced, and thus the signal charge must be reduced. In this case, if the signal gain is set to be increased by the external control signal GAIN, A / D conversion is performed. The input dynamic range of the circuit unit 106 can be fully used. As a result, the readout circuit unit 103 according to the present embodiment can be applied not only to a pixel array but also to photoelectric conversion devices having different pixel sizes.

  In addition, each photoelectric conversion element causes individual differences in photoelectric conversion output due to variations in the manufacturing process, but the gain of the photoelectric conversion device according to the present embodiment can be controlled by a signal from the outside in the readout circuit unit 103. Therefore, output variations can be easily corrected, and costs can be reduced by reducing external parts for correction and improving yield.

  In the present embodiment, for simplicity, the switch Sg and the integrating capacitor Cf10 are paired and the gain switching is performed in two stages. However, the present invention is not limited to this. If a plurality of switches and capacitive elements are prepared and the gain is controlled by a plurality of external control signals, finer gain adjustment is possible.

  In the present embodiment, only the first operational amplifiers E1 to E3 have variable gains. However, the second operational amplifiers F1 to F3 and the third operational amplifier H1 can vary the gains with the same configuration. An effect is obtained.

(13th Embodiment)
As the pixel arrangement increases and the number of pixels in the photoelectric conversion unit increases, the time required to read out each pixel is shortened when all the pixels are read out within a certain period of time. For example, in the above-mentioned chest X-ray imaging apparatus having 4000 × 4000 pixels, considering that a still image is read out by one frame per second, the time allowed for reading out one pixel is 1 / (4000 × 4000) = 62. It can be seen that this is an extremely short time of 5 × 10 ⁻⁹ seconds. In general, instead of serially outputting all the pixels, for example, all the pixels are divided into four (in 2000 × 2000 pixel units), and this is processed in parallel to reduce the readout speed of each pixel. In order to take advantage of “immediateness”, which is one of the features of medical X-ray digital cameras, in response to higher-definition still image output and high-frame-rate moving image output, It is important to improve the reading speed itself.

In the ninth embodiment, there is only one operational amplifier that reads signals from the sampling capacitor C _{Li in} the third operational amplifier H1, so that reading per pixel is performed at each ON time t3 of the reading pulses Sp1 to Sp3. In addition, a time t5 when the third reset switch St1 is turned on is required to reset the third integration capacitor Cf3 in order to read the next signal. Here, the ON time t3 is a time required for the third operational amplifier H1 to sufficiently respond to the amount of charge transferred from the sampling capacitors C _{L1 to} C _L3 to the third integration capacitor Cf3, and the third operational amplifier H1. Determined by performance. On the other hand, the time t5 is a time necessary for discharging the charge on the third integration capacitor Cf3. To sufficiently reset the previous charge, t5 ≧ 5τ (τ is the capacitance value of the third integration capacitor Cf3 and the third The time constant determined by the product of the ON resistance of the reset switch St1 is required. As an example, if the capacitance value of the third integration capacitor Cf3 is 10 pF and the ON resistance of the third reset switch St1 is 1 kΩ, the time constant τ is 10 × 10 ⁻⁹ seconds, which is necessary for resetting the third integration capacitor Cf3. Time t5 is 5 times 50 × 10 ⁻⁹ seconds. Therefore, the time t3 remaining for serially reading out the output of 4000 × 4000 pixels in 1 second is 62.5 × 10 ⁻⁹ −50 × 10 ⁻⁹ = 12.5 × 10 ⁻⁹ seconds, which is very high speed. The third operational amplifier H1 that operates in the above must be prepared. Here, in order to reduce the time constant, it is conceivable to reduce the capacitance value of the third integration capacitor Cf3, for example, 1 pF. However, reducing the capacitance value of the third integration capacitor Cf3 can reduce the reset noise ( (KTC noise) is increased, which is not preferable. There is also a limit to reducing the ON resistance of the third reset switch St1. As described above, the ninth embodiment is desired to be improved in a system that requires multiple pixels and high-speed readout.

  FIG. 18 is a circuit diagram of a signal transfer apparatus showing a seventh embodiment of the present invention in view of the above points.

  In FIG. 18, H1 is a third operational amplifier having the same configuration as the third operational amplifier H1 in the ninth embodiment in which the common output of the read switches Sr1 and Sr3 is connected to the inverting input terminal, and H2 is a read switch. A third operational amplifier in which the common output of Sr2 and Sr4 is connected to the inverting input terminal, Cf3 ′ is a third integration capacitor connected between the inverting input terminal and the output terminal of the third operational amplifier H2, and St2 is a third operational amplifier. A reset switch for resetting the integration capacitor Cf3 ′, Sx2 is a driving pulse for controlling the reset switch St2, VREF3 is a third reference voltage set at the normal input terminal of the third operational amplifier H1, H2, and Sc1 is a third operational amplifier. An output selection switch for connecting H1 and the A / D conversion circuit unit 106, Ls1 is a drive pulse for controlling the output selection switch Sc1, and Sc2. Is an output selection switch for connecting the third operational amplifier H2 and the A / D conversion circuit unit 106, and Ls2 is a drive pulse for controlling the output selection switch Sc2.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(14th Embodiment)
FIG. 19 is a circuit diagram of an imaging apparatus according to the fourteenth embodiment of the present invention. Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

19 differs from FIG. 14 in that read switches Sr1 to Sr4 for reading signals from sampling capacitors C _{L1 to} C _L4 are connected to the third operational amplifier H1 and the third operational amplifier H2 every other column. The outputs of the third operational amplifiers H1 and H2 are connected to the output selection switches Sc1 and Sc2, respectively, and the other terminals of the output selection switches Sc1 and Sc2 are connected in common and input to the A / D conversion circuit unit 106. It is.

  FIG. 20 is a timing chart for explaining operations after sampling according to the present embodiment. The operation before sampling is the same as that of the sixth embodiment shown in FIG.

When the reading operation is started after the sampling operation is completed, first, the signal read from the sampling capacitor C _L1 by applying the first reading pulse Sp1 is read to the third integration capacitor Cf3 of the third operational amplifier H1. At this time, the reset switch St2 of the third integration capacitor Cf3 ′ of the third operational amplifier H2 is turned on by the drive pulse Sx2, and the third integration capacitor Cf3 ′ is in a reset state. The output selection switches Sc1 and Sc2 connected to the output terminals of the third operational amplifiers H1 and H2, respectively, have the output selection switch Sc1 turned on and the output selection switch Sc2 turned off by the drive pulses Ls1 and Ls2. The output of the third operational amplifier H1 is selected and input to the A / D conversion circuit unit 106. When the reading of the first signal is finished, the polarity of the reset switches St1, St2 of the third integration capacitors Cf3 and Cf3 ′ and the drive pulses Sx1, Sx2, Ls1, Ls2 of the output selection switches Sc1, Sc2 are inverted, and the third The operational amplifier H1 enters the reset state, and prepares for the third signal readout from the sampling capacitor C _L3, and the third operational amplifier H2 is selected for the A / D conversion circuit unit 106 and becomes conductive. Then, the second signal accumulated in the sampling capacitor C _L2 by the second readout pulse Sp2 is read out to the third integration capacitor Cf3 ′ of the third operational amplifier H2, and a signal is output.

  Thereafter, this operation is repeated, and the signal of each pixel is alternately output through two paths of the third operational amplifiers H1 and H2 every other column. For this reason, the integration capacitor reset period t5 does not appear in the serial output input to the A / D conversion circuit unit 106, and the time required for readout in units of pixels is only t3, so that a very high-speed operational amplifier is prepared. There is no need. In the present embodiment, two readout paths are used. However, the present invention is not limited to this, and it is needless to say that three or more systems may be used as necessary.

  As described above, according to the present embodiment, by preparing a plurality of readout paths after sampling, the other operational amplifier is reset in the output period of one operational amplifier to prepare for the next signal readout. Therefore, the signal output can be read at high speed without intermittent.

  In the present embodiment, the driving pulses Sx1 and Sx2 are alternately turned ON and OFF, and the output selection switches Sc1 and Sc2 are alternately selected by the driving pulses Ls1 and Ls2, so that the third operational amplifiers H1 and H2 The signal is alternately output to the A / D conversion circuit unit 106, but the method is not limited to this.

  For example, it is possible to cause the A / D conversion circuit unit 106 to alternately output signals by simultaneously turning on the drive pulses Sx1 and Sx2 and alternately controlling the output selection switches Sc1 and Sc2 only with the drive pulses Ls1 and Ls2. It is.

However, when the drive pulses Sx1 and Sx2 are turned on at the same time and signals are transmitted simultaneously, the outputs of the third operational amplifiers H1 and H2 also change simultaneously. Switching this with the output selection switches Ls1 and Ls2 and outputting it to the A / D conversion circuit unit 106 means that the outputs of the third operational amplifiers H1 and H2 are turned into the A / D conversion circuit after Sp1 and Sp2 are turned on. There will be a difference in the time until the data is taken into the unit 106.
When the reading speed is high, for example, when Ls1 is turned ON first, the output of the third operational amplifier H1 is taken into the A / D conversion circuit unit 106 before sufficiently reaching the desired voltage, and the third operational amplifier H2 After that, a further time elapses and the voltage is taken in after reaching a desired voltage. As a result, even if the signals of the third operational amplifiers H1 and H2 are the same, a striped pattern may appear as a picture. It is done.

  Therefore, since a high reading speed is required year by year, the present embodiment in which the drive pulses Sx1 and Sx2 are alternately turned on is preferable.

(Fifteenth embodiment)
FIG. 21 is a circuit diagram of a signal transfer apparatus having a suitable operational amplifier in which the signal charge reading speed is improved in the operational amplifier constituting the signal transfer apparatus of the present invention.

  In FIG. 21, 3 is an operational amplifier, C3 is a phase compensation capacitor disposed in the operational amplifier 3, SW3 is a switch for switching the phase compensation capacitor C3, Q1 to Q13 are transistors, and 4 is a first conductivity type transistor Q13. A level shift circuit comprising transistors Q11 and Q12 of the second conductivity type, a source circuit of Q13, a switching circuit constituted by a phase compensation capacitor C3 and a switch SW3, 5 a control circuit for controlling the switching circuit 4, and 6 a switching circuit 4 An odd-numbered inverter delay circuit constituting a part of the control circuit 5, 7 a 2-input AND circuit constituting a part of the control circuit 5 of the switching circuit 4, 50 a normal input terminal of the operational amplifier 3, and 60 The inverting input terminal of the operational amplifier 3, I1 is a constant current source, and Vv1, Vv2, and Vv3 are constant voltage sources.

Here, the gate of the transistor Q12 constituting the switching circuit 4 is connected to a power supply VREF1 that supplies a reference voltage. The control signal CRES for driving the reset switch S _RES1 is connected to one input terminal of the inverter delay circuit 6 and the 2-input AND circuit, and the output of the inverter delay circuit 6 is connected to the other input terminal of the 2-input AND circuit. Has been.

  The inverter delay circuit 6 of the control means 5 may be composed of one or more shift registers, and the inverting output terminal of the final stage shift register may be connected to the input terminal of the AND gate of the control circuit 5. . Further, the inverter delay circuit of the control circuit 5 is constituted by a time constant circuit such as an RC circuit and an inverter connected in series thereto, and the output terminal of the inverter is connected to the input terminal of the AND gate of the control means 5. Also good.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(Sixteenth embodiment)
FIG. 22 is a circuit diagram of an imaging apparatus according to the sixteenth embodiment of the present invention. Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

In FIG. 22, C _1-1 , C _2-1 , and C _3-1 are capacitance values of the interelectrode capacitance 111 of the photoelectric conversion elements S _1-1 , S _2-1 , and S _3-1 , and Q _{1 −1} , Q _2-1 , and Q _3-1 are signal charges that are photoelectrically converted by the photoelectric conversion elements S _1-1 , S _2-1 , and S _3-1 and accumulated in the interelectrode capacitance 111.

Also, in FIG. 22, for easy comparison with the other embodiments in this specification, photoelectric conversion elements S _1-1 and S ₂₋ are used as the operational amplifier 3 as in the first operational amplifier E1 used in FIG. _{Although the first} stage operational amplifier is arranged for ₁ and S _3-1 , the arrangement location of the operational amplifier of the present invention is not limited to this. For example, the present invention can be applied to the second operational amplifiers F1 to F3 and / or the third operational amplifier H1 shown in FIG.

  Here, the operation of the imaging apparatus of the present invention will be described with reference to FIG.

First, the photoelectric conversion elements S _1-1 as a light receiving region, S _2-1, resulting signal charges of the photoelectric conversion in S _3-1 is a period of time accumulated in inter-electrode capacitor 111 in the photoelectric conversion element ( (It is not shown in FIG. 23).

Thereafter, when the first transfer pulse is applied from the shift register 102 to the switch _T1-1 for t1 time, the photoelectric conversion element _S1-1 and the inverting input terminal of the operational amplifier 3 become conductive, and the signal charge _Q1-1 is _generated. The output of the operational amplifier 3 is transferred to the first integration capacitor Cf1, and the output signal is transmitted to the subsequent processing circuit (reading operation).

Furthermore, in order to read out the next photoelectric conversion element S _2-1 , it is necessary to reset the first integration capacitor Cf 1 in which the signal charge of the previous pixel is accumulated. Therefore, when the reset switch S _RES1 is turned on by applying the control signal CRES, among the differential input transistors of the operational amplifier 3, Q1 is turned on and Q2 is turned off, so that the phase compensation capacitor C3 is charged with the bias current 2I. In this embodiment, in addition to this, the control signal CRES of the first reset switch S _RES1 becomes Hi, and at the same time, the output of the control means 5 becomes Hi, the switch SW3 is turned ON, and the source electrode of Q13 and the phase compensation capacitor C3 are brought into conduction. To do. As a result, the phase compensation capacitor C3 is charged also by the time constant τ3 determined by the output impedance of the transistor Q13, the ON resistance of the switch SW3, and the capacitance value of the phase compensation capacitor C3. Since the output impedance of the transistor Q13 and the ON resistance of the switch SW3 can be increased, the time constant τ3 can be sufficiently reduced, and the slew rate of the operational amplifier 3 is improved.

  Thereafter, after a delay time t3 by the inverter delay circuit 6, the output of the control circuit 5 becomes Lo, so that the switch SW3 is turned OFF and the operational amplifier 3 enters the buffer amplifier operation. Here, if the transistor size and the current value of the transistor Q11 as a constant current source are adjusted so that the gate-source voltages of the transistors Q12 and Q13 constituting the level shift circuit are equal, the potential of the phase compensation capacitor C3 is adjusted. Is equal to the value when the operational amplifier 3 performs the buffer amplifier operation, so that the output voltage of the operational amplifier 3 is quickly stabilized at VREF1 after the forced reset period t3, and the reset time t2 can be shortened.

Thereafter, when the reset period ends enter the read operation, the signal charges of the next pixel of the photoelectric conversion device 101 is read by the shift register 102 and the switching element T _2-1 to the first integration capacitor Cf1.

  In this embodiment, since the phase compensation capacitor C3 of the operational amplifier 3 is forcibly charged by the switching circuit 4, a charging transient current I "is generated, but the period until the potential of C3 reaches the desired potential VREF1, that is, the maximum Since it is limited to t3 time, the increase in power consumption can be minimized.

(17th Embodiment)
FIG. 24 is a circuit diagram of a signal transfer apparatus having a suitable operational amplifier in which the signal charge reading speed is improved in the operational amplifier constituting the signal transfer apparatus of the present invention.

In FIG. 24, 7 is a comparator, 8 is a latch circuit, Q14 is a constant current source, a second conductivity type transistor, 10 is charged with a phase compensation capacitor C3 of the operational amplifier 3 composed of the transistor Q14 and the switch SW3. A switching circuit 9 is a control circuit composed of a comparator 7 and a latch circuit 8 for controlling the switching circuit 10. The output terminal of the operational amplifier 3 is connected to the inverting input terminal of the comparator 7, and the reference voltage VREF1 is connected to the normal input terminal. On the other hand, the data input terminal of the latch circuit 8 power control signal CRES where the clock input terminal for driving the reset switch S _RES1, the output terminal of the comparator 7 is respectively connected to the reset terminal, the forward data output terminal Drives the switch SW3.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  The feature of this embodiment is that, at the time of resetting, the switch SW3 is turned ON, and the constant current I ′ ″ is further added to the bias current 2I to charge the phase compensation capacitor C3.

  The signal transfer apparatus of the present invention can be suitably used for an imaging apparatus described below, and the operation of the signal transfer apparatus will be described later by taking an imaging apparatus using the example as an example.

(Eighteenth embodiment)
FIG. 25 is a circuit diagram of an imaging apparatus according to the eighteenth embodiment of the present invention. Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  25 differs from FIG. 22 in that a control circuit for controlling the switching circuit 10 is configured by the comparator 7 and the latch circuit 8. In FIG.

Moreover, to facilitate comparison with the other embodiments herein In Figure 25, the photoelectric conversion elements S _1-1 as the first operational amplifier E1 being used as the operational amplifier 3, for example in FIG. 14, S _{2- Although the first} stage operational amplifier is arranged for ₁ and S _3-1 , the arrangement location of the operational amplifier of the present invention is not limited to this. For example, the present invention can be applied to the second operational amplifiers F1 to F3 and / or the third operational amplifier H1 shown in FIG.

  Here, the operation of the imaging apparatus of the present invention will be described with reference to FIG.

First, signal charges obtained as a result of photoelectric conversion in the photoelectric conversion elements _S1-1 , _S2-1 , and _S3-3 as light receiving regions are accumulated in the interelectrode capacitance 111 in the photoelectric conversion element for a certain period ( (It is not shown in FIG. 25).

Thereafter, when the first transfer pulse is applied from the shift register 102 to the switch _T1-1 for t1 time, the photoelectric conversion element _S1-1 and the inverting input terminal of the operational amplifier 3 become conductive, and the signal charge _Q1-1 is _generated. The output of the operational amplifier 3 is transferred to the first integration capacitor Cf1, and the output signal is transmitted to the subsequent processing circuit (reading operation).

Furthermore, in order to read out the next photoelectric conversion element S _2-1 , it is necessary to reset the first integration capacitor Cf 1 in which the signal charge of the previous pixel is accumulated. Therefore, the reset switch S _RES1 is turned on by applying the control signal CRES. At that moment, the output of the operational amplifier E1 is lower than the signal output state of the previous pixel, that is, a state lower than VREF1, so that the output of the comparator 7 is Hi, so that the latch circuit 8 is enabled and output simultaneously with the control signal CRES becoming Hi. The data becomes Hi and the switch SW3 is turned ON, and the transistor Q14 and the phase compensation capacitor C3 are conducted. As a result, the phase compensation capacitor C3 is also charged by the constant current I ′ ″ supplied by Q14, so that the slew rate of the operational amplifier 3 is improved.

1 / SR (t / V) = C3 / (2I + I ″ ′) (24)
Thereafter, the output of the comparator 7 is inverted to Lo when the phase compensation capacitor C3 is charged and the output voltage of the operational amplifier 3 exceeds the desired voltage VREF1 when operating as the buffer amplifier during the reset period. Therefore, the latch circuit 8 is reset. The switch SW3 is turned OFF, and the operational amplifier 3 enters the buffer amplifier operation and becomes stable.

Then enters the reset period ends the read operation, the signal charges of the next pixel of the photoelectric conversion device 101 is read out to the integrating capacitor Cf1 by the shift register 102 and the switching element T _2-1.

  In this embodiment, the phase compensation capacitor C3 of the operational amplifier 3 is forcibly charged by the constant current I ′ ″ supplied by the switching circuit 10. This is because the output voltage of the operational amplifier 3 reaches the desired potential VREF1. The current consumption of the comparator 7 itself can be made smaller than the bias current I, so that the reset time t2 can be shortened while suppressing an increase in power consumption.

  Next, a radiation imaging system according to an embodiment of the present invention will be described. The imaging device according to each of the embodiments described above can be used as this imaging device.

  FIG. 27A is a schematic configuration diagram of an implementation example of an X-ray detection apparatus as a radiation imaging apparatus according to the present invention, and FIG. 27B is a schematic cross-sectional view taken along the line AA ′ of FIG. is there.

  Reference numeral 6011 denotes a sensor substrate (a-Si sensor substrate) on which a plurality of amorphous silicon photoelectric conversion elements and amorphous silicon TFTs (both not shown) are formed, SR1 denotes a shift register, and 6010 denotes a shift register SR1. PCB 1 is connected to the a-Si sensor substrate 6011 by the flexible circuit substrate 6010, and PCB 2 is also connected to the a-Si sensor substrate 6011 by the flexible circuit substrate 6010. An LSI chip (IC) having the above-described signal transfer device of the present invention is mounted on the flexible circuit board. Reference numeral 6012 denotes a base constituting a large photoelectric conversion device in which a plurality of a-Si sensor substrates 6011 are bonded, 6014 denotes a memory, 6013 denotes a lead plate for protecting the memory 6014 from X-rays, 6018 denotes a processing circuit, 6019 Denotes a connector, 6020 denotes a case made of carbon fiber for housing the whole, and 6030 denotes a scintillator for converting X-rays incident on the a-Si sensor substrate 6011 into visible light. For example, CsI is deposited as the scintillator 6030.

  FIG. 28 shows an X-ray diagnostic system as a radiation imaging system of the present invention, which shows an application example of the imaging apparatus described above.

  In FIG. 28, 6050 is an X-ray tube, 6060 is an X-ray generated from the X-ray tube, 6040 is an image sensor as an imaging device, 6061 is a patient or subject, 6062 is a chest of the subject 6061, and 6070 performs image processing. An image processor, 6080 and 6081 are displays, 6090 is a transmission means such as a telephone line, 6100 is a film processor, and 6110 is a film as a recording means.

  The operation flow of the X-ray diagnostic system shown in FIG. 28 is that the X-ray 6060 generated by the X-ray tube 6050 passes through the chest 6062 of the patient or subject 6061 and the photoelectric conversion device with the scintillator mounted on the upper part. Is incident on an image sensor 6040. This incident X-ray includes information inside the body of the patient 6061. The scintillator emits light in response to the incidence of X-rays, and this is photoelectrically converted to obtain electrical information. This information is digitally converted, image processed by an image processor 6070, and can be observed on a display 6080 in a control room.

  Further, this information can be transferred to a remote place by a transmission means such as a telephone line 6090, and can be displayed on a display 6081 such as a doctor room in another place or recorded on a recording means such as an optical disk, and diagnosed by a remote doctor. It is also possible. Further, it can be recorded on a recording means such as a film 6110 by the film processor 6100.

(Comparative example)
The following two comparative examples 1 and 2 are given as comparative examples of the sixteenth and eighteenth embodiments of the present invention.

  FIG. 32 is a circuit diagram of the imaging apparatus of Comparative Example 1. FIG. 33 is a timing chart for explaining the operation of FIG.

  FIG. 34 is a circuit diagram of the imaging apparatus of Comparative Example 2. FIG. 35 is a timing chart for explaining the operation of FIG.

  The comparative example 1 is different from the sixteenth and eighteenth embodiments in that the switching circuit 4 and the control circuit 5, the switching circuit 9 and the control circuit 10 arranged in the sixteenth and eighteenth embodiments are compared with each other. Reference numeral 1 is a configuration that is not arranged.

  In FIG. 32, V1 is the voltage value of the bias power source 107.

  Further, the parts denoted by the same reference numerals have been described above, and the description thereof will be omitted.

  Here, the operation of the imaging apparatus of FIG. 32 will be described with reference to FIG.

First, each of which is a certain period accumulated signal charge obtained as a result of the photoelectric conversion Q _1-1 to Q _3-1 in the inter-electrode capacitor 111 in the photoelectric conversion element in the photoelectric conversion elements S _1-1 to S _3-1 .

Then the first transfer pulse from the shift register 102 becomes conductive when applied t1 hours to switches T _1-1 and the first photoelectric conversion elements S _1-1 and the inverting input terminal of the operational amplifier 3 is, the signal charges Q _{1 -1} is transferred to the integration capacitor Cf1, and the output of the operational amplifier 3 is changed to transmit the signal to the subsequent processing circuit (reading operation).

  The output voltage Vo of the operational amplifier 3 at this time is given by the following equation.

_{Vo = VREF1-Q 1-1 / Cf1} (25)
At the same time, since the operational amplifier 3 is an inverting operational amplifier, the charge on the interelectrode capacitance is initialized to a value represented by the equation (26) when the capacitance value is _C1-1 .

_{Qo = C 1-1 × (VREF1-} V11) (26)
Then reset the signal charge Q _1-1 before pixel by shorting both ends of the integrating capacitor Cf1 reset switch S _RES1 is to time t2 ON by the control signal CRES provided for reading the signal charges of the next pixel (reset operation ).

At this time, since the operational amplifier 3 operates as a buffer amplifier, the output voltage Vo is Vo = VREF1 (27)
It becomes.

Second signal charge Q _2-1 of the photoelectric conversion elements S _2-1 are read out of the integration capacitor Cf1 newly when the second transfer pulse the shift register 102 again applied to the switch T _2-1. Thereafter, readout of signal charges of all pixels is completed by sequentially repeating reset and readout operations.

(25) the output voltage Vo apparent as operational amplifier 3 from equation depending on the signal charge quantity Q _1-1 to Q _3-1 which is photoelectrically converted in the photoelectric conversion elements S _1-1 to S _3-1 Change. Figure 33 shows a case where the signal charge amount is different, and each photoelectric conversion element S _1-1 to S _3-1 are uniform, thus the inter-electrode capacitance value C _1-1 -C _3-1 thereof each Are equal.

That is, when n is an arbitrary integer, in a multi-pixel imaging device,
C _1-1 = C _2-1 = ... = C _n-1 (28)
Is established.

Therefore, transfer time time Ttotal of the photoelectric conversion elements S _1-1 to S _3-1 signal charge accumulation time t0 and the signal charges of the number of all pixels in the required reading of all pixels of the imaging device shown in FIG. 32 It is expressed as the sum of t1 and the reset time t2 of the integration capacitor Cf1.

Ttotal = t0 + (t1 + t2) × n (29)
In equation (29), the accumulation time t0 is not dependent on the total number of pixels n because accumulation is possible for all the pixels at once. However, since the signal charge transfer and reset times t1 and t2 are necessary for each pixel, for example, a two-dimensional photoelectric conversion device As the number of pixels increases, the overall processing time increases. Therefore, in a readout circuit of a photoelectric conversion device that requires high-speed signal processing such as a moving image, it is required to reduce these times. .

  On the other hand, FIG. 34, which is Comparative Example 2, is a diagram showing together the internal circuit of the operational amplifier 3 generally used in the imaging apparatus shown in FIG. FIG. 35 is a timing chart thereof.

  Next, the operation of the operational amplifier 3 at the time of reset will be described with reference to FIG.

  In general, when the gate potentials of the first conductivity type transistors Q1 and Q2 constituting the differential input transistor pair change, the drain current thereof changes as follows.

IQ1 = I + ΔI (30)
IQ2 = I−ΔI (31)
The drains of Q1 and Q2 are respectively connected to the drains of the second conductivity type transistors Q3 and Q4 constituting the constant current source, and the difference current is input to the second conductivity type grounded gate transistors Q5 and Q6. The current passing through Q5 is input to a current mirror circuit composed of first conductivity type transistors Q7 to Q10, and this output current, that is, the difference current between the drain current of Q8 and the current passing through Q6, fills phase compensation capacitor C3. The output voltage is changed by discharging.

IQ8 = I ′ − (I + ΔI) (32)
IQ6 = I ′ − (I−ΔI) (33)
IQ6-IQ8 = 2ΔI (34)
The change in the output voltage is fed back to the gate electrode of Q2, which is the inverting input terminal, and is stabilized so that ΔI = 0.

When the reset switch S _RES1 is turned on, the instantaneous output terminal is in the signal output state of the previous pixel, so that the gate potential of the transistor Q2 becomes lower than the gate potential of Q1 as shown in the equation (25). Is turned off. The drain current change of Q1 and Q2 caused by this is
ΔI = I (35)
Therefore, the phase compensation capacitor C3 is charged with the bias current 2I of the differential pair Q1, Q2, and the time required to change the output voltage by 1V, that is, the reciprocal of the slew rate SR of the operational amplifier 3 is given by the equation (36). It is expressed as follows.

1 / SR (t / V) = C3 / 2I (36)
Therefore, the reset time t2 requires the minimum time obtained by multiplying the maximum signal voltage Vsigmax by the equation (36).

t2 >> Vsigmax / SR
= Vsigmax × (C3 / 2I) (37)
From equation (37), it can be seen that the phase compensation capacitance value C3 can be reduced or the bias current value 2I can be increased in order to shorten the reset time t2. However, since the operational amplifier 3 becomes a buffer amplifier at the time of resetting, the system becomes unstable if the phase compensation capacitance value is reduced. For this reason, a relatively large value of C3 is usually used so as to be stable even at the time of resetting, but a large bias current value is required to charge this and increase the slew rate SR. Since this bias current becomes a DC current consumed not only in the reset period but also in the readout period, it leads to an increase in power consumption of the entire system, which is not preferable.

  Therefore, there has been a demand for a signal charge readout circuit that suppresses an increase in power consumption, shortens the reset time t2 without decreasing the phase compensation capacitance value and makes the system unstable, and improves the signal charge readout speed. .

Transfer efficiency of signal charge Q _1-1 times t1 required to transfer to Q _3-1 to the integral capacitor Cf1 is normal transfer switch T _1-1 through T _3-1, i.e. switches T _1-1 through T ₃ It is determined from a time constant τ1 determined by the product of the ON resistance Ron of ₋₁ and the sum of the input capacitance C0 and the integration capacitance Cf1 of the operational amplifier 3. That is, they are sensitive aperture ratio decreases the pixels by increasing the size of the switch in order to reduce the ON resistance since it is provided for each pixel constituted by such transfer switch T _1-1 through T _3-1 is usually TFT Therefore, there is a limit in reducing the ON resistance. Therefore, to ensure sufficient transfer efficiency,
t1 >> 5τ1 (38)
τ1 = Ron × (C0 + Cf1) (39)
About time is required.

On the other hand, at the time of reset, the integration capacitor Cf1 is reset by the time constant τ2 between the ON resistance of the switch _SRES1 and Cf1 when the reset switch _SRES1 is turned ON, but the ON resistance of the switch _SRES1 can be made sufficiently small. Therefore, in this case, the time constant τ 2 is not a dominant factor for determining t 2, and the reset time t 2 is normally determined by the response speed of the operational amplifier 3.

  In the sixteenth embodiment and the eighteenth embodiment, the switching circuit that charges and discharges the phase compensation capacitor C3 of the operational amplifier 3 is in the reset period, that is, in the period in which the capacitor element that reads the signal charge is reset by turning on the first switching element. In this case, the phase compensation capacitor is forcibly charged / discharged by turning it on for a period determined by the control circuit so that this potential reaches a desired potential. is there.

1 is a circuit diagram of a signal transfer apparatus according to a first embodiment of the present invention. It is a circuit diagram of the imaging device by a 2nd embodiment of the present invention. It is a timing chart explaining operation | movement of the imaging device by 2nd Embodiment of this invention. It is a circuit diagram of the signal transfer apparatus by 3rd Embodiment of this invention. It is a circuit diagram of the imaging device by 4th Embodiment of this invention. FIG. 9 is a circuit diagram of a signal transfer device according to a fifth embodiment of the present invention. It is a circuit diagram of the imaging device by 6th Embodiment of this invention. It is a timing chart explaining operation | movement of the imaging device by 6th Embodiment of this invention. It is a figure explaining the output voltage of the inverting operational amplifier which concerns on FIG. 5 of this invention. It is a figure explaining the output voltage of the inverting operational amplifier which concerns on FIG. 7 of this invention. It is a circuit diagram of the signal transfer apparatus by 7th Embodiment of this invention. It is a circuit diagram of the imaging device by 8th Embodiment of this invention. It is a circuit diagram of the signal transfer apparatus by 9th Embodiment of this invention. It is a circuit diagram of the imaging device by 10th Embodiment of this invention. It is a timing chart explaining operation | movement of the imaging device by 10th Embodiment of this invention. It is a circuit diagram of the signal transfer apparatus by 11th Embodiment of this invention. It is a circuit diagram of the imaging device by 12th Embodiment of this invention. It is a circuit diagram of the signal transfer apparatus by 13th Embodiment of this invention. It is a circuit diagram of the imaging device by 14th Embodiment of this invention. It is a timing chart explaining operation | movement of the imaging device by 14th Embodiment of this invention. It is a circuit diagram of the signal transfer apparatus by 15th Embodiment of this invention. It is a circuit diagram of the imaging device by 16th Embodiment of this invention. It is a timing chart explaining operation | movement of the imaging device by 16th Embodiment of this invention. It is a circuit diagram of the signal transfer apparatus by 17th Embodiment of this invention. It is a circuit diagram of the imaging device by 18th Embodiment of this invention. It is a timing chart explaining operation | movement of the imaging device by 18th Embodiment of this invention. (A) is a typical block diagram of the example of mounting of the radiation imaging device by this invention, (b) is typical sectional drawing in the A-A 'line of Fig.27 (a). The application example to the radiation imaging system of the radiation imaging device by this invention is shown. It is a circuit diagram of the photoelectric conversion apparatus which is a 1st prior art example. It is a timing chart explaining operation | movement of the photoelectric conversion apparatus which is a 1st prior art example. It is a circuit diagram of the photoelectric conversion apparatus which is a 2nd prior art example. 6 is a circuit diagram of an imaging apparatus that is Comparative Example 1. FIG. 10 is a timing chart for explaining the operation of the imaging apparatus that is Comparative Example 1; FIG. 10 is a circuit diagram of an imaging apparatus that is Comparative Example 2. 10 is a timing chart for explaining the operation of an imaging apparatus that is Comparative Example 2.

Explanation of symbols

101 Photoelectric conversion circuit unit 102 Driving circuit unit 103 Reading circuit unit 104 Reading switch driving circuit unit 105 Output buffer amplifier 106 A / D conversion circuit unit 107 Bias power supply 110 Light receiving region 111 Interelectrode capacitance 112 Terminal 113 Terminal B1 B3 buffer amplifier C1~C3 load capacitance Cf1 first integrating capacitor C _L1 -C _L3 sampling capacitor CRES control signal E1~E3 first operational amplifier G1~G3 gate driving line SMPL voltage pulse S _1-1 to S _3-3 photoelectric conversion element Sn1~Sn3 sampling switch Sr1~Sr3 reading switches S _RES1 to S _RES3 first reset switch T _1-1 through T _3-3 switching element VREF1 first reference voltage M1~M3 matrix signal wires

Claims (18)

A plurality of terminals connected to a plurality of signal sources;
In a signal transfer device having a readout circuit unit that converts a signal input from the plurality of terminals into a serial signal and outputs the serial signal,
The readout circuit unit includes a first operational amplifier connected to the terminal, a sampling switch that samples an output signal output through the first operational amplifier, and a sampling capacitor that stores the sampled output signal. A readout switch that sequentially reads out the stored output signal as a serial signal from the sampling capacitor, and a second operational amplifier that receives the serial signal,
The first operational amplifier includes an inverting input terminal connected to the corresponding terminal, a normal input terminal to which a reference voltage is supplied, and an output terminal, and the inverting input terminal of the first operational amplifier; An integration capacitor and a reset switch are connected in parallel between the output terminal,
The second operational amplifier includes an inverting input terminal connected to the sampling capacitor via the read switch, a normal input terminal to which a reference voltage is supplied, and an output terminal, and the second operational amplifier And a reset switch connected in parallel between the inverting input terminal and the output terminal. 2. The signal transfer device according to claim 1, wherein the first operational amplifier includes a capacitor and a reset switch in addition to the integral capacitor connected between the inverting input terminal and the output terminal of the first operational amplifier. A signal transfer device connected in parallel. 3. The signal transfer device according to claim 1, wherein the reading circuit unit includes a normal input terminal to which a reference voltage is supplied, an inverting input terminal that receives an output of the first operational amplifier, and a sampling switch. A signal transfer device further comprising a third operational amplifier having an output terminal connected thereto. 4. The signal transfer device according to claim 3, wherein an integration capacitor and a reset switch are connected between the inverting input terminal and the output terminal of the third operational amplifier. 5. The signal transfer device according to claim 3, wherein a capacitive element is disposed between the output terminal of the first operational amplifier and the inverting input terminal of the third operational amplifier. Transfer device. 6. The signal transfer device according to claim 1, wherein a resistance element is disposed between the sampling switch and the sampling capacitor. 7. The signal transfer device according to claim 1, wherein the sampling capacitor is connected to one of a plurality of common output lines by the read switch, and the output signal stored in the sampling capacitor. Is input to the inverting input terminal of the second operational amplifier connected to one of the plurality of common output lines. 8. The signal transfer device according to claim 1, wherein a switching circuit that charges and discharges a phase compensation capacitor of the first operational amplifier, and an operation of the reset switch of the first operational amplifier, And a control circuit for controlling the switching circuit. A circuit unit having a conversion element that converts at least one of incident light or radiation into an electrical signal;
In an imaging apparatus comprising: a signal transfer circuit unit that transfers a signal from the circuit unit;
The signal transfer circuit unit includes a first operational amplifier connected to the circuit unit, a sampling switch for sampling an output signal output through the first operational amplifier, and a sampling capacitor for storing the sampled output signal And a read switch that sequentially reads out the stored output signal as a serial signal from the sampling capacitor, and a second operational amplifier that receives the serial signal,
The first operational amplifier includes an inverting input terminal connected to the circuit unit, a non-inverting input terminal to which a reference voltage is supplied, and an output terminal. The inverting input terminal of the first operational amplifier and the An integration capacitor and a reset switch are connected in parallel between the output terminal and
The second operational amplifier includes an inverting input terminal connected to the sampling capacitor via the read switch, a normal input terminal to which a reference voltage is supplied, and an output terminal, and the second operational amplifier An imaging device, wherein an integration capacitor and a reset switch are connected in parallel between the inverting input terminal and the output terminal. 10. The imaging device according to claim 9, wherein the first operational amplifier further includes a capacitor and a reset switch in parallel with the integration capacitor connected between the inverting input terminal and the output terminal of the first operational amplifier. An image pickup apparatus connected to 11. The imaging device according to claim 9, wherein the signal transfer circuit unit is connected to a normal input terminal to which a reference voltage is supplied, an inverting input terminal that receives the output of the first operational amplifier, and the sampling switch. And a third operational amplifier having an output terminal. 12. The imaging apparatus according to claim 11, wherein an integration capacitor and a reset switch are connected between the inverting input terminal and the output terminal of the third operational amplifier. 13. The imaging apparatus according to claim 11 or 12, wherein a capacitive element is arranged between the output terminal of the first operational amplifier and the inverting input terminal of the third operational amplifier. . The imaging apparatus according to claim 9, wherein a resistance element is disposed between the sampling switch and the sampling capacitor. 15. The imaging device according to claim 9, wherein the sampling capacitor is connected to one of a plurality of common output lines by the readout switch, and the output signal accumulated in the sampling capacitor is An imaging apparatus, wherein the imaging device is inputted to the inverting input terminal of the second operational amplifier connected to any one of the plurality of common output lines. The imaging apparatus according to claim 9, wherein the circuit unit includes a thin film photoelectric conversion element and a thin film switching element. The imaging device according to claim 9, wherein the circuit unit includes a photoelectric conversion element and a light emitter that emits light upon receiving radiation. An imaging device according to claim 17,
Signal processing means for processing a signal from the imaging device;
Recording means for recording a signal from the signal processing means;
Display means for displaying a signal from the signal processing means;
Transmission processing means for transmitting a signal from the signal processing means;
A radiation imaging system comprising: a radiation source for generating the radiation.