WO2017110163A1

WO2017110163A1 - Solid-state imaging element, driving method for solid-state imaging element, and electronic device

Info

Publication number: WO2017110163A1
Application number: PCT/JP2016/076977
Authority: WO
Inventors: 恭範佃
Original assignee: ソニー株式会社
Priority date: 2015-12-25
Filing date: 2016-09-13
Publication date: 2017-06-29
Also published as: JP2017118373A

Abstract

The solid-state imaging element according to the present disclosure comprises: a unit pixel including a charge detection unit that converts, into voltage, charge obtained as a result of photoelectric conversion; a vertical signal line common to one or more of the unit pixels; a pixel control line that controls the unit pixel; a first electric current supply unit that supplies electric current to the vertical signal line when a signal is read out from the unit pixel to the vertical signal line; and a second electric current supply unit that supplies, to the vertical signal line, electric current corresponding to an electric potential change in the charge detection unit accompanied by a transition of the electric potential of the pixel control line. The second electric current supply unit stops supplying the electric current to the vertical signal line in conjunction with the timing at which the electric potential change in the charge detection unit occurs.

Description

Solid-state imaging device, driving method of solid-state imaging device, and electronic device

The present disclosure relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device.

Acceleration of pixel signal reading speed and high definition are desired for solid-state imaging devices. In addition, increasing the number of pixels is desired to improve the resolution. As the number of pixels increases, the number of pixels connected to the vertical signal line (column signal line) increases, and the parasitic capacitance of the vertical signal line increases. This increase in the parasitic capacitance of the vertical signal line hinders shortening of the settling (static / settling) time of the potential of the vertical signal line. Shortening the settling time is important for increasing the readout speed of pixel signals. That is, in a solid-state image sensor, there is a trade-off between increasing the pixel signal readout speed and increasing the number of pixels.

Conventionally, in order to shorten the settling time of the potential of the vertical signal line, an additional current is supplied to the vertical signal line according to the potential fluctuation amount of the vertical signal line (for example, refer to Patent Document 1). By causing an additional current to flow through the vertical signal line in accordance with the potential fluctuation amount of the vertical signal line, the slew rate of the vertical signal line is improved, so that the settling time can be shortened.

In addition, in order to shorten the settling time of the potential of the vertical signal line, an additional current is applied to the vertical signal line at the timing of reading the pixel signal after the signal for changing the potential of the vertical signal line (reset control signal or transfer control signal). (For example, refer nonpatent literature 1). Similar to the prior art described in Patent Document 1, by supplying an additional current to the vertical signal line, the slew rate of the vertical signal line is improved, so that the settling time can be shortened.

Japanese Patent Laying-Open No. 2015-139081

The prior art described in Patent Document 1 is useful when the potential of the vertical signal line is large. However, the settling after the potential of the floating diffusion FD (charge voltage conversion unit / charge detection unit) fluctuates when the supply of the additional current is stopped or due to the feedthrough generated in response to the transition of the potential of the pixel control line. When the entire settling time is controlled, the effect of shortening the settling time is small.

In the prior art described in Non-Patent Document 1, even if the potential of the vertical signal line has once settled, the gate-source voltage V of the amplification transistor constituting the source follower is stopped along with the supply of the additional current. _gs changes. When the gate-source voltage V _gs changes, it is necessary to wait again for the settling time determined by the RC delay equation of the wiring resistance R and parasitic capacitance C of the vertical signal line. Further, the effect of shortening the settling time is limited to the case where the potential fluctuation of the vertical signal line due to the change in the potential of the floating diffusion FD is sufficiently larger than the potential fluctuation of the vertical signal line due to the supply stop of the additional current. . Conversely, when the potential change of the floating diffusion FD is small, the settling time of the potential of the vertical signal line is extended.

Accordingly, the present disclosure provides a solid-state imaging device, a solid-state imaging device driving method, and the solid-state imaging device capable of more reliably reducing the settling time of the potential of the vertical signal line and increasing the pixel signal reading speed. It is an object to provide an electronic device having

In order to achieve the above object, a solid-state imaging device of the present disclosure is provided.
A unit pixel including a charge detection unit that converts a charge obtained by photoelectric conversion into a voltage;
A vertical signal line shared by one or more unit pixels,
A pixel control line for controlling the unit pixel,
A first current supply unit for supplying a current to the vertical signal line when reading a signal from the unit pixel to the vertical signal line; and
A second current supply unit configured to supply a current corresponding to a potential variation of the charge detection unit accompanying the transition of the potential of the pixel control line to the vertical signal line;
The second current supply unit stops the supply of current to the vertical signal line in synchronization with the occurrence timing of the potential fluctuation of the charge detection unit. In addition, an electronic apparatus according to the present disclosure for achieving the above object includes the solid-state imaging device having the above configuration.

In order to achieve the above object, a solid-state imaging device of the present disclosure is provided.
A unit pixel including a charge detection unit that converts a charge obtained by photoelectric conversion into a voltage;
A vertical signal line shared by one or more unit pixels, and
It has a pixel control line that controls the unit pixel,
Solid that supplies current to the vertical signal line when reading a signal from the unit pixel to the vertical signal line, and supplies current to the vertical signal line corresponding to the potential fluctuation of the charge detection unit due to the potential transition of the pixel control line In driving the image sensor,
The supply of current to the vertical signal line is stopped in synchronization with the occurrence timing of the potential fluctuation of the charge detection unit.

When the potential of the pixel control line transitions, the potential of the charge detection unit fluctuates (changes) accordingly. When the potential of the charge detection unit varies, the potential of the vertical signal line varies. Therefore, when a current corresponding to the potential fluctuation of the charge detection unit accompanying the transition of the potential of the pixel control line is supplied to the vertical signal line and the supply is stopped in conjunction with the occurrence timing of the potential fluctuation of the charge detection unit, Variation in the potential of the signal line can be suppressed.

According to the present disclosure, the supply of the current corresponding to the potential variation of the charge detection unit to the vertical signal line is stopped in conjunction with the occurrence timing of the potential variation of the charge detection unit, so that the potential of the vertical signal line is reduced. Variation can be suppressed. Thereby, since the settling time of the potential of the vertical signal line can be more reliably shortened, the pixel signal reading speed can be increased.

It should be noted that the effect described here is not necessarily limited, and may be any effect described in the present specification. Moreover, the effect described in this specification is an illustration to the last, Comprising: It is not limited to this, There may be an additional effect.

FIG. 1 is a system configuration diagram illustrating an outline of a configuration of a solid-state imaging device of the present disclosure. FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a unit pixel. FIG. 3 is a circuit diagram illustrating a circuit configuration of a main part of the solid-state imaging device according to the first embodiment. 4A is a timing waveform diagram showing a timing relationship between the reset control signal RST, the transfer control signal TRG, the control signal Φ _BST , and the control signal Φ _SH , and FIG. 4B is a diagram associated with the transition of the transfer control signal TRG. FIG. 6 is a timing waveform diagram showing signal waveforms of respective parts of the circuit 3. FIG. 5 is a circuit diagram showing a configuration example of the current generation circuit according to Example 1 of the second embodiment. FIG. 6 is a circuit diagram illustrating a configuration example of a current generation circuit according to Example 2 of the second embodiment. FIG. 7 is a circuit diagram illustrating a configuration example of a current generation circuit according to Example 3 of the second embodiment. FIG. 8 is a circuit diagram of the circuit configuration of the main part of the solid-state imaging device according to the third embodiment. FIG. 9A is a timing waveform diagram for explaining a procedure for determining an optimum value of the additional current, and FIG. 9B is a waveform diagram showing an image of a change in voltage of the vertical signal line due to a change in the additional current. FIG. 10 is a circuit diagram illustrating a circuit configuration of a main part of the solid-state imaging device according to the fourth embodiment. FIG. 11 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure.

Hereinafter, modes for carrying out the technology of the present disclosure (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to the embodiments, and various numerical values in the embodiments are examples. In the following description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. The description will be given in the following order.
1. 1. Description of the solid-state imaging device of the present disclosure, a driving method thereof, and an electronic device in general 2. Solid-state imaging device of the present disclosure First embodiment (example in which additional current is fixed)
4). Second embodiment (example in which the additional current is variable)
4-1. Example 1 (example in which an additional current adjustment mechanism is mounted for each pixel column)
4-2. Example 2 (example in which an adjustment mechanism for additional current is mounted in common for all pixel columns)
4-3. Example 3 (example in which an adjustment mechanism for an additional current is mounted in common for all pixel columns)
5). Third Embodiment (Example in which an optimum value of additional current is determined using an AD converter)
6). Fourth Embodiment (Example in which an optimum value of additional current is determined using voltage measuring means)
7). Modification 8 Electronic device of the present disclosure (example of imaging device)

<Description of Solid-State Imaging Device of the Present Disclosure, its Driving Method, and Electronic Device>
In the solid-state imaging device, the driving method thereof, and the electronic device of the present disclosure, the unit pixel has a transfer transistor that transfers the charge obtained by photoelectric conversion to the charge detection unit, and the pixel control line A transfer control signal for driving the transfer transistor can be transmitted. At this time, the second current supply unit can be configured to stop the supply of current to the vertical signal line in conjunction with the transition timing of the transfer control signal.

In the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic device, the unit pixel includes a reset transistor that resets the charge detection unit, and the pixel control line includes the reset transistor. The reset control signal for driving the signal can be transmitted. At this time, the second current supply unit can be configured to stop the supply of current to the vertical signal line in conjunction with the transition timing of the reset control signal.

Furthermore, the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic apparatus include an amplification transistor that reads the voltage converted by the charge detection unit to the vertical signal line for each unit pixel. It can be configured. At this time, the amplification transistor and the first current supply unit constitute a source follower that converts the voltage converted by the charge detection unit into the potential of the vertical signal line. In addition, the second current supply unit can be configured to generate an overdrive voltage of the source follower equivalent to the potential fluctuation of the charge detection unit by supplying a current to the vertical signal line. Further, the second current supply unit can be configured such that the current supplied to the vertical signal line is variable.

Further, in the solid-state imaging device, the driving method thereof, and the electronic apparatus of the present disclosure including the above-described preferable configuration, the potential fluctuation amount of the charge detection unit accompanying the transition of the potential of the pixel control line, and the second current An acquisition unit that acquires the amount of fluctuation in the overdrive voltage of the source follower accompanying the supply of current to the vertical signal line from the supply unit can be provided. At this time, the second current supply unit can be configured to set the current supplied to the vertical signal line based on the acquisition result of the acquisition unit. Moreover, it is preferable that an acquisition means acquires as the variation | change_quantity of a specific pixel row | line | column or the average fluctuation | variation amount of several pixel row | line | column.

Furthermore, in the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic device, the second current supply unit includes the potential fluctuation amount of the charge detection unit and the fluctuation amount of the overdrive voltage. The current that is closest to the pixel control line can be set as a current corresponding to the potential variation of the charge detection unit accompanying the transition of the potential of the pixel control line. Further, the second current supply unit can be configured to sample a current amount adjustment signal for adjusting a current supplied to the vertical signal line.

Furthermore, in the solid-state imaging device of the present disclosure including the preferable configuration described above, a driving method thereof, and an electronic device, a configuration including a readout circuit unit connected to a vertical signal line can be employed. At this time, the reading circuit unit can be configured to function as an acquisition unit. Alternatively, the acquisition means may be configured by voltage measurement means provided outside or inside the solid-state imaging device. In addition, the readout circuit portion can be configured to sample and hold the voltage of the vertical signal line. The readout circuit unit can be configured using an analog-digital converter that converts an analog pixel signal read from a unit pixel into digital pixel data.

Furthermore, in the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic device, the fixed potential wiring of the first current supply unit and the fixed potential wiring of the second current supply unit; Are preferably separated.

<Solid-state imaging device of the present disclosure>
First, an outline of the configuration of the solid-state imaging device of the present disclosure will be described. Here, a CMOS image sensor which is a kind of XY address type solid-state imaging device will be described as an example of the solid-state imaging device of the present disclosure. The solid-state imaging device may have a so-called flat structure or a so-called laminated structure. Here, the “flat structure” is a peripheral circuit of a pixel array unit in which unit pixels are arranged in a two-dimensional matrix, that is, a drive unit that drives each unit pixel of the pixel array unit, or a unit pixel. In this structure, a signal processing unit that performs predetermined signal processing on a signal to be transmitted is disposed on the same semiconductor substrate (semiconductor chip) as the pixel array unit. The “stacked structure” is a structure in which a signal processing unit or the like is mounted on a semiconductor substrate different from the pixel array unit and these semiconductor substrates are stacked.

[System configuration]
FIG. 1 is a system configuration diagram illustrating an outline of a configuration of a solid-state imaging device of the present disclosure. As illustrated in FIG. 1, the solid-state imaging device 10 of the present disclosure includes a pixel array unit 11, a peripheral driving system, and a signal processing system. In this example, as peripheral driving systems and signal processing systems, for example, a row scanning unit (vertical scanning unit) 12, a reading circuit unit 13, a column scanning unit (horizontal scanning unit) 15, a horizontal output line 16, and a video signal processing unit. 17 and a timing control unit 18 are provided. These drive system and signal processing system are integrated on the same semiconductor substrate (semiconductor chip) 30 as the pixel array unit 11.

In this system configuration, the timing control unit 18 includes, for example, a row scanning unit 12, a readout circuit unit 13, and a column scanning unit based on an externally input vertical synchronization signal VD, horizontal synchronization signal HD, master clock MCK, and the like. A clock signal, a control signal, and the like serving as a reference for operation such as 15 are generated. Clock signals, control signals, and the like generated by the timing control unit 18 are given as drive signals to the row scanning unit 12, the readout circuit unit 13, the column scanning unit 15, and the like.

The pixel array unit 11 generates photoelectric charges according to the amount of received light, and unit pixels (hereinafter sometimes simply referred to as “pixels”) 20 each having a photoelectric conversion element to accumulate are arranged in a row direction and a column direction. That is, it is configured to be arranged in a matrix (two-dimensional matrix). Here, the row direction refers to the pixel arrangement direction in the pixel row, and the column direction refers to the pixel arrangement direction in the pixel column.

The unit pixel 20 may be a back-illuminated pixel or a front-illuminated pixel. Here, the “back-illuminated pixel” refers to a pixel structure that takes incident light from the opposite side, that is, the back side when the side on which the wiring layer is disposed is the front side. Further, the “surface irradiation type pixel” refers to a pixel structure that takes in incident light from the surface side on which the wiring layer is disposed.

In the pixel array unit 11, the pixel control line 31 in which the pixel control lines 31 ( _{31_1} to _{31_m} ) are wired in the row direction for each pixel row with respect to the pixel array of m rows and n columns is a unit pixel. A control signal for performing control when a signal is read from 20 is transmitted. In FIG. 1, the pixel control line 31 is illustrated as one wiring, but the number is not limited to one. One end of each of the pixel control lines 31 _{_ 1} to 31 _{_m} is connected to each output end corresponding to each row of the row scanning unit 12. Further, vertical signal lines 32 ( _{32_1} to _{32_n} ) are wired along the column direction for each pixel column with respect to the pixel array of m rows and n columns. The vertical signal line 32 is shared by one or more unit pixels 20 for each pixel column.

The row scanning unit 12 includes a shift register, an address decoder, and the like, and drives each pixel 20 of the pixel array unit 11 at the same time or in units of rows. Although the specific configuration of the row scanning unit 12 is not shown, the row scanning unit 12 generally has two scanning systems, a reading scanning system and a sweeping scanning system. In order to read out a signal from the unit pixel 20, the readout scanning system selectively scans the unit pixels 20 of the pixel array unit 11 in units of rows. A signal read from the unit pixel 20 is an analog signal. The sweep-out scanning system performs sweep-out scanning with respect to the readout row on which readout scanning is performed by the readout scanning system, preceding the readout scanning by a time corresponding to the shutter speed.

By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion element of the unit pixel 20 in the readout row, thereby resetting the photoelectric conversion element. A so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and a new exposure is started (photocharge accumulation is started).

The signal read out by the readout operation by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation. A period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photo charge exposure period in the unit pixel 20.

The readout circuit unit 13 is configured to sample and hold the voltage of the vertical signal lines 32 ( _{32_1} to _{32_n} ). The readout circuit unit 13 can be configured using, for example, an analog-digital converter that converts an analog pixel signal into digital pixel data. An analog-digital converter having a configuration for performing correlated double sampling (CDS) processing for removing noise during reset operation of the unit pixel 20 during analog-digital conversion is used. Can do.

In FIG. 1, the column scanning unit 15 includes a shift register, an address decoder, and the like, and controls the column address and column scanning of the readout circuit unit 13. Under the control of the column scanning unit 15, the digital pixel data subjected to analog-digital conversion in the readout circuit unit 13 is sequentially read out to the horizontal output line 16 and supplied to the video signal processing unit 17.

The video signal processing unit 17 performs predetermined signal processing on the digital data (video signal) read from the reading circuit unit 13 and then outputs the data as imaging data from the output terminal 33 to the outside of the semiconductor substrate 30.

[Circuit configuration of unit pixel]
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the unit pixel 20. As shown in FIG. 2, the unit pixel 20 according to this example includes, for example, a photodiode PD as a photoelectric conversion element. In addition to the photodiode PD, the unit pixel 20 includes, for example, a transfer transistor 21, a reset transistor 22, an amplification transistor 23, and a selection transistor 24.

Here, for example, N-type MOSFETs are used as the four transistors of the transfer transistor 21, the reset transistor 22, the amplification transistor 23, and the selection transistor 24. However, the combination of the conductivity types of the four transistors 21 to 24 exemplified here is merely an example, and the combination is not limited to these combinations.

A plurality of

control lines

311, 312, and 313 are wired in common to the pixels in the same pixel row as the above-described pixel control lines 31 (31 _{_ 1} to 31 _{_m} ) for the unit pixel 20. The plurality of

control lines

311, 312, 313 are connected to the output end corresponding to each pixel row of the row scanning unit 12 in units of pixel rows. The row scanning unit 12 appropriately outputs a transfer control signal TRG, a reset control signal RST, and a selection control signal SEL to the plurality of

control lines

311, 312, and 313.

The photodiode PD has an anode electrode connected to a low-potential-side power source (for example, ground), and photoelectrically converts received light into photocharge (here, photoelectrons) having a charge amount corresponding to the amount of light. Accumulate charge. The cathode electrode of the photodiode PD is electrically connected to the gate electrode of the amplification transistor 23 through the transfer transistor 21. A region electrically connected to the gate electrode of the amplification transistor 23 is a floating diffusion (floating diffusion region / impurity diffusion region) FD. The floating diffusion FD is a charge detection unit (charge voltage conversion unit) that converts a charge into a voltage.

The transfer transistor 21 is connected between the cathode electrode of the photodiode PD and the floating diffusion FD. A transfer control signal TRG that activates a high level (for example, V _DD level) is applied to the gate electrode of the transfer transistor 21 from the row scanning unit 12 through the control line 311. When the transfer transistor 21 is turned on in response to the transfer control signal TRG, it is photoelectrically converted by the photodiode PD and transfers the accumulated photocharge to the floating diffusion FD.

The reset transistor 22 has a drain electrode connected to a node (power supply line) of the voltage V _DD and a source electrode connected to the floating diffusion FD. A reset control signal RST that activates a high level is applied to the gate electrode of the reset transistor 22 from the row scanning unit 12 through the control line 312. The reset transistor 22 becomes conductive in response to the reset control signal RST, and resets the floating diffusion FD by discarding the charge of the floating diffusion FD to the node of the voltage V _DD .

The amplification transistor 23 has a gate electrode connected to the floating diffusion FD and a drain electrode connected to the node of the voltage V _DD . The amplification transistor 23 serves as an input part of a source follower that reads a signal obtained by photoelectric conversion in the photodiode PD. That is, the source electrode of the amplification transistor 23 is connected to the vertical signal line 32 via the selection transistor 24. The amplification transistor 23 and the current source 34 connected to one end of the vertical signal line 32 constitute a source follower that converts the voltage of the floating diffusion FD into the potential of the vertical signal line 32.

For example, the selection transistor 24 has a drain electrode connected to the source electrode of the amplification transistor 23 and a source electrode connected to the vertical signal line 32. A selection control signal SEL that activates a high level is applied to the gate electrode of the selection transistor 24 from the row scanning unit 12 through the control line 313. The selection transistor 24 becomes conductive in response to the selection control signal SEL, and transmits the signal output from the amplification transistor 23 to the vertical signal line 32 with the unit pixel 20 selected.

The selection transistor 24 may have a circuit configuration connected between the node of the voltage V _DD and the drain electrode of the amplification transistor 23. In this example, as a pixel circuit of the unit pixel 20, a 4Tr configuration including the transfer transistor 21, the reset transistor 22, the amplification transistor 23, and the selection transistor 24, that is, four transistors (Tr) is given as an example. However, it is not limited to this. For example, the selection transistor 24 may be omitted, and a 3Tr configuration in which the amplification transistor 23 has the function of the selection transistor 24 may be used, or a configuration in which the number of transistors is increased as necessary.

[Vertical signal line potential settling time]
The operation at the time of reading the reset potential (reset level) V _rst and the signal potential (signal level) V _sig of the floating diffusion FD in the unit pixel 20 having the above circuit configuration will be described more specifically.

( _Read reset potential _Vrst )
Reading of the reset potential V _rst of the floating diffusion FD is performed as follows.
1) When the reset control signal RST transitions from a low level to a high level, the reset transistor 22 becomes conductive, and a reset voltage of, for example, the voltage V _DD is applied to the floating diffusion FD.
2) After this reset operation, the potential of the floating diffusion FD changes due to the feedthrough of the reset transistor 22 when the reset control signal RST transitions from a high level to a low level.
3) As the potential of the floating diffusion FD changes, the potential of the vertical signal line 32 also changes.
4) At this time, settling until the potential of the vertical signal line (VSL) 32 is stabilized (stabilized / settled) due to RC delay caused by the wiring resistance R and the parasitic capacitance C of the vertical signal line 32 (hereinafter referred to as “VSL settling”). Time may be required).

(Reading signal potential V _sig )
Reading of the signal potential V _sig of the floating diffusion FD is performed as follows.
1) The transfer control signal TRG transits from a low level to a high level, the transfer transistor 21 becomes conductive, and the photocharge obtained by the photodiode PD is transferred to the floating diffusion FD.
2) In the floating diffusion FD, the photocharge transferred from the photodiode PD is converted into a voltage.
3) The potential of the floating diffusion FD changes due to the feedthrough of the transfer transistor 21 when the transfer control signal TRG transitions from the high level to the low level when the transfer of the photocharge is completed.
4) When reading the signal potential V _sig , RC delay settling is required as in the case of reading the reset potential V _rst .

In the circuit operation of the unit pixel 20 described above, the potential fluctuation of the vertical signal line 32 due to the feedthrough of the reset transistor 22 and the transfer transistor 21 is ΔV _FT (= difference from the final stable voltage), and the wiring of the vertical signal line 32 Let τ be the time constant of RC delay due to the resistor R and the parasitic capacitance C. Then, the potential V (t) of the vertical signal line 32 is given by the following equation (1).

Here, if the time for settling to 10-bit accuracy (0.1%) is T,

And

To set up to 10-bit precision requires 6.9τ.

On the other hand, the VSL settling time can be shortened by reducing the potential variation ΔV _FT of the vertical signal line 32 due to the feedthrough of the reset transistor 22 and the transfer transistor 21. Specifically, if the initial value of [Delta] V _FT, the time T _settle for settling the 0.1DerutaV _FT becomes 2.3τ the following equation (4).

Since the settling time is shortened from 6.9τ → (6.9-2.3) τ due to the difference in the initial value, the improvement effect of VSL settling time is 2.3 / 6.9, that is, 33.3%. Become.

In the solid-state imaging device 10 of the present disclosure, in the current situation where the VSL settling time is determined by the transition of the potential of the pixel control line 31, the potential variation ΔV _FT of the vertical signal line 32 due to the feedthrough of the reset transistor 22 and the transfer transistor 21 is _reduced . It is characterized by reducing the VSL settling time. The technique of the present disclosure for reducing the potential fluctuation ΔV _FT of the vertical signal line 32 due to the feedthrough of the reset transistor 22 and the transfer transistor 21 will be specifically described below.

<First Embodiment>
The circuit configuration of the main part of the solid-state imaging device according to the first embodiment is shown in the circuit diagram of FIG. The circuit of the main part according to the first embodiment is a circuit common to a part of the circuit (hereinafter referred to as “in-column circuit”) 13A in the readout circuit unit (column circuit unit) 13 and the readout circuit unit 13. (Hereinafter referred to as “column common circuit”) 13B. The in-column circuit 13A may be provided in common for each pixel column of the pixel array unit 11, or may be provided for each unit of a plurality of pixel columns, or the pixel column. It may be provided for each.

3, the current source 34 also illustrated in FIG. 2 is a first current supply unit (hereinafter referred to as “current supply unit”) that supplies a current I ₀ to the vertical signal line 32 when a pixel signal is read from the unit pixel 20 to the vertical signal line 32. , Described as “first current supply unit 34”). The first current supply unit 34 includes a MOS transistor 51, a MOS transistor 52, and a current source 53. The MOS transistor 51 is connected in series to the end of the vertical signal line 32. The MOS transistor 52 has a diode connection configuration in which a gate electrode and a drain electrode are connected in common.

The MOS transistor 51 and the MOS transistor 52 have a gate electrode connected in common to form a current mirror circuit. The current source 53 is connected in series to the MOS transistor 52 and supplies a predetermined reference current to the MOS transistor 52. As a result, a current I ₀ corresponding to the reference current supplied from the current source 53 to the MOS transistor 52 flows through the vertical signal line 32.

In the first current supply unit 34 configured as described above, the MOS transistor 51 belongs to the intra-column circuit 13A, and the MOS transistor 52 and the current source 53 belong to the common circuit 13B for the column.

In addition to the first current supply unit 34, a second current supply unit 60 that supplies a current corresponding to the potential fluctuation of the floating diffusion FD accompanying the potential transition of the pixel control line 31 to the vertical signal line 32 is provided. It has been. The second current supply unit 60 is characterized in that the supply of current to the vertical signal line 32 is stopped in synchronization with the occurrence timing of the potential fluctuation of the floating diffusion FD. Here, the floating diffusion FD is a charge detection unit (charge voltage conversion unit) that converts the charge transferred from the photodiode PD into a voltage.

The second current supply unit 60 includes a switch element 61, a MOS transistor 62, a capacitor element 63, a switch element 64, a MOS transistor 65, and a current source 66. One end of the switch element 61 is connected to the end of the vertical signal line 32. The other end of the switch element 61 is connected to the drain electrode of the MOS transistor 62. That is, the MOS transistor 62 is connected to the end of the vertical signal line 32 via the switch element 61.

The capacitive element 63 is connected between the gate electrode and the source electrode of the MOS transistor 62. One end of the switch element 64 is connected to the gate electrode of the MOS transistor 62. The capacitive element 63 and the switch element 64 constitute a circuit that samples a current amount adjustment signal (bias voltage of the MOS transistor 62) for adjusting an additional current αI ₀ described later. The other end of the switch element 64 is connected to the gate electrode of the MOS transistor 65. The MOS transistor 65 has a diode connection configuration in which a gate electrode and a drain electrode are connected in common. The MOS transistor 62 and the MOS transistor 65 constitute a current mirror circuit by selectively connecting the gate electrodes via the switch element 64. The current source 66 is connected in series to the MOS transistor 52 and supplies a predetermined reference current to the MOS transistor 65.

The switch element 61 is controlled to be turned on (closed) / off (opened) by a control signal Φ _BST applied from the OR gate circuit 67 through the variable delay circuit 68. The OR gate circuit 67 has a drive signal for changing the potential of the floating diffusion FD, for example, a reset control signal RST and a transfer control signal TRG as two inputs. Thereby, the control signal Φ _BST is generated based on the reset control signal RST and the transfer control signal TRG. The variable delay circuit 68 may be appropriately adjusts the output timing of the control signals [Phi _BST. Switching element 64, the on / off control performed by the control signal [Phi _SH. Control signal [Phi _SH, in the circuit unit (not shown) is generated at a timing earlier by a predetermined time T than the generation timing of the control signals [Phi _BST. However, the switch element 64 and the control signal [Phi _SH is not a requirement.

The timing relationship of the reset control signal RST, the transfer control signal TRG, the control signal Φ _BST , and the control signal Φ _SH is shown in the timing waveform diagram of FIG. 4A.

In the current generation circuit having the above configuration, the first current supply unit 34 uses the vertical signal line 32 to output the current I ₀ determined by the reference current of the current source 53 when reading the pixel signal from the unit pixel 20 to the vertical signal line 32. To supply. As an example, the current I ₀ is about 4 μA. The second current supply unit 60 supplies an additional current αI ₀ to the vertical signal line 32 in addition to the current I ₀ . The additional current αI ₀ is a current corresponding to the potential change of the floating diffusion FD caused by the transition of the potential of the pixel control line 31, that is, the feedthrough accompanying the transition of the reset control signal RST and the transfer control signal TRG. It is determined by the reference current supplied from the current source 66 to the MOS transistor 65.

The second current supply unit 60 stops the supply of the additional current αI ₀ to the vertical signal line 32 in conjunction with the occurrence timing of the fluctuation of the floating diffusion FD. Here, “linked to the generation timing” is not limited to the same timing as the generation timing, in other words, may be a timing that is before or after the generation timing. Note that the stop timing of the additional current αI ₀ may be small enough to ignore the RC delay of the vertical signal line 32 with respect to the potential transition timing of the pixel control line 31. Control of the supply start / supply stop of the additional current αI ₀ to the vertical signal line 32 is based on a drive signal that changes the potential of the floating diffusion FD, in this example, the reset control signal RST and the transfer control signal TRG. Done.

Thus, by supplying the additional current αI ₀ to the vertical signal line 32, the overdrive voltage V _od of the source follower including the amplification transistor 23 changes in proportion to the following equation (5).

Here, when the gate-source voltage of the amplification transistor 23 is V _gs and the threshold voltage is V _th , the overdrive voltage V _od is V _od = V _gs −V _th . Β is a gain of the source follower, and V _od0 is an overdrive voltage when the additional current αI ₀ is not supplied to the vertical signal line 32.

On the other hand, regarding the potential change ΔV _FD of the floating diffusion FD caused by the feedthrough accompanying the transition of the potential of the pixel control line 31, the potential change ΔV _cnt of the pixel control line 31 and the pixel control line 31 -floating diffusion It can be expressed by the following equation (6) by the parasitic capacitance C ₁ between the FDs and the total parasitic capacitance C _{2 of} the floating diffusion FD-fixed potential wiring.

Due to the potential fluctuation (variation ΔV _FD ) of the floating diffusion FD, the potential fluctuation of the vertical signal line 32 occurs according to the gain β of the source follower. At this time, the potential variation ΔV _FT of the vertical signal line 32 is ΔV _FT = α · ΔV _FD .

Therefore, an overdrive voltage V _od equivalent to the potential fluctuation amount ΔV _FT when the potential of the vertical signal line 32 fluctuates in accordance with the feedthrough accompanying the transition of the potential of the pixel control line 31, and the additional current αI ₀ is vertically It is generated by supplying it to the signal line 32. Then, the supply of the additional current αI ₀ to the vertical signal line 32 is stopped in conjunction with the occurrence timing of the potential fluctuation of the floating diffusion FD. As a result, the potential variation ΔV _FT of the vertical signal line 32 is canceled by the overdrive voltage V _od . As a result, settling can be started from a voltage close to the final settling voltage of the vertical signal line 32.

The VSL settling time T _settle can be expressed by the following equation (7), where ΔV _VSL is the difference between the voltage at the start of settling and the final settling voltage.

As is clear from the equation (7), the smaller the error (difference ΔV _VSL ) of the voltage at the start of settling from the final settling voltage, the shorter the time necessary for settling, that is, the VSL settling time T _settle is set. Is possible.

When the signal after charge-voltage conversion in the floating diffusion FD is large, the source follower including the amplification transistor 23 becomes a cutoff region in the initial stage of settling, and the slew rate of the potential of the vertical signal line 32 is (1 + α ) Determined by I ₀ / C _VSL . Therefore, as a secondary _matter , the VSL settling time T _settle can be shortened. Here, C _VSL is a parasitic capacitance of the vertical signal line 32.

A signal waveform of each part of the circuit of FIG. 3 accompanying the transition of the transfer control signal TRG is shown in the timing waveform diagram of FIG. 4B. The timing waveform diagram of FIG. 4B shows the transfer control signal TRG, the potential of the vertical signal line 32 without the additional current αI ₀ , the current of the vertical signal line 32, the overdrive voltage V _od of the source follower, and the additional current αI. Each waveform of the potential of the vertical signal line 32 when _{0 is} present is shown.

Second Embodiment
The first embodiment is an example in which the additional current αI ₀ is fixed, that is, an example in which the current value is determined by a fixed reference current of the current source 66. On the other hand, the second embodiment is an example in which the additional current αI ₀ is variable in accordance with the potential variation ΔV _FT of the vertical signal line 32 for each semiconductor chip (each solid-state imaging device). The adjustment mechanism that adjusts the additional current αI ₀ in accordance with the potential variation ΔV _FT of the vertical signal line 32 may be mounted in the current generation circuit for each pixel column of the pixel array unit 11, or the current common to all the pixel columns. You may mount in a production | generation circuit. Hereinafter, a specific embodiment of the adjustment mechanism of the additional current αI ₀ will be described.

[Example 1]
The first embodiment is an example in which the adjustment mechanism for the additional current αI ₀ is mounted on the current generation circuit for each pixel column. FIG. 5 shows a configuration example of the current generation circuit according to the first embodiment. In the current generation circuit according to the first embodiment, in the second current source 2, the number of fingers (number of fingers) of the MOS transistor 62 of the in-column circuit constituting the current mirror circuit can be selected. Then, by switching the switch elements 69 ₁ to 69 _p based on the finger number selection control signal, an adjustment mechanism for the additional current αI ₀ is realized by selecting the number of fingers to be used from the number of fingers p of the MOS transistor 62. Yes.

[Example 2]
The second embodiment is an example (No. 1) in which the adjustment mechanism for the additional current αI ₀ is mounted on the current generation circuit in common to all the pixel columns. FIG. 6 shows a configuration example of the current generation circuit according to the second embodiment. In the current generation circuit according to the second embodiment, the second current source 2 can select the number of fingers of the MOS transistor 65 of the column common circuit that forms the current mirror circuit. Then, by switching the switch elements 69 ₁ to 69 _p based on the finger number selection control signal, an adjustment mechanism for the additional current αI ₀ is realized by selecting the number of fingers to be used from the number of fingers p of the MOS transistor 65. Yes.

[Example 3]
The third embodiment is an example (No. 2) in which the adjustment mechanism for the additional current αI ₀ is mounted on the current generation circuit in common to all the pixel columns. FIG. 7 shows a configuration example of a current generation circuit according to the third embodiment. In the current generation circuit according to the third embodiment, in the second current source 2, the reference current itself of the current source 66 that is input to the current mirror circuit or output from the current mirror circuit is based on the current amount adjustment signal. Thus, an adjustment mechanism for the additional current αI ₀ is realized.

Hereinafter, specific examples of determining the optimum value of the additional current αI ₀ will be described as a third embodiment and a fourth embodiment. In determining the optimum value of the additional current αI ₀ , the difference ΔV _VSL between the voltage at the start of settling and the final settling voltage and the variation ΔV _od of the overdrive voltage V _od of the source follower including the amplification transistor 23 are Detection (measurement) is performed during imaging (non-imaging) without image output, at startup, or during manufacturing (manufacturing process) of a solid-state imaging device. When measuring in the manufacturing process, the measurement result is stored in a non-volatile memory and used to set an additional current αI _{0 in} an arbitrary analog-digital converter (hereinafter referred to as “AD converter”). It is preferable to make it.

<Third Embodiment>
The third embodiment is an example in which the optimum value of the additional current αI ₀ is determined in the readout circuit 13 by using the AD converter 40 arranged for each pixel column. In the present embodiment, the AD converter 40 transmits the potential variation ΔV _FT of the floating diffusion FD accompanying the transition of the potential of the pixel control line 31 and the vertical signal line 32 from the second current supply unit 60. It functions as an acquisition means for acquiring the variation ΔV _od of the overdrive voltage V _od of the source follower accompanying the supply of the current.

In obtaining the potential variation ΔV _FT of the floating diffusion FD and the variation ΔV _od of the overdrive voltage V _od , it may be obtained as a variation of a specific pixel column, or a plurality of pixel columns ( You may make it acquire as an average fluctuation part (including all the pixel columns). Moreover, the acquisition result of 1 time may be sufficient and the average of the acquisition result of multiple times may be sufficient. The same applies to the fourth embodiment.

Hereinafter, a potential transition of the pixel control line 31 to produce a potential variation [Delta] V _FD of the floating diffusion FD, and is described as a transition of the reset control signal RST. The same applies to the fourth embodiment.

FIG. 8 shows a circuit configuration of a main part of the solid-state imaging device according to the third embodiment. The main circuit according to the third embodiment includes an intra-column circuit 13A and a column common circuit 13B (that is, a current generation circuit), and an additional current determination circuit 70 that determines an optimum value of the additional current αI ₀ .

The additional current determination circuit 70 includes a memory 71, a memory 72, a comparator 73, and a current selection circuit 74. The additional current determination circuit 70 has a potential variation ΔV _FT and a variation ΔV _{od of the} overdrive voltage V _od of the floating diffusion FD. As a means for obtaining the above, the AD converter 40 is used to determine the optimum value of the additional current αI ₀ .

The memory 71 sets the reset control signal RST to a high level, and sets the AD conversion result (1) of the voltage of the vertical signal line 32 when a sufficient settling time has elapsed and the reset control signal RST once to a high level. Later, it is set to a low level, and the difference from the AD conversion result (2) of the voltage of the vertical signal line 32 when a sufficient settling time has elapsed is stored. The difference between the AD conversion result (1) and AD conversion result (2) is equal to the potential variation [Delta] V _FD of the floating diffusion FD to those AD conversion.

The memory 72 sets the reset control signal RST to a high level once, supplies an additional current αI ₀ to the vertical signal line 32, and then the AD conversion result of the voltage of the vertical signal line 32 when a sufficient settling time has elapsed ( The difference between 3) and the above AD conversion result (1) is stored. The difference between the AD conversion result (3) and the AD conversion result (1) is equal to the AD conversion of the variation ΔV _od of the overdrive voltage V _od of the source follower. The comparator 73 compares the stored value in the memory 71 with the stored value in the memory 72. The current selection circuit 74 determines the optimum value of the additional current αI ₀ by controlling the current of the variable current source 66 based on the comparison result of the comparator 73, for example.

The procedure for determining the optimum value of the additional current αI ₀ by the additional current determination circuit 70 having the above configuration will be described with reference to the timing waveform diagram of FIG. 9A. Further, an image of a change in the voltage of the vertical signal line 32 due to a change in the additional current αI ₀ is shown in the waveform diagram of FIG. 9B.

1) First, the reset control signal RST is set to a high level, and the AD converter 40 converts the voltage of the vertical signal line 32 when a sufficient settling time has elapsed. Thereby, the AD conversion result (1) is obtained.
2) Next, the reset control signal RST is once set to a high level and then set to a low level, and the AD converter 40 AD converts the voltage of the vertical signal line 32 when a sufficient settling time has elapsed. Thereby, an AD conversion result (2) is obtained.
3) Next, after the reset control signal RST is once set to a high level and the additional current αI ₀ is supplied to the vertical signal line 32, the voltage of the vertical signal line 32 when a sufficient settling time has elapsed is converted into an AD converter. A / D conversion is performed at 40. Thereby, an AD conversion result (3) is obtained.
4) The additional current αI ₀ is swept by controlling the current of the variable current source 66, and the comparison result of the comparator 73, that is, the potential change ΔV _FD of the floating diffusion _FD and the overdrive voltage of the source follower a variation [Delta] V _od of V _od determines the additional current .alpha. I ₀ which is closest as the optimum value.

As described above, according to the additional current determination circuit 70 according to the third embodiment, the potential of the floating diffusion FD accompanying the transition of the potential of the pixel control line 31 based on the AD conversion result of the existing AD converter 40. The fluctuation amount and the fluctuation amount of the overdrive voltage of the source follower accompanying the supply of current from the second current supply unit 60 to the vertical signal line 32 can be acquired. Since the optimum value of the additional current αI ₀ supplied to the vertical signal line 32 can be determined based on these acquisition results, the setting of the additional current αI ₀ can be realized without adding a circuit, and each pixel column or two or more columns can be realized. There is an advantage that control can be performed in units of two or more pixel columns using the average value of the pixel columns.

<Fourth embodiment>
The fourth embodiment is an example in which the optimum value of the additional current αI ₀ is determined using voltage measuring means such as a voltmeter. In the present embodiment, the voltage measuring unit is configured to detect the potential variation ΔV _FT of the floating diffusion FD accompanying the potential transition of the pixel control line 31 and the vertical signal line 32 from the second current supply unit 60. It functions as an acquisition means for acquiring the variation ΔV _od of the overdrive voltage V _od of the source follower accompanying the current supply. The voltage measuring means may be a measuring device outside the solid-state image sensor, or may be an AD converter different from the AD converter 40 mounted on the solid-state image sensor. When a measuring device outside the solid-state image sensor is used as the voltage measuring means, it has a mechanism for outputting a signal obtained by short-circuiting a specific vertical signal line 32 or a plurality of vertical signal lines 32 to the outside of the solid-state image sensor. .

FIG. 10 shows a circuit configuration of a main part of the solid-state imaging device according to the fourth embodiment. As evident from comparison of FIGS. 8 and 10, basically, as a means for obtaining a variation [Delta] V _od of the floating diffusion FD potential variation [Delta] V _FT and the overdrive voltage V _od, the AD converter 40 Instead, the configuration other than using the voltage measuring means 80 is the same as that of the third embodiment. Further, not only the configuration but also the procedure for determining the optimum value of the additional current αI ₀ is basically the same as in the case of the third embodiment.

According to the additional current determination circuit 70 according to the fourth embodiment that uses voltage measuring means such as a voltmeter, the AD converter 40 has a configuration that is higher than that of the additional current determination circuit 70 according to the third embodiment that uses the AD converter 40. There is an advantage that a voltage change can be detected with a voltage accuracy exceeding the resolution.

The additional current αI ₀ for which the optimum value is determined by the additional current determination circuit 70 according to the third embodiment or the fourth embodiment is applied to the setting at the time of imaging accompanied by image output. At this time, the current control voltage may be sampled and held in a state where the additional current αI ₀ is not supplied. Thus, the second current supply portions 60 for generating an additional current .alpha. I _0, prevents current value IR drop varies during the supply of the additional current .alpha. I _0, the optimum additional current .alpha. I ₀ in all pixel rows Supply can be realized.

<Modification>
Although the present disclosure has been described based on the preferred embodiments, the present disclosure is not limited to these embodiments. The configuration and structure of the solid-state imaging device described in the above embodiments and the configuration of the driving method of the solid-state imaging device are examples, and can be changed as appropriate. For example, as the fixed potential wiring of the second current supply unit 60 that generates the additional current αI ₀ , the first current supply unit 34 that generates the current I ₀ used for the settling of the final vertical signal line 32 is fixed. It may be the same as the potential wiring, but is preferably separated. By separating these fixed potential wirings, fluctuations in the fixed potential accompanying the start / stop of supply of the additional current αI ₀ can be prevented.

<Electronic device of the present disclosure>
The solid-state imaging device according to the first to fourth embodiments described above uses a solid-state imaging device for an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function such as a mobile phone, or an image reading unit. It can be used as an imaging unit (image capturing unit) in electronic devices such as copying machines. In some cases, the above-described module form mounted on an electronic device, that is, a camera module is used as an imaging device.

[Imaging device]
FIG. 11 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure. As shown in FIG. 11, an imaging apparatus 100 according to this example includes an optical system 101 including a lens group, an imaging unit 102, a DSP circuit 103 that is a camera signal processing unit, a frame memory 104, a display device 105, and a recording device 106. , An operation system 107, a power supply system 108, and the like. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

The optical system 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102. The imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal. The DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.

The frame memory 104 is used for storing data as appropriate during the signal processing in the DSP circuit 103. The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the imaging unit 102. The recording device 106 records the moving image or still image captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disk, or an HDD (Hard Disk Disk Drive).

The operation system 107 issues operation commands for various functions of the imaging apparatus 100 under the operation of the user. The power supply system 108 appropriately supplies various power supplies serving as operation power for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

In the imaging apparatus 100 having the above configuration, the solid-state imaging device according to the first embodiment, the second embodiment, the third embodiment, or the fourth embodiment described above can be used as the imaging unit 102.

In addition, this indication can also take the following structures.
[1] A unit pixel including a charge detection unit that converts a charge obtained by photoelectric conversion into a voltage,
A vertical signal line shared by one or more unit pixels,
A pixel control line for controlling the unit pixel,
A first current supply unit for supplying a current to the vertical signal line when reading a signal from the unit pixel to the vertical signal line; and
A second current supply unit configured to supply a current corresponding to a potential variation of the charge detection unit accompanying the transition of the potential of the pixel control line to the vertical signal line;
The second current supply unit stops supplying current to the vertical signal line in conjunction with the occurrence timing of the potential fluctuation of the charge detection unit;
Solid-state image sensor.
[2] The unit pixel includes a transfer transistor that transfers the charge obtained by photoelectric conversion to the charge detection unit,
The pixel control line transmits a transfer control signal that drives the transfer transistor,
The second current supply unit stops supplying current to the vertical signal line in conjunction with the transition timing of the transfer control signal.
The solid-state imaging device according to [1] above.
[3] The unit pixel includes a reset transistor that resets the charge detection unit,
The pixel control line transmits a reset control signal for driving the reset transistor,
The second current supply unit stops supplying the current to the vertical signal line in conjunction with the transition timing of the reset control signal;
The solid-state imaging device according to the above [1] or [2].
[4] The unit pixel has an amplification transistor that reads the voltage converted by the charge detection unit to the vertical signal line,
The amplification transistor and the first current supply unit constitute a source follower that converts the voltage converted by the charge detection unit into the potential of the vertical signal line,
The second current supply unit generates an overdrive voltage of the source follower equivalent to the potential fluctuation of the charge detection unit by supplying a current to the vertical signal line.
The solid-state imaging device according to any one of [1] to [3] above.
[5] The second current supply unit has a configuration in which the current supplied to the vertical signal line is variable.
The solid-state imaging device according to any one of [1] to [4] above.
[6] A change in the potential of the charge detection unit due to the transition of the potential of the pixel control line, and a change in the overdrive voltage of the source follower accompanying the supply of current from the second current supply unit to the vertical signal line. It has an acquisition means to acquire,
The second current supply unit sets a current to be supplied to the vertical signal line based on the acquisition result of the acquisition unit.
The solid-state imaging device according to [4] above.
[7] The acquisition unit acquires the variation of a specific pixel column or the average variation of a plurality of pixel columns.
The solid-state imaging device according to [6] above.
[8] The second current supply unit converts the current that causes the potential fluctuation of the charge detection unit and the fluctuation of the overdrive voltage to be the closest to the potential fluctuation of the charge detection unit accompanying the transition of the potential of the pixel control line. Set as the corresponding current,
The solid-state imaging device according to [6] or [7].
[9] The second current supply unit samples a current amount adjustment signal for adjusting a current supplied to the vertical signal line.
The solid-state imaging device according to [5] above.
[10] A readout circuit unit connected to the vertical signal line is provided,
The readout circuit unit functions as an acquisition unit.
The solid-state imaging device according to [6] above.
[11] The read circuit unit samples and holds the voltage of the vertical signal line.
The solid-state imaging device according to [10] above.
[12] The acquisition unit is a voltage measurement unit provided outside or inside the solid-state imaging device.
The solid-state imaging device according to [6] above.
[13] The fixed potential wiring of the first current supply unit and the fixed potential wiring of the second current supply unit are separated.
The solid-state imaging device according to any one of [1] to [12].
[14] A unit pixel including a charge detection unit that converts a charge obtained by photoelectric conversion into a voltage,
A vertical signal line shared by one or more unit pixels, and
It has a pixel control line that controls the unit pixel,
Solid that supplies current to the vertical signal line when reading a signal from the unit pixel to the vertical signal line, and supplies current to the vertical signal line corresponding to the potential fluctuation of the charge detection unit due to the potential transition of the pixel control line In driving the image sensor,
Stop the supply of current to the vertical signal line in conjunction with the occurrence timing of the potential fluctuation of the charge detection unit,
A method for driving a solid-state imaging device.
[15] The unit pixel includes a transfer transistor that transfers the charge obtained by photoelectric conversion to the charge detection unit,
The pixel control line transmits, and stops the supply of current to the vertical signal line in conjunction with the transition timing of the transfer control signal that drives the transfer transistor.
The method for driving a solid-state imaging device according to the above [14].
[16] The unit pixel includes a reset transistor that resets the charge detection unit.
The supply of current to the vertical signal line is stopped in conjunction with the transition timing of the reset control signal that drives the reset transistor transmitted by the pixel control line.
The method for driving a solid-state imaging device according to the above [14] or [15].
[17] The unit pixel has an amplification transistor that reads the voltage converted by the charge detection unit to the vertical signal line,
The amplification transistor and the first current supply unit constitute a source follower that converts the voltage converted by the charge detection unit into the potential of the vertical signal line,
An overdrive voltage of the source follower equivalent to the potential fluctuation of the charge detection unit is generated by supplying a current to the vertical signal line.
The method for driving a solid-state imaging device according to any one of [14] to [16].
[18] A change in potential of the charge detection unit accompanying a transition in potential of the pixel control line and a change in overdrive voltage of the source follower accompanying the supply of current from the second current supply unit to the vertical signal line. Acquire and set the current supplied to the vertical signal line based on the acquisition result,
The method for driving a solid-state imaging device according to the above [17].
[19] Obtain as a variation of a specific pixel column or an average variation of a plurality of pixel columns.
The method for driving a solid-state imaging device according to the above [18].
[20] A unit pixel including a charge detection unit that converts a charge obtained by photoelectric conversion into a voltage,
A vertical signal line shared by one or more unit pixels,
A pixel control line for controlling the unit pixel,
A first current supply unit for supplying a current to the vertical signal line when reading a signal from the unit pixel to the vertical signal line; and
A second current supply unit configured to supply a current corresponding to a potential variation of the charge detection unit accompanying the transition of the potential of the pixel control line to the vertical signal line;
The second current supply unit stops supplying current to the vertical signal line in conjunction with the occurrence timing of the potential fluctuation of the charge detection unit;
An electronic device having a solid-state image sensor.

DESCRIPTION OF SYMBOLS 10 ... Solid-state image sensor, 11 ... Pixel array part, 12 ... Row scanning part, 13 ... Reading circuit part, 13A ... In-column circuit, 13B ... Common circuit for columns, 15 ... Column scanning unit, 16 ... Horizontal output line, 17 ... Video signal processing unit, 18 ... Timing control unit, 20 ... Unit pixel, 21 ... Transfer transistor, 22 ... Reset transistor, 23... Amplification transistor, 24... Selection transistor, 30... Semiconductor substrate (semiconductor chip), 31 ( _{31.sub._1} to _{31.sub .-- m} )... Pixel control line, 32 ( _{32.sub._1} to _{32.sub .--} _n) ) ... vertical signal line, 34 ... first current supply unit, 40 ( _{40_1} to _{40_n} ) ... AD (analog-digital) converter, 41 ... comparator (comparator), 42 ... Up / down counter, 43 Latch circuit 60 ... second current supply unit 70 ... additional current determination circuit 71,72 ... memory 73 ... comparator 74 ... current selection circuit 80 ...・ Voltage measuring means, FD: Floating diffusion (charge detection unit / charge voltage conversion unit), PD: Photodiode (photoelectric conversion element)

Claims

A unit pixel including a charge detection unit that converts a charge obtained by photoelectric conversion into a voltage;
A vertical signal line shared by one or more unit pixels,
A pixel control line for controlling the unit pixel,
A first current supply unit for supplying a current to the vertical signal line when reading a signal from the unit pixel to the vertical signal line; and
A second current supply unit configured to supply a current corresponding to a potential variation of the charge detection unit accompanying the transition of the potential of the pixel control line to the vertical signal line;
The second current supply unit stops supplying current to the vertical signal line in conjunction with the occurrence timing of the potential fluctuation of the charge detection unit;
Solid-state image sensor.
The unit pixel has a transfer transistor that transfers the charge obtained by photoelectric conversion to the charge detection unit,
The pixel control line transmits a transfer control signal that drives the transfer transistor,
The second current supply unit stops supplying current to the vertical signal line in conjunction with the transition timing of the transfer control signal.
The solid-state imaging device according to claim 1.
The unit pixel has a reset transistor that resets the charge detection unit,
The pixel control line transmits a reset control signal for driving the reset transistor,
The second current supply unit stops supplying the current to the vertical signal line in conjunction with the transition timing of the reset control signal;
The solid-state imaging device according to claim 1.
The unit pixel has an amplification transistor that reads the voltage converted by the charge detection unit to the vertical signal line,
The amplification transistor and the first current supply unit constitute a source follower that converts the voltage converted by the charge detection unit into the potential of the vertical signal line,
The second current supply unit generates an overdrive voltage of the source follower equivalent to the potential fluctuation of the charge detection unit by supplying a current to the vertical signal line.
The solid-state imaging device according to claim 1.
The second current supply unit has a configuration in which the current supplied to the vertical signal line is variable.
The solid-state imaging device according to claim 1.
Acquisition for acquiring a potential fluctuation of the charge detection unit accompanying a transition of the potential of the pixel control line and a fluctuation of the overdrive voltage of the source follower accompanying the supply of current to the vertical signal line from the second current supply unit Means,
The second current supply unit sets a current to be supplied to the vertical signal line based on the acquisition result of the acquisition unit.
The solid-state imaging device according to claim 4.
The acquisition means acquires the variation of a specific pixel column or the average variation of a plurality of pixel columns.
The solid-state imaging device according to claim 6.
The second current supply unit uses a current corresponding to the potential variation of the charge detection unit accompanying the transition of the potential of the pixel control line as a current at which the potential variation of the charge detection unit and the variation of the overdrive voltage are closest. Set as
The solid-state imaging device according to claim 6.
The second current supply unit samples a current amount adjustment signal for adjusting a current supplied to the vertical signal line.
The solid-state imaging device according to claim 5.
It has a readout circuit part connected to the vertical signal line,
The readout circuit unit functions as an acquisition unit.
The solid-state imaging device according to claim 6.
The readout circuit section samples and holds the voltage of the vertical signal line.
The solid-state imaging device according to claim 10.
The acquisition means is a voltage measurement means provided outside or inside the solid-state imaging device,
The solid-state imaging device according to claim 6.
The fixed potential wiring of the first current supply unit and the fixed potential wiring of the second current supply unit are separated.
The solid-state imaging device according to claim 1.
A unit pixel including a charge detection unit that converts a charge obtained by photoelectric conversion into a voltage;
A vertical signal line shared by one or more unit pixels, and
It has a pixel control line that controls the unit pixel,
Solid that supplies current to the vertical signal line when reading a signal from the unit pixel to the vertical signal line, and supplies current to the vertical signal line corresponding to the potential fluctuation of the charge detection unit due to the potential transition of the pixel control line In driving the image sensor,
Stop the supply of current to the vertical signal line in conjunction with the occurrence timing of the potential fluctuation of the charge detection unit,
A method for driving a solid-state imaging device.
The unit pixel has a transfer transistor that transfers the charge obtained by photoelectric conversion to the charge detection unit,
The pixel control line transmits, and stops the supply of current to the vertical signal line in conjunction with the transition timing of the transfer control signal that drives the transfer transistor.
The method for driving a solid-state imaging device according to claim 12.
The unit pixel has a reset transistor that resets the charge detection unit,
The supply of current to the vertical signal line is stopped in conjunction with the transition timing of the reset control signal that drives the reset transistor transmitted by the pixel control line.
The method for driving a solid-state imaging device according to claim 14.
The unit pixel has an amplification transistor that reads the voltage converted by the charge detection unit to the vertical signal line,
The amplification transistor and the first current supply unit constitute a source follower that converts the voltage converted by the charge detection unit into the potential of the vertical signal line,
An overdrive voltage of the source follower equivalent to the potential fluctuation of the charge detection unit is generated by supplying a current to the vertical signal line.
The method for driving a solid-state imaging device according to claim 14.
Obtaining the potential fluctuation amount of the charge detection unit accompanying the transition of the potential of the pixel control line and the fluctuation amount of the overdrive voltage of the source follower accompanying the current supply from the second current supply unit to the vertical signal line, Based on this acquisition result, the current supplied to the vertical signal line is set.
The method for driving a solid-state imaging device according to claim 17.
Obtain as a variation of a specific pixel column or an average variation of a plurality of pixel columns,
The method for driving a solid-state imaging device according to claim 18.
A unit pixel including a charge detection unit that converts a charge obtained by photoelectric conversion into a voltage;
A vertical signal line shared by one or more unit pixels,
A pixel control line for controlling the unit pixel,
A first current supply unit for supplying a current to the vertical signal line when reading a signal from the unit pixel to the vertical signal line; and
A second current supply unit configured to supply a current corresponding to a potential variation of the charge detection unit accompanying the transition of the potential of the pixel control line to the vertical signal line;
The second current supply unit stops supplying current to the vertical signal line in conjunction with the occurrence timing of the potential fluctuation of the charge detection unit;
An electronic device having a solid-state image sensor.