JP2012109888A - Solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device of high picture quality with reduced horizontal line noise.SOLUTION: One embodiment of the solid state image pickup device of present invention is a solid state image pickup device which reads a pixel signal from a unit pixel Pnm selected in units of row. It includes an amplifying transistor M4 contained in each unit pixel, a first transistor MLm which is provided to each row and supplies a bias current to the amplifying transistor M4 that belongs to a selected row, a primary side mirror transistor MF which is a current source for generating a reference bias voltage, a first bias signal line which transmits the reference bias voltage to a gate terminal of the first transistor MLm from a gate terminal of the primary side mirror transistor MF of the current source, and a sample hold circuit 250 which is inserted into a bias signal line between the gate terminal of the primary side mirror transistor MF of the current source and the gate terminal of each first transistor MLm.

Description

  The present invention relates to a solid-state imaging device, a camera, and a driving method for the solid-state imaging device that are widely used in image input devices especially for video cameras and digital still cameras.

  In a conventional solid-state imaging device, particularly in a column parallel output type MOS image sensor that selects pixels in a certain row in an imaging region and reads out pixel signals generated by the selected pixels in parallel via column signal lines, A correlated double sampling (CDS) circuit is provided for each column of multiple or single pixel units, and the signal component of the pixel is correlated double detection of the reset component and the data component (= reset component + signal component) It is detected by doing.

  In recent years, since the resolution of a solid-state imaging device has been increased, lower noise is desired more than ever. In general, noise generated from a solid-state imaging device can be roughly classified into horizontal line noise and vertical line noise depending on the type.

  Most of the vertical line noise is caused by FPN (Fixed Pattern Noise), and the column in which the noise is generated is fixed for each device. Therefore, a DSP (Digital Signal Processor) connected to the subsequent stage of the solid-state imaging device. ) And other correction techniques can be optimized for each device and most of them can be removed.

  On the other hand, the horizontal line noise includes random horizontal line noise peculiar to a column parallel output type image sensor, and high-intensity streaking in which the row where the noise occurs corresponds to the high-intensity part of the subject. These cannot be corrected for each device, and reduction of the absolute amount is desired.

  In general, random noise generated randomly on the entire screen is difficult to visually recognize, but horizontal line noise is easily visually recognized. Therefore, specifically, the horizontal line noise needs to be reduced to about 1/10 times that of the random noise. Patent Document 1 discloses a technique that can improve horizontal line noise.

  FIG. 6 shows a conventional method described in Patent Document 1. The bias currents Ibias1 to Ibiasm flowing in the column signal lines VL1 to VLm are determined by applying the output voltage of the pixel amplification transistor M3 to the gate terminals via the drain terminals of the load transistors ML1 to MLm of the constant current circuit 242. Determined by a so-called self-bias method. In the CDS period, the voltage difference Vgs between the gate terminal and the source terminal becomes constant by the capacitive element C1 connected between the gate terminal and the source terminal of the load transistors ML1 to MLm of the constant current circuit 242, and the constant current is Flowing.

  According to this configuration, since the gate terminal is not connected to each column and is independent, random horizontal noise specific to the column parallel output type image sensor is reduced. Further, during the period of reading out the reset component and the data component (= reset component + signal component) by correlated double detection (CDS), the load transistors ML1 to MLm of the constant current circuit 242 are connected between the gate terminals and the source terminals. Since the voltage of the voltage difference Vgs between the gate terminal and the source terminal is made constant by the capacitive element C1, even if the voltage drop of the GND line fluctuates, the bias currents Ibias1 to Ibiasm become constant current, and high luminance streaking is reduced. .

Japanese Patent No. 3500761

  However, although the prior art disclosed in Patent Document 1 can reduce horizontal noise, it has the following two problems.

  The first problem is that it is difficult to realize low power consumption. In the conventional method, the bias currents Ibias1 to Ibiasm flowing through the constant current circuit 242 are determined by applying the output voltage of the pixel amplification transistor M3 to the gate terminal via the drain terminal, and are determined by a so-called self-bias method. The For this reason, there is a problem that variation variation is large. In particular, the size of the amplifying transistor M3 of the pixel is fine, and the influence of this variation is remarkable. In addition, the number of pixel defects has been increased due to the miniaturization of process rules accompanying the recent increase in the number of pixels (for example, 10 million pixels or more), and the variation factors of the bias currents Ibias1 to Ibiasm have increased.

  That is, since this bias current is generated by the self-bias method, it is greatly affected by power supply voltage fluctuations, temperature fluctuations, and device variations. Specifically, there is no accuracy of the order of 1 μA that is required in recent years, and it has therefore been difficult to reduce power consumption. That is, it is necessary to flow an excessive current at the typ setting in consideration of the minimum value of variation, and even if the required current per column is 2 μA, the typ setting is set to 10 μA in consideration of the minimum value of variation. Then, assuming that Vdd = 3.3V and 3000 columns, the power consumption is excessively consumed as Vdd · (10 μA−2 μA) · 3000 columns = 79 mW.

  For this reason, the conventional technology has a problem with respect to the deterioration of heat dissipation due to the recent downsizing of the camera set, and the development of technology for reducing power consumption is an urgent task.

  The second problem is the deterioration of the linearity of the output voltage of the amplification transistor M3 with respect to the luminance level detected by the photo detector D1. The conventional method aims to hold the voltage difference Vgs between the gate terminal and the source terminal by the capacitive element C1 connected between the gate terminal and the source terminal of the load transistors ML1 to MLm.

  However, when the column signal lines VL1 to VLm change, the voltage Vgs changes due to the parasitic capacitance Cgd1 between the load transistors ML1 to MLm. That is, the currents Ibias1 to Ibiasm flowing through the constant current circuit 252 vary according to the output voltage of the amplification transistor M3, and linearity degradation occurs.

  In particular, since the parasitic capacitance Cgd1 is not managed in the diffusion process, the parasitic capacitance Cgd1 has a relative variation for each column, and the linearity is different for each column.

  Therefore, the present invention has been made in view of the above-described conventional problems, and the object thereof is a solid state that realizes high image quality and low power consumption capable of improving horizontal line noise that is easily visually recognized. An imaging device, a camera, and a driving method of a solid-state imaging device are provided.

  In particular, regarding low power consumption, it is suitable for downsizing of recent camera sets.

  In order to solve the above-described problem, a solid-state imaging device according to one aspect of the present invention is a solid-state imaging device that reads a pixel signal from unit pixels that are selected in rows and have a plurality of unit pixels arranged in a matrix. , An amplification transistor included in each of the plurality of unit pixels and outputting a pixel signal; a column signal line from which the amplified signal is read; and a bias current applied to the amplification transistor belonging to the selected row provided for each column. And a drain terminal and a gate terminal are short-circuited, and a first reference bias voltage is generated at the gate terminal by a constant reference bias current supplied between the source terminal and the drain terminal. From the gate terminal of the second transistor and the second transistor to the gate terminal of each of the first transistors, the first reference Transmitting a bias voltage to mirror the bias current with respect to the reference bias current; the gate terminal of the second transistor; and the gate of each first transistor. And a first sample and hold circuit inserted in the first bias signal line between the terminals.

  According to this configuration, the sample and hold circuit can remove a noise component generated in the second transistor that generates the reference bias current of the current mirror. Finally, noise components can be removed from the pixel signal output from the amplification transistor, and horizontal line noise can be effectively reduced. As a result, a high-quality image can be obtained.

  Here, the first sample-and-hold circuit includes a first switch element inserted in the first bias signal line between the gate terminal of the second transistor and the gate terminal of each first transistor. And a first capacitor connected to the gate terminal and the source terminal of the first transistor.

  According to this configuration, the first sample and hold circuit can be formed by a simple circuit including a switch element and a capacitor element.

  Here, each of the unit pixels includes a photodiode that changes light into a signal charge, a floating diffusion layer that holds the signal charge, a reset transistor that resets the signal charge in the floating diffusion layer, and a floating state from the photodiode. A transfer transistor for transferring a signal charge to the diffusion layer; and an amplification transistor for outputting the pixel signal corresponding to the signal charge held in the floating diffusion layer, wherein the first switch element is a reset transistor The bias hold period from the first read period including the reset operation to the second read period including the transfer operation by the transfer transistor may be off, and may be turned on when the bias hold period is completed.

  According to this configuration, during the read period including the reset operation by the reset transistor and the CDS period until the read period including the transfer operation by the transfer transistor, the charge is held in the capacitor and becomes a constant voltage. As a result, the DC component of the noise superimposed on the capacitive element at the moment of sampling by the switch element can be completely canceled by the subsequent CDS circuit, and the horizontal noise can be effectively reduced. As a result, a high-quality image can be obtained.

  Here, the solid-state imaging device includes a third transistor that is provided for each column and makes the voltage of the drain terminal of the first transistor that supplies a bias current to the amplification transistor belonging to the selected row constant. , A source terminal of the third transistor is connected to a drain terminal of the first transistor, a drain terminal of the third transistor is connected to the column signal line, and a gate terminal of the third transistor is a second terminal. The second reference bias voltage may be applied from a bias circuit connected via the bias signal line.

  According to this configuration, it is possible to eliminate the deterioration of the linearity of the output voltage according to the luminance level of the pixel.

  Here, the solid-state imaging device may include a second sample and hold circuit inserted in the second bias signal line between the bias circuit and the gate terminal of each third transistor. .

  According to this configuration, the sample and hold circuit can remove a noise component generated by the cascode transistor bias circuit. Finally, noise components can be removed from the pixel signal output from the amplification transistor, and horizontal line noise can be effectively reduced. As a result, a high-quality image can be obtained.

  Here, the second sample-and-hold circuit includes a second switch element inserted in the second bias signal line between the bias circuit and the gate terminal of each third transistor, and the third switch element. A second capacitor connected to the gate terminal of the transistor and a source terminal on the first transistor side.

  According to this configuration, the second sample and hold circuit can be formed by a simple circuit including a switch element and a capacitor element.

  Here, the second switch element is off during a bias hold period from a first read period including a reset operation by the reset transistor to a second read period including a transfer operation by the transfer transistor, It may be turned on when the bias hold period is completed.

  According to this configuration, during the read period including the reset operation by the reset transistor and the CDS period until the read period including the transfer operation by the transfer transistor, the charge is held in the capacitor and becomes a constant voltage. As a result, the DC component of the noise superimposed on the capacitive element at the moment of sampling by the switch element can be completely canceled by the subsequent CDS circuit, and the horizontal noise can be effectively reduced. As a result, a high-quality image can be obtained.

  Here, the first capacitor element and the second capacitor element are MOS type capacitors, and a first metal wiring is formed above the first drain end and the first source end of the first capacitor element. A first metal wiring layer over the second drain end and the second source end of the second capacitor element, the first drain end, the first source end, The second drain end and the second source end may be shielded from light by the first metal wiring layer.

  According to this configuration, a drain end and a source end having a PN junction when high-intensity light enters during a read period including a reset operation by a reset transistor and a CDS period from a read period including a transfer operation by the transfer transistor. Unnecessary charges generated in the can be suppressed.

  Here, the first capacitor element and the second capacitor element are MIM type capacitors, the second metal wiring layer constituting one electrode of the first capacitor element is at the GND potential, The second metal wiring layer constituting one electrode of the two capacitor elements may be at the GND potential.

  According to this configuration, since the diffusion layer is not used and the wiring layer can be used, an increase in chip size can be suppressed.

  In addition, the driving method of the camera and the solid-state imaging device according to one embodiment of the present invention has the same configuration as described above.

  According to the solid-state imaging device according to the present invention, it is possible to effectively reduce the horizontal line noise generated in the high-resolution solid-state imaging device, and to realize the coexistence with low power consumption.

It is a circuit diagram which shows the structure of the solid-state imaging device which can implement | achieve both reduction of horizontal line noise and low power consumption concerning Embodiment 1 of this invention. It is a timing chart which concerns on embodiment of this invention. It is a circuit diagram which shows the structure of the solid-state imaging device which can implement | achieve coexistence of reduction of horizontal line noise and low power consumption concerning Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the solid-state imaging device which can implement | achieve coexistence of reduction of horizontal line noise and low power consumption concerning Embodiment 3 of this invention. 1 is a circuit diagram illustrating a configuration of a backside illumination type solid-state imaging device according to Embodiment 1 of the present invention. FIG. It is a circuit diagram which shows the structure of the solid-state imaging device in a prior art.

(First embodiment)
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a first embodiment of the invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a solid-state imaging device according to an embodiment of the present invention.

  As shown in FIG. 1, the solid-state imaging device is a column parallel output type image sensor, and includes a pixel array 200, a constant current circuit 252, a timing generator 1, and a row scanning circuit 2. The pixel array 200 includes unit pixels P11 to Pnm arranged in an n × m matrix. The constant current circuit 252 is connected to the unit pixels P11 to Pnm via the column signal lines VL1 to VLm.

  In such a configuration, a CDS circuit that performs correlated double detection for each column is arranged on the rear stage side of the pixel array 200, and voltages indicating pixel signals are output from the output terminals Vout1 to Voutm. The In the CDS operation, when the reset component and the data component (= reset component + signal component) are read, the pixels in the selected row (row) of the pixel array 200 are simultaneously applied to the CDS circuit provided for each column with the same clock. Communicate the signal. Each CDS circuit sequentially transmits the acquired pixel signal to the subsequent stage.

  Even if the CDS circuit is an analog type CDS system that detects the analog signal of the reset component and the data component in a correlated double manner, the digital signal of the reset component and the data component that are digitally converted by the AD conversion means is detected in a correlated double manner. The digital CDS method may be used. In the correlated double detection, conventionally, in the detection of the pixel signal, a means for detecting the signal component by detecting the analog signal of the reset component and the data component (= reset component + signal component) by the correlated double detection has been taken. . Recently, in order to further reduce noise and speed, digital signals of reset components and data components (= reset components + signal components) digitally converted by AD conversion means provided for each column in pixel signal detection In some cases, a means for detecting by detecting correlated double is taken.

  The constant current circuit 252 is connected to the column signal lines VL1 to VLm, and load transistors ML1 to MLm provided for each column, and a primary side mirror of a current source that forms a current mirror circuit with these transistors. The transistor MF is configured.

  The load transistors ML1 to MLm are provided for each column, and supply a bias current to the amplification transistors M3 belonging to the selected row. One load transistor and one amplification transistor M3 belonging to the selected row form a source follower circuit.

  In the primary side mirror transistor MF of the constant current circuit 252, the drain terminal and the gate terminal are short-circuited, the drain terminal is connected to the current source 251 and the source terminal is grounded. As a result, the primary side mirror transistor MF of the current source generates a constant reference bias current between the source terminal and the drain terminal, and generates a reference bias voltage VbiasL at the gate terminal.

  The gate terminal of the primary side mirror transistor MF of the constant current circuit 252 and the gate terminals of the load transistors ML1 to MLm are connected by a bias signal line. This bias signal line supplies a reference bias voltage VbiasL from the gate terminal of the primary side mirror transistor MF of the current source to the gate terminals of the load transistors ML1 to MLm. The primary mirror transistor MF of the current source and the load transistors ML1 to MLm constitute a current mirror. With respect to the reference bias current Ibias, the bias current of each load transistor is a mirror current. The mirror ratio may be 1: 1 or may be an arbitrarily determined ratio, and the current can be accurately set.

  Further, among the unit pixels P11 to Pnm, for example, the unit pixel P11 includes one photo detection unit D1 that receives light and generates photocharges, and four MOS transistors M1, M2, M3, and M4. .

  These four MOS transistors set the potential of the floating diffusion region to a desired value by setting the potential of the floating diffusion region to the transfer transistor M1 for transferring the photocharge collected by the photodetection unit D1 to the floating diffusion region. A reset transistor M2 for discharging and resetting the floating diffusion region, an amplifying transistor M3 that acts as a source follower buffer amplifier when the voltage of the floating diffusion region is applied to the gate, and functions as an address by switching This is the selection transistor M4.

  In the above-described operation, among the unit pixels P11 to Pnm, the voltage of the photo detection unit D1 is determined according to the brightness of ambient light. For example, the photo detector D1 that receives bright light generates a low voltage, while the photo detector D1 that receives dark light generates a relatively high voltage.

  As described above, the voltage of the node FD1 forms a source follower circuit by the amplification transistor M3 of the pixel in the selected row and the load transistors ML1 to MLm constituting the constant current circuit 252, and outputs each of the column signal lines VL1 to VLm. The output voltages of the terminals Vout1 to Voutm are determined by the voltage of the node FD1 in the selected row and the currents Ibias1 to Ibiasm flowing through the load transistors ML1 to MLm.

(Configuration of the present invention)
The gate terminal of the primary side mirror transistor MF of the constant current circuit 252 generates a reference bias voltage VbiasL. A sample and hold circuit 250 is inserted between the gate terminal of the primary side mirror transistor MF and the gate terminals of the load transistors ML1 to MLm, and includes a switch element SW1 and a capacitive element C1. When the switch element SW1 is turned on, the reference bias voltage VbiasL is supplied to the capacitive element C1. On the contrary, if the switch element SW1 is turned off, the voltage difference between the gate terminal and the source terminal of each load transistor ML1 to MLm is held at a constant value.

  At this time, if the capacitive element C1 is a MOS type capacitor, the drain end and the source end of the capacitive element C1 must be covered with a metal wiring layer to be shielded from light, and unnecessary charges generated at these PN junctions must be suppressed.

  If the capacitor C1 is an MIM capacitor, the metal wiring layer constituting one electrode of the capacitor C1 may be connected to the source terminals of the load transistors ML1 to MLm as the GND potential. According to this configuration, since the diffusion layer is not used and the wiring layer can be used, an increase in chip size can be suppressed.

  Capacitance elements C1 and C2 may use parasitic capacitances between the gate terminals and back gate terminals of transistors ML1 to MLm and MC1 to MCm, respectively.

(Random horizontal noise)
Several factors can be considered for the horizontal line noise. One of them is a phenomenon in which a horizontal line appears randomly in a horizontal direction in a subject having dark to low illuminance on the screen, and is also called random horizontal line noise.

  This phenomenon is peculiar to the column parallel output type image sensor. In particular, in the configuration in which the gate terminals of the load transistors (load transistors) are connected to all the columns, the AC noise superimposed on the gate voltage of the load transistors causes the pixel amplification. It occurs because it appears as the output voltage of the transistor, and appears as a horizontal line on the screen.

(High brightness streaking)
Another factor causing horizontal line noise is a phenomenon in which a whitish band appears in the horizontal direction in a region where a bright high-brightness object is present on the screen, which is also called high-brightness streaking.

  This phenomenon is because the output signal of the pixels in the same row as the bright subject is relatively smaller than the output signals of the pixels above and below the row due to the influence of the bright subject. Occurs because a band occurs, and appears as a horizontal band on the screen. The generation mechanism of the high-intensity streaking is that when a high-intensity signal is incident, the bias current Ibiasx of the column in which the high-intensity is incident is reduced due to the short channel effect of the load transistor MLx in the corresponding column, so that the voltage of the GND line The descent is reduced. As a result, the voltage difference Vgs between the gate terminal and the source terminal of the column where the high luminance is not incident increases, the bias currents Ibias1 to Ibiasm of all the columns increase, and the pixel including the high luminance is included. In the line, a whitish band occurs.

  The prior art for reducing high-intensity streaking and its problems are as described above. Hereinafter, it will be described that, according to the technique of the first embodiment of the present invention, low power consumption, which is one of the problems of the prior art, is achieved, and further, random horizontal line noise can be reduced.

(About low power consumption)
With the configuration of the first embodiment of the present invention, the reference bias current Ibias can be made to flow to the amplification transistor of the pixel in accordance with the mirror ratio accurately, so that the minimum value of variation is taken into consideration as in the conventional circuit. It is not necessary to flow an excessive current in the setting, and low power consumption can be realized. Furthermore, in order to make the current Ibias of the current source 251 less susceptible to the influence of the power supply voltage fluctuation and the temperature fluctuation, the current accuracy is further improved by creating it from a constant voltage circuit / constant current circuit called a band gap reference circuit (BGR). Can be increased.

  As a result, conventionally, it has been necessary to flow an excessive current many times at the typ setting in consideration of the minimum value of variation with respect to the required bias currents Ibias1 to Ibiasm. Since it is not affected by fluctuations and temperature fluctuations, it is not necessary to pass an excessive current.

  For this reason, the prior art is a problem with respect to the deterioration of heat dissipation due to the recent downsizing of the camera set, and this low power consumption technique is optimal for downsizing.

(About random horizontal noise)
Further, during the CDS period from the first read period for reading the reset component to the second read period for reading the data component (= reset component + signal component), the gate terminals of the load transistors ML1 to MLm The voltage difference between the source terminal and the source terminal is held at a constant value, and the DC component of noise is canceled by the CDS circuit, and random horizontal noise is not generated. Here, the first read period includes a reset operation by the reset transistor M2, and the second read period includes a transfer operation by the transfer transistor M1. The CDS period is an example of a bias hold period.

  The specific explanation is as follows. First, before the pixel signal is output from the amplification transistor M3 to the column signal lines VL1 to VLm (time t10 in FIG. 2), the voltage of the reference bias VbiasL is sampled by the capacitive element C1 by the switch element SW1. At this time, the noise component superimposed on the reference bias VbiasL is superimposed on the capacitive element C1 as a DC component, and the CDS period (Tcds in FIG. 2) continues to be held.

  Within this CDS period, the reset component V1 and the data component V2 (= reset component + signal component) of the pixel signals of the column signal lines VL1 to VLm are read out to the CDS circuit, and only the signal component is detected. As a result, the noise DC component contained in both the reset component and the data component is completely canceled by the CDS circuit, and the noise removal effect can be enhanced.

(About high-intensity streaking)
Further, when high luminance is incident, the voltage effect of the GND line varies due to the short channel effect of the load transistors ML1 to MLm, but the voltage difference between the gate terminal and the source terminal of each load transistor ML1 to MLm is constant. Therefore, high-intensity streaking does not occur as in the conventional example.

  As described above, in the solid-state imaging device according to Embodiment 1 of the present invention, the sample-and-hold circuit 250 is newly provided between the gate terminal of the primary side mirror transistor MF of the current source and the gate terminals of the load transistors ML1 to MLm. It is characterized by providing. As a result, it is possible to reduce power consumption, take measures against random horizontal noise, and take measures against high luminance streaking.

(Noise reduction effect by CDS method)
As for circuit noise, device noise such as thermal noise of white noise and 1 / f noise having frequency dependency is generated from each device such as each transistor element and resistor element. As a measure against white noise, since it is determined by the product of the noise density and the signal pass band, means for narrowing the signal pass band can be considered. On the other hand, as countermeasures against 1 / f noise, a means for increasing the size of a transistor in the circuit or a method for reducing the sampling frequency of the CDS can be considered.

  First, the current Ibias of the current source 251 is generally created from a constant voltage circuit / constant current circuit called a band gap reference circuit (BGR) in order to make it less susceptible to power supply voltage fluctuations and temperature fluctuations. . For this reason, device noise is generated from each transistor element and resistor element.

  Furthermore, the distance from the band gap reference circuit (BGR) to the primary side mirror transistor MF of the current source is often separated in terms of layout, and the wiring through which this Ibias flows and the wiring of other digital signals run side by side or cross. If so, these digital noises are superimposed on Ibias.

  Further, device noise such as thermal noise and 1 / f noise of the device of the primary side mirror transistor MF of the current source is also added.

  As a result, the current noise superimposed on the current Ibias of the primary mirror transistor MF of the current source and the device noise of the primary mirror transistor MF of the current source are converted into the gate voltage VbiasL of the primary mirror transistor MF of the current source. Is done.

  Next, without the sample and hold circuit 250 of the present invention, the voltage noise superimposed on the gate voltages of the load transistors ML1 to MLm is converted into current noise superimposed on the currents Ibias1 to Ibias2, and finally Then, it is converted into voltage noise by the amplification transistor M3 in the selected row and is superimposed on the output voltage from the output terminals Vout1 to Voutm of the column signal lines VL1 to VLm.

  Next, the CDS circuit calculates the signal components of the unit pixels P11 to Pnm using the voltage difference between the previously stored reset component V1 and the later stored data component V2 (= reset component + signal component). .

  For this reason, with respect to 1 / f noise having a frequency lower than the frequency of CDS (the time difference for reading the reset component V1 and the data component V2), the reset component V1 and the data component V2 stored later (= reset component + signal component) ) Is zero, and can be removed by CDS. However, a noise component having a high frequency cannot be removed by CDS, and conversely, thermal noise is deteriorated by √2 times, and noise is superimposed on all columns. As a result, it becomes easy to visually see as random horizontal line noise.

  On the other hand, in the first embodiment of the present invention, a sample hold circuit 250 is added. At this time, the noise superimposed on the reference bias voltage VbiasL of the gate voltage of the primary side mirror transistor MF of the constant current circuit 252 includes a DC to AC component, but at the moment when SW1 is turned off and sampled. Then, it is superimposed as a DC component on the capacitive element C1, and the CDS period continues to be held.

  That is, during the CDS period, since the voltage between the gate terminal and the source terminal of the load transistors ML1 to MLm is a constant value, the bias currents Ibias1 to Ibiasm are constant values. As a result, even if the noise DC component is superimposed on the capacitive element C1, the CDS circuit calculates the voltage difference between the reset component V1 and the data component V2 (= reset component + signal component). Canceled completely.

(Explanation of timing chart)
In the embodiment of the present invention, each signal is controlled by the timing chart shown in FIG.

  First, reset control signals TRES1 to n, transfer control signals TTX1 to n and select control signals TSEL1 to n, which are output signals of the timing generator 1, are supplied to the reset transistor M2, the transfer transistor M1, and the selection transistor M4 by the row scanning circuit 2, respectively. The voltage is converted to an optimum voltage for driving. Next, the reset control signals VRES1 to n, transfer control signals VTX1 to n, and select control signals VSEL1 to n are read out sequentially to the column signal lines VL1 to VLm for each row while performing vertical scanning.

  In addition, a sample hold selection signal SH1 output from the timing generator 1 is newly provided. Here, since the timing generator 1 is often integrated into one chip with the solid-state imaging device in recent years, the addition and control of the sample hold selection signal SH1 can be easily realized.

  To describe this operation, first, at time t10, the select control signal VSEL1 becomes High level, and the selection transistor M4 of the unit pixels P11 to P1m is turned on to select the first row.

  The sample hold selection signal SH1 outputs a low level from the timing generator 1 at time t10, the switch element SW1 constituting the sample hold circuit 250 is turned off, and the voltage of the reference bias voltage VbiasL at this moment is stored in the capacitor. Sampling to element C1.

  Here, the select control signal VSEL1 and the sample hold selection signal SH1 may or may not be synchronized, but the circuit configuration of the timing generator 1 can reduce the number of circuit elements if they are synchronized. preferable.

  Next, in a state where the transfer control signal VTX1 is Low level and the transfer transistor M1 is turned off, at time t11, the reset control signal VRES1 becomes High level to turn on the reset transistor M2, and the floating diffusion nodes of the unit pixels P11 to P1m are turned on. Reset the voltage of FD1.

  Next, in a state where the voltage of the floating diffusion node FD1 is reset, at time t12, the reset control signal VRES1 becomes a low level, and the reset transistor M2 is turned off.

  Next, the voltage of the floating diffusion node FD1 of each of the unit pixels P11 to P1m is amplified by the amplification transistor M3, and is output from the output terminals Vou1 to Voutm via the column signal lines VL1 to VLm during the period from time t12 to time t13. It is read by the CDS circuit and stored as the reset component V1.

  After a while, at time t13, the transfer control signal VTX1 becomes a high level to turn on the transfer transistor M1, and all the photocharges accumulated in the photo detection unit D1 are transmitted to the floating diffusion node FD1. Thereafter, at time t14, the transfer control signal VTX1 becomes Low level, and the transfer transistor M1 is turned off.

  Then, the voltage of the floating diffusion node FD1 is amplified by the amplification transistor M3, and is read from the output terminals Vou1 to Voutm to the CDS circuit via the column signal lines VL1 to VLm during the period from the time t14 to the time t15. Stored as component V2 (= reset component + signal component). Thereafter, after sufficiently stabilizing (time t15), the sample hold selection signal SH1 again becomes a high level, and the voltage of the reference bias voltage VbiasL starts to be charged in the capacitive element C1.

  Next, the CDS circuit uses the voltage difference between the previously stored reset component V1 and the later stored data component V2 (= reset component + signal component) to generate a pure signal output from each pixel P11 to P1m. A signal component for light is calculated. The reset component V1 and the data component V2 include the DC component of the noise at the moment when the reference bias voltage VbiasL is sampled, but are completely canceled and the random horizontal noise becomes zero.

  Next, when the second row is selected, the signals of the second row are read out as output terminals Vout1 to Voutm via the column signal lines VL1 to VLm. The same applies to the third and subsequent lines.

(Summary)
As described above, in the solid-state imaging device according to Embodiment 1 of the present invention, a sample is newly added between the gate terminal of the primary-side mirror transistor MF of the current source and the gate terminals of the load transistors ML1 to MLm. A hold circuit 250 is inserted. The switch element SW1 constituting the sample and hold circuit 250 includes the reference bias voltage VbiasL generated in the primary side mirror transistor MF of the current source that generates the reference bias current of the current mirror, at the instant of time t10, including noise. It functions as a DC component, which is sampled in the capacitive element C1 and held during the CDS period (Tcds).

  With the above configuration, the reference bias current Ibias can be accurately supplied to the pixel according to the mirror ratio. For this reason, it is not necessary to flow an excessive current at the typ setting in consideration of the minimum variation, and low power consumption can be realized.

  Further, during the CDS period, the voltage difference between the gate terminal and the source terminal of each of the load transistors ML1 to MLm is kept constant, so that the random horizontal noise described above does not occur. Similarly, high luminance streaking does not occur.

  Note that although the CDS period in which the bias voltage is held in the capacitor C1 is described as 1H (one horizontal scanning period), it may be 1V (one vertical scanning period).

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIG.

  First, the device configuration of the imaging device and the solid-state imaging device according to the second embodiment of the present invention is based on the imaging device and the solid-state imaging device according to the first embodiment of the present invention shown in FIG.

  The timing chart according to the second embodiment of the present invention is the same as the timing chart according to the first embodiment of the present invention shown in FIG.

  In the solid-state imaging device according to the second embodiment of the present invention, a cascode circuit 263 is added to the imaging device according to the first embodiment.

  The cascode circuit 263 includes cascode transistors MC1 to MCm connected to the column signal lines VL1 to VLm, and a bias circuit VBIAS that supplies the bias voltage VbiasC. The cascode transistors MC1 to MCm are provided for each column, and are connected between the load transistors ML1 to MLm and the output terminals Vout1 to Voutm.

  First, as described above, the amplification transistor M3 of the pixel in the selected row has a source follower structure with the load transistors ML1 to MLm constituting the constant current circuit 252, and each output terminal of the column signal lines VL1 to VLm. The voltages Vout1 to Voutm are determined by the voltage of the node FD1 of the selected row and the currents Ibias1 to Ibiasm flowing through the load transistors ML1 to MLm.

  That is, the voltages of the output terminals Vout1 to Voutm are determined according to the brightness of ambient light. For example, a photo detector that receives bright light generates a low voltage, while a photo detector that receives dark light generates a relatively high voltage.

  What is concerned about the first embodiment is that the problem of deterioration of the linearity of the output voltage of the amplification transistor M3 with respect to the luminance level detected by the photo detector D1, which is one of the problems of the prior art, is not solved. Now, it will be described that this problem is solved in the second embodiment. In the following description, x represents a column number and x = 1 to m.

  First, in FIG. 1, the capacitive element between the gate terminal and the source terminal of the load transistor MLx is C1. Further, a parasitic capacitance between the column signal line VLx connected to the drain terminal of the load transistor MLx and the gate terminal of the load transistor MLx is Cgd1.

  At this time, the voltage fluctuation amount ΔVoutx at the output terminal Voutx is equal to the drain voltage fluctuation amount ΔVd1x of the load transistor MLx, and the gate voltage fluctuation amount ΔVg1x can be calculated by capacitance division according to (Equation 1).

  ΔVg1x = ΔVd1x · Cgd1 / (Cgd1 + C1) (Formula 1)

  At this time, the bias current Ibiasx can be expressed by (Expression 2) when the mutual conductance of the load transistor MLx is Gml, and is collectively expressed by (Expression 3). If Gml increases, ΔVg1x may affect current Ibiasx.

  That is, the change ΔIbiasx in the bias current value when the reset component V1 is read from the output terminal Voutx of the column signal line VLx and when the data component V2 (= reset component + signal component) is read can be expressed by (Expression 3). it can.

  ΔIbiasx = ΔVg1x · Gml (Formula 2)

ΔIbiasx = ΔVg1x · Gml
= (ΔVd1x · Cgd1 / (Cgd1 + C1)) · Gml (Formula 3)

  Therefore, when the mutual conductance Gml of the load transistor MLx is large, or when the parasitic capacitance Cgd1 is large as the layout configuration, or when the capacitive element C1 is small, the output of the amplification transistor M3 with respect to the luminance level detected by the photodetection unit D1 The problem of voltage linearity degradation occurs.

  In particular, since the parasitic capacitance Cgd1 is not managed in the diffusion process, the parasitic capacitance Cgd1 has a relative variation for each column, and the linearity is different for each column.

  For this reason, the second embodiment solves the above-described problem, and newly provides cascode transistors MC1 to MCm for each column and connects them between the load transistors ML1 to MLm and the output terminals Vout1 to Voutm. Yes.

  In this cascode configuration, when the reset component V1 and the data component V2 (= reset component + signal component) are read, even if there are voltage fluctuations at the output terminals Vout1 to Voutm, fluctuations in the drain voltages of the load transistors ML1 to MLm. The quantities ΔVd1 to ΔVdm become zero. Therefore, from (Equation 3), ΔIbiasx becomes zero, and the problems of linearity degradation and relative variation in linearity for each column can be solved.

(Summary)
As described above, in the cascode circuit 263, the cascode transistors MC1 to MCm are provided for each column and are connected between the load transistors ML1 to MLm and the output terminals Vout1 to Voutm. As a result, it is possible to reduce the power consumption, and to solve the problems of the degradation of the linearity of the output voltage of the amplification transistor M3 with respect to the luminance level detected by the photo detector D1 and the relative variation of the linearity of each column.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIG.

  First, the device configuration of the imaging device and the solid-state imaging device according to the third embodiment of the present invention is based on the imaging device and the solid-state imaging device according to the first embodiment of the present invention shown in FIG.

  The timing chart according to the third embodiment of the present invention is the same as the timing chart according to the first embodiment of the present invention shown in FIG.

  In the solid-state imaging device according to the third embodiment of the present invention, a cascode circuit 262 having a sample hold circuit 260 is added to the imaging device according to the first embodiment.

  The cascode circuit 262 includes cascode transistors MC1 to MC2 connected to the column signal lines VL1 to VLm, and a bias circuit VBIAS that supplies the bias voltage VbiasC. The cascode transistors MC1 to MCm are provided for each column, and are connected between the load transistors ML1 to MLm and the output terminals Vout1 to Voutm.

  Here, in the cascode circuit 262, a sample hold circuit 260 is inserted between the bias circuit VBIAS that supplies the cascode bias voltage VbiasC and the gate terminals of the load transistors MC1 to MC2. The switch element SW2 constituting the sample hold circuit 260 serves to sample and hold the bias voltage VbiasC in the capacitive element C2.

  At this time, if the capacitive elements C1 and C2 are MOS type capacitors, the drain ends and the source ends of the capacitive elements C1 and C2 are covered with a metal wiring layer to be shielded from light, and unnecessary charges generated at these PN junctions It is necessary to suppress.

  If the capacitive elements C1 and C2 are MIM type capacitors, the metal wiring layer constituting one of the two electrodes of each of the capacitive elements C1 and C2 has a GND potential, and each load transistor ML1 to MLm It may be connected to the source terminal of According to this configuration, since the diffusion layer is not used and the wiring layer can be used, an increase in chip size can be suppressed.

  What is concerned about the second embodiment is that the random horizontal noise is slightly deteriorated depending on the transistor size, and this problem will be explained in the third embodiment. In the following description, x represents a column number and x = 1 to m.

  First, in FIG. 3, the resistance between the drain and source of the load transistors ML1 to MLm is R1. The source output resistances of the cascode transistors MC1 to MCm are Rc (= 1 / Gmc). Gmc is the mutual conductance of the cascode transistors MC1 to MCm. Further, the source output resistance of the amplifying transistor M3 of the pixel is assumed to be Ra (= 1 / Gma). Gma is the mutual conductance of the amplification transistor M3 of the pixel. Further, a noise component superimposed on the bias voltage VbiasC of the cascode transistors MC1 to MCm is assumed to be ΔVbiasC.

  At this time, the voltage noise ΔVoutx generated at the source output terminal Voutx of the amplification transistor M3 can be calculated by (Equation 4).

  ΔVOUTx = ΔVbiasC · Ra / (Rc + Rl) (Formula 4)

  As described above, if the bias voltages VbiasC of the cascode transistors MC1 to MCm are connected to all the columns, noise components are generated at the same time in common to all the columns. There is sex. This is because, as described above, the CDS circuit can remove the low frequency component from the noise component but cannot remove the high frequency component.

  As a third embodiment, the above problem is solved, and a bias circuit VBIAS that newly supplies a bias voltage VbiasC of the cascode transistors MC1 to MCm and a gate terminal of each of the cascode transistors MC1 to MCm, A sample hold circuit 260 is provided.

  As a result, the random horizontal noise can be removed in the same manner as the sample hold circuit 250 with the load transistors ML1 to MLm in the first embodiment.

  This is because during the CDS period, the gate terminals of the cascode transistors MC1 to MCm are not connected and are independent, so that the noise at the moment (time t10) when the bias voltage VbiasC is sampled becomes a DC component and is held in the capacitive element C2. This is because it is canceled by the CDS circuit.

  Furthermore, in this case, it is necessary to examine the influence on the linearity of the output voltage of the amplification transistor M3 with respect to the luminance level detected by the photo detection unit D1 taken as a countermeasure in the second embodiment, which will be described.

  First, in FIG. 4, the capacitive element between the gate terminals of the cascode transistors MC1 to MCm and the source terminals of the load transistors ML1 to MLm is C2. Next, the parasitic capacitance Cgd2 between the column signal lines VL1 to VLm connected to the drains of the cascode transistors MC1 to MCm and the gates of the cascode transistors MC1 to MCm is set.

  At this time, the voltage fluctuation amount ΔVoutx of the output terminal Voutx is equal to the drain voltage fluctuation amount ΔVd2x of the cascode transistor MCx, and the gate voltage fluctuation amount ΔVg2x can be calculated by (Equation 5) by capacitance division.

  ΔVg2x = ΔVd2x · Cgd2 / (Cgd2 + C2) (Formula 5)

  At this time, the amount of fluctuation of the gate voltage of the cascode transistor MCx becomes equal to the amount of fluctuation of the drain voltage of the load transistor MLx, and therefore, the amount of fluctuation ΔVd1x of the drain voltage of the load transistor MLx can be expressed by (Equation 6). .

ΔVd1x = ΔVg2x
= ΔVd2x · Cgd2 / (Cgd2 + C2) (Formula 6)

  At this time, the fluctuation amount ΔIbias of the bias current with respect to the luminance level can be calculated by (Expression 7) using (Expression 3) and (Expression 6).

ΔIbiasx = ΔVg1x · Gml
= (ΔVd1x · Cgd1 / (Cgd1 + C1)) · Gml
= ΔVd2x · (Cgd2 / (Cgd2 + C2)) ·
(Cgd1 / (Cgd1 + C1)) · Gml (Formula 7)

  At this time, from (Equation 7), the product of the capacity division value (Cgd2 / (Cgd2 + C2)) and (Cgd1 / (Cgd1 + C1)) becomes very small, and ΔIbiasx becomes almost zero. As a result, the problem of degradation of the linearity of the output voltage of the amplification transistor M3 with respect to the luminance level detected by the photo detection unit D1 can be solved.

(Summary)
As described above, in the cascode circuit 262, the sample hold circuit 260 is inserted between the bias circuit VBIAS that supplies the cascode bias voltage VbiasC and the gate terminals of the load transistors MC1 to MCm. As a result, low power consumption is achieved, linearity deterioration of the output voltage of the amplification transistor M3 with respect to the luminance level detected by the photo detector D1, improvement in relative variation in linearity for each column, random horizontal noise, The problem of high brightness streaking can be solved.

(Replenishment)
The present invention can be applied to all solid-state imaging devices including a readout circuit, such as a CMOS solid-state imaging device.

  Note that the individual imaging device of the above embodiment can be modified as follows, for example, within the scope of the present invention. In the embodiment, there is one FD, one reset transistor, one transfer transistor, one amplification transistor, and one selection transistor for each PD. Etc. may be shared.

  In addition, the CDS circuit detects the reset component and the data component of the digital signal by the AD conversion means even if the analog CDS method detects the reset component and the data component of the analog signal by the correlated double detection. It may be a digital CDS system.

  Further, the CDS period held in the capacitive elements C1 and C2 has been described as 1H (one horizontal scanning period), but may be 1V (one vertical scanning period).

  Capacitance elements C1 and C2 may use parasitic capacitances between the gate terminals and back gate terminals of transistors ML1 to MLm and MC1 to MCm, respectively.

  The capacitive elements C1 and C2 may be MOS type capacitive elements, MIM type capacitive elements, or parasitic capacitive elements between wirings.

  In addition, the present invention is not limited to the front-illuminated type, and as shown in FIG. 5, the photodetecting portion BD1 is formed on the substrate surface side, and the back surface where the light incident from the optical lens is received on the substrate surface side. An irradiation type solid-state imaging device may be used.

  All the individual imaging devices according to such modifications are included in the present invention.

  Furthermore, the solid-state imaging device according to the present invention is not limited to the above embodiment. Other embodiments realized by combining arbitrary constituent elements in the above-described embodiments, various modifications that can be conceived by those skilled in the art without departing from the gist of the present invention, Various devices incorporating the solid-state imaging device according to the present invention are also included in the present invention. For example, a camera incorporating the solid-state imaging device according to the present invention is also included in the present invention.

  As described above, the present invention can improve the horizontal line noise with a simple configuration having a very small number of elements, such as a CMOS solid-state imaging device, a digital still camera, a movie camera, and a camera-equipped mobile phone. It can be applied to surveillance cameras.

1 Timing Generator 2 Row Scan Circuit 200 Pixel Array 240 Sample Hold Circuit 242 Constant Current Circuit 250 Sample Hold Circuit 252 Constant Current Circuit 260 Sample Hold Circuit 262 Cascode Circuit 263 Cascode Circuits VL1 to VLm Column Signal Lines P11 to Pnm Unit Pixel D1 Photo Detection Part BD1 Photodetection part FD1 on the substrate surface side Floating diffusion node M1 Transfer transistor M2 Reset transistor M3 Amplification transistor M4 Selection transistor MF Current source primary side mirror transistors ML1 to MLm Load transistors MC1 to MCm Cascode transistors SW1 and SW2 Switch element C1 , C2 capacitive elements VRES1 to VRESn reset control signals VSEL1 to VSELn select control signals VTX1 to VTXn Nsufa control signal TRES1~TRESn reset control signal TSEL1~TSELn select control signal TTX1~TTXn transfer control signal SH1 sample hold selection signal VBIAS bias circuit

Claims (9)

A solid-state imaging device that reads a pixel signal from a unit pixel that has a plurality of unit pixels arranged in a matrix and is selected in units of rows,
An amplification transistor that is included in each of the plurality of unit pixels and outputs a pixel signal;
A column signal line from which the amplified signal is read; and
A first transistor provided for each column and supplying a bias current to an amplification transistor belonging to a selected row;
A second transistor that has a drain terminal and a gate terminal short-circuited and generates a first reference bias voltage at the gate terminal by a constant reference bias current supplied between the source terminal and the drain terminal;
To mirror the bias current with respect to the reference bias current by transmitting the first reference bias voltage from the gate terminal of the second transistor to the gate terminal of each first transistor. A first bias signal line of
A solid-state imaging device comprising: a first sample-and-hold circuit inserted in the first bias signal line between the gate terminal of the second transistor and the gate terminal of each first transistor. The first sample and hold circuit includes:
A first switch element inserted in the first bias signal line between the gate terminal of the second transistor and the gate terminal of each first transistor;
The solid-state imaging device according to claim 1, further comprising: a first capacitive element connected to the gate terminal and the source terminal of the first transistor. Each of the unit pixels is
A photodiode that converts light into signal charge;
A floating diffusion layer for holding signal charges;
A reset transistor for resetting the signal charge of the floating diffusion layer;
A transfer transistor for transferring signal charges from the photodiode to the floating diffusion layer;
The amplification transistor that outputs the pixel signal according to the signal charge held in the floating diffusion layer, and
The first switch element is off during a bias hold period from a first readout period including a reset operation by the reset transistor to a second readout period including a transfer operation by the transfer transistor,
The solid-state imaging device according to claim 2, which is turned on when the bias hold period is completed. A third transistor provided for each column and configured to make a voltage at a drain terminal of the first transistor supplying a bias current to the amplification transistor belonging to a selected row constant;
A source terminal of the third transistor is connected to a drain terminal of the first transistor, a drain terminal of the third transistor is connected to the column signal line, and a gate terminal of the third transistor is a second terminal. The solid-state imaging device according to claim 1, wherein the second reference bias voltage is applied from a bias circuit connected via a bias signal line. The solid-state imaging device according to claim 4, further comprising: a second sample hold circuit inserted in the second bias signal line between the bias circuit and the gate terminal of each of the third transistors. The second sample and hold circuit includes:
A second switch element inserted in the second bias signal line between the bias circuit and the gate terminal of each third transistor;
The solid-state imaging device according to claim 5, further comprising: a second capacitor element connected to the gate terminal of the third transistor and a source terminal on the first transistor side. The second switch element is off during a bias hold period from a first read period including a reset operation by the reset transistor to a second read period including a transfer operation by the transfer transistor,
The solid-state imaging device according to claim 6, which is turned on when the bias hold period is completed. The first capacitor element and the second capacitor element are MOS type capacitors,
A first metal wiring layer is provided above the first drain end and the first source end of the first capacitive element,
The first capacitor wiring layer includes the first metal wiring layer above the second drain end and the second source end,
The first drain end, the first source end, the second drain end, and the second source end are shielded from light by the first metal wiring layer. The solid-state imaging device described. The first capacitor element and the second capacitor element are MIM type capacitors,
The second metal wiring layer constituting one electrode of the first capacitor element has a GND potential, and the second metal wiring layer constituting one electrode of the second capacitor element has a GND potential. The solid-state imaging device according to claim 2 or 6.

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