WO2022262111A1

WO2022262111A1 - Circuit for eliminating fixed pattern noise, and image sensor

Info

Publication number: WO2022262111A1
Application number: PCT/CN2021/113956
Authority: WO
Inventors: 王凯; 刘笑霖; 苏奎任; 齐一泓; 李前
Original assignee: 中山大学
Priority date: 2021-06-17
Filing date: 2021-08-23
Publication date: 2022-12-22
Also published as: CN113271420A

Abstract

Provided in the present application is a circuit for eliminating fixed pattern noise. The circuit comprises: bright pixels, which are used for sensing incident light and outputting an analog image signal voltage; dark pixels, an output voltage from which serves as a reference voltage of a variable gain differential amplification circuit; the variable gain differential amplification circuit, which performs differential comparison on the reference voltage output from the dark pixels and the signal voltage output from the bright pixels, so as to realize the removal of noise in a pixel array of an image sensor and the reading of an intensity signal of incident light sensed by the bright pixels; and a switch circuit, which is connected to the dark pixels, the bright pixels and the variable gain differential amplification circuit, and is used for controlling the connection or disconnection of the circuit. In the present application, differentiation is performed on the voltage of randomly read dark pixels under a dark condition and a signal voltage of bright pixels, and a variable gain differential amplification circuit is designed, such that fixed pattern noise is eliminated or reduced to the maximum extent; moreover, the magnitude of the light intensity is read. Further provided in the present application is an image sensor including the circuit.

Description

A circuit and image sensor for eliminating fixed pattern noise

technical field

The invention relates to the technical field of image sensor signal processing, in particular to a circuit for eliminating fixed pattern noise and an image sensor.

Background technique

The structure of a complementary metal oxide semiconductor (CMOS) image sensor (CIS) generally consists of a pixel array, a correlated double sampling circuit (Correlated Double Sampling, CDS), an amplifier (Amplifier, AMP), an analog-to-digital converter (Analog-to-Digital Converter) , ADC), timing control logic, signal processing unit and external interface unit, as shown in Figure 1. Wherein, the pixel array is composed of m×n pixels arranged in an array, and the pixel circuits of the existing CIS mainly include passive pixels, active pixels or random read active pixel circuits. A typical passive pixel circuit is usually composed of a MOS tube and a photodiode; a typical active pixel circuit is mainly composed of a photodiode, a reset MOS tube, a source follower MOS tube and a selection switch MOS tube; a random read active The pixel circuit is mainly composed of a photodiode, a MOS amplifier tube, and a switch MOS tube.

In the design of the CMOS image sensor readout circuit, to suppress and eliminate the noise of the image sensor and improve the signal-to-noise ratio is a problem that needs to be considered in the circuit design of the image sensor. The noise of the image sensor mainly includes the inherent noise of the device itself and some additional noise introduced by the process flow, circuit structure and working mode. Generally speaking, the former introduces thermal noise and flicker noise, while the latter manifests as KTC noise and fixed pattern noise (Fixed Pattern Noise, FPN).

Traditional image sensor pixel circuits usually use correlated double sampling technology to suppress low-frequency noise, because the charge on the capacitor cannot change abruptly, that is to say, the noise and voltage from the same circuit are correlated in time, and the signal voltage and The reset voltage is sampled twice, and the difference between the two sampled values is used as the value of the output signal, so that noise can be removed. However, there are also some problems in the correlated double sampling technology: the use of capacitors and a large number of transistors will occupy a large area, and will also introduce additional noise; For random read image sensors, such as the commonly mentioned image sensors using logarithmic pixel circuits, the device connection method inside the pixel circuit of this type of image sensor requires redesign of the back-end signal readout and processing circuits. Correlated double sampling cannot be achieved to remove the effect of fixed pattern noise. In addition, for an image sensor with a global electronic shutter function, it is also difficult to implement correlated double sampling and remove fixed pattern noise.

Contents of the invention

Based on this, in order to remove the fixed pattern noise in the above situation and read the light intensity signal, the present invention provides a circuit for eliminating the fixed pattern noise.

The present invention adopts the following technical solutions to solve the existing problems of the prior art:

A circuit for eliminating fixed pattern noise, comprising:

A bright pixel, which is any pixel in the image sensor pixel array, is used to sense incident light and output an analog image signal voltage;

The dark pixel has the same size, structure and pixel circuit as the bright pixel, and its output voltage is used as the reference voltage of the variable gain differential amplifier circuit;

A variable gain differential amplifier circuit, which is respectively connected to the bright pixel and the dark pixel, and compares the reference voltage output by the dark pixel and the signal voltage output by the bright pixel to realize the removal of noise in the pixel array of the image sensor and the bright pixel Reading of the sensed incident light intensity signal;

The switch circuit is respectively connected between the dark pixel and the variable gain differential amplifier circuit and between the bright pixel and the variable gain differential amplifier circuit, and is used to control the connection or disconnection of the circuit.

Further, the variable gain differential amplifier circuit includes a sampling capacitor, a second capacitor, and an operational amplifier, and the switch circuit includes a switch S ₁ , a switch S ₂ , a switch S ₃ , a switch S ₄ , and is used to generate a switching circuit sequence to Control the two-phase non-overlapping clock signal generator of each switch; The two ends of the second capacitor are respectively connected to the reverse input terminal and the positive output terminal of the operational amplifier, and are connected to the sampling capacitor through the switch S2 _; There are two switches S1, wherein the _first switch S1 is connected between the bright pixel and the sampling capacitor, and the second switch S1 is connected between the dark pixel and the positive input terminal of the operational amplifier _; _one end _of the switch S3 is connected to Between the _first switch S1 and the sampling capacitor, the other end is connected between the _second switch S1 and the positive input of the operational amplifier _; _one end of the switch S4 is connected between the switch S2 and the sampling capacitor, and the other end is connected between the switch S2 and the sampling capacitor. One end is connected between the second switch S1 and the positive input end of the operational amplifier. The sampling capacitor is composed of a first capacitor and a third capacitor connected in parallel.

Further, the variable gain differential amplifier circuit includes a first resistor, a variable resistor, and an operational amplifier; the switch circuit includes a switch _S0 and a dual-phase non-interconnecting circuit for generating the timing sequence of the switch circuit to control the switch _S0 Stacked clock signal generator; the switch _S0 is two, wherein the first switch _S0 is connected in series with the first resistor between the bright pixel and the inverting input terminal of the operational amplifier, and the second switch _S0 is connected in series Between the dark pixel and the positive input of the operational amplifier; one end of the variable resistor is connected in series with the first resistor and connected to the negative input of the operational amplifier, and the other end of the variable resistor is connected to the positive input of the operational amplifier. Connect to the output. The variable resistor is composed of a second resistor connected in series with a third resistor.

Another object of the present invention is to provide an image sensor provided with the above-mentioned circuit for eliminating fixed pattern noise.

The circuit of the present invention can be applied to the existing CIS pixel structure, including passive pixel, active pixel or random read active pixel circuit. The passive pixel is generally composed of a MOS transistor and a photodiode. The active pixel is mainly composed of a photodiode, a reset MOS transistor, a source follower MOS transistor and a selection switch MOS transistor.

Further, the random read active pixel circuit structure includes a photodiode, a MOS amplifier tube and a switch MOS tube; the cathode of the photodiode is controlled by a reset signal, and its anode is connected to the substrate of the MOS amplifier tube; the MOS amplifier tube The source is connected to the drain of the switching MOS transistor, and the gate thereof is controlled by a bias voltage; the source of the switching MOS transistor is connected to a constant current source to convert the output current of the bright pixel or the dark pixel into an output voltage. The constant current source clamps the change of the current magnitude, and converts the current change of bright and dark pixels into the change of the output terminal voltage.

Since the size, structure and pixel circuit of the dark pixel are the same as those of the bright pixel, the signal voltage of the randomly read bright pixel under the light condition and the output voltage of the randomly read dark pixel under the dark condition are passed through a variable gain differential amplifier circuit By making a difference, the fixed pattern noise can be eliminated or greatly reduced, and the voltage signal of the current light intensity change can be output at the same time.

Compared with prior art, the beneficial effect of the present invention is:

The present invention introduces the difference between the randomly read bright pixel voltage under light conditions and the randomly read dark pixel voltage under dark conditions, and eliminates or minimizes the fixed pattern noise through the design of a variable gain differential amplifier circuit, and reads light strong size. At the same time, by changing the value of the capacitor or the value of the resistor, the gain of the operational amplifier can be changed.

Description of drawings

FIG. 1 is a schematic structural diagram of an existing image sensor;

Fig. 2 is a structural schematic diagram of the image sensor of the present invention

Fig. 3 shows the block diagram of the circuit principle of the present invention working in the switched capacitor variable gain amplification mode;

Fig. 4 shows the block diagram of the circuit principle of the present invention working under the variable gain amplification mode of the resistor network;

Fig. 5 shows the circuit diagram of Embodiment 1 of the present invention;

Fig. 6 shows the circuit diagram of Embodiment 2 of the present invention;

Fig. 7 shows the circuit diagram of Embodiment 3 of the present invention;

FIG. 8 shows a timing diagram of a switching circuit generated by the dual-phase non-overlapping clock signal generator of the present invention.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings, but this does not limit the protection scope of the present invention. Based on the description of the embodiments of the present application, other embodiments obtained by persons of ordinary skill in the art without making creative efforts all belong to the protection scope of the present invention. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated.

Please refer to FIG. 2 , which shows a schematic structural diagram of the image sensor described in this application.

The image sensor of the present invention includes a bright pixel 02, a dark pixel 01, a variable gain differential amplifier circuit and a switch circuit. The bright pixel 02 is any pixel in the pixel array of the image sensor, which is used to sense incident light and output an analog image signal voltage. The dark pixel 01 is a pixel set in the bright pixel 02 array under non-illumination conditions. Its size, structure and pixel circuit are exactly the same as the bright pixel 02. The output voltage of the dark pixel 01 is used as the reference voltage of the variable gain differential amplifier circuit.

The variable gain differential amplifier circuit is respectively connected to the bright pixel 02 and the dark pixel 01, and is used for differential comparison between the reference voltage output by the dark pixel 01 and the signal voltage output by the bright pixel 02, thereby realizing the removal of noise in the pixel array of the image sensor And read out the incident light intensity signal sensed by the bright pixel 02;

The switch circuit is connected between the dark pixel 01 and the variable gain differential amplifier circuit, and between the bright pixel 02 and the variable gain differential amplifier circuit, and is used to control the connection or disconnection of the circuit.

The structure of the bright pixel 02 in the present invention can be any pixel structure of the existing complementary metal oxide semiconductor (CMOS) image sensor (CIS), including passive pixels, active pixels or random read active pixel circuits , also including any known pixel structure not listed in this embodiment. The passive pixel is generally composed of a MOS transistor and a photodiode. The active pixel is mainly composed of a photodiode, a reset MOS transistor, a source follower MOS transistor and a selection switch MOS transistor. The structure of the random read active pixel circuit is mainly composed of a photodiode, a MOS amplifier tube, and a switch MOS tube. Similarly, the structure of the dark pixel 01 is consistent with the bright pixel 02 listed above. With reference to Fig. 3 and Fig. 4, wherein Fig. 3 has shown the circuit principle block diagram that the present invention works under the switched capacitor variable gain amplification mode, and Fig. 4 shows the circuit principle that the present invention works under the resistance network variable gain amplification mode block diagram.

The working mode of the variable gain differential amplifier circuit described in this embodiment includes a switched capacitor variable gain amplification mode and a resistor network variable gain amplification mode; the switched capacitor variable gain amplification mode is mainly realized by a switched capacitor variable gain amplifier circuit , the resistor network variable gain amplification mode is mainly realized by a resistor network variable gain amplifier circuit. The image sensor of the present invention can adopt any one of the above-mentioned two working modes, and can also include the above-mentioned two working modes at the same time. For the specific circuit structure of the two working modes, please refer to the following embodiments 1-3. Embodiments 1-3 will describe the structure of a random read active pixel circuit as a bright and dark pixel, but the pixel structure of the present invention is not limited to For the structures described in Embodiments 1 to 3, using any existing pixel structure to replace the random read active pixel circuit structure described in this embodiment also falls within the protection scope of the present invention.

Example 1

Referring to FIG. 5 , this embodiment exemplarily describes the structure of a switched capacitor variable gain amplifier circuit.

A circuit for eliminating fixed pattern noise described in this embodiment includes a dark pixel 01 , a bright pixel 02 , a constant current source Iref, a variable gain differential amplifier circuit, and a switch circuit. The dark pixels 01 are arranged in the pixel array of the image sensor, which can form a column or a row, or be arranged according to actual needs. The bright pixel 02 is any pixel unit under the illumination condition in the image sensor pixel array, and the dark pixel 01 and the bright pixel 02 are respectively connected with the constant current source Iref to convert their output currents into output voltages respectively, and the output is a voltage The pixel structure, this circuit does not need to set the constant current source Iref. The switch circuit is respectively connected between the dark pixel 01 and the variable gain differential amplifier circuit and between the bright pixel 02 and the variable gain differential amplifier circuit, and is used to control the connection or disconnection of the circuit.

The dark pixel 01 is mainly composed of a photodiode, a MOS amplifier tube, and a switch MOS tube; the cathode of the photodiode is controlled by a reset signal, and its anode is connected to the substrate of the MOS amplifier tube; the source of the MOS amplifier tube is connected to the drain of the switch MOS tube connected, and its gate is controlled by a bias voltage. The source of the switching MOS transistor is connected to a constant current source Iref to convert the output current of the dark pixel into an output voltage. The size structure and circuit design of the bright pixel 02 are exactly the same as those of the dark pixel 01 , and will not be repeated here.

When the gate bias voltage controls the MOS amplifier tube to work in the subthreshold region, an inversion layer channel is formed. When the incident light enters from the photodiode, it is absorbed by the photodiode and converted into photogenerated electron-hole pairs. Under the action of the built-in electric field of the diode, the holes are swept into the p-type substrate region, which increases the potential of the substrate, which in turn produces a forward body bias on the MOS amplifier tube and reduces the threshold voltage of the MOS amplifier tube. , using the principle of high transconductance amplification in the subthreshold region can realize the multiplication of current. Then the source output terminal of the switching MOS tube is connected to a constant current source, and the current change generated by the light is converted into a voltage change.

The variable gain differential amplifier circuit in this embodiment includes a sampling capacitor, a second capacitor C2 and an operational amplifier OPA1. The switching circuit includes a switch S ₁ , a switch S ₂ , a switch S ₃ , a switch S ₄ and a dual-phase non-overlapping clock signal generator (not shown in FIG. 4 ) for generating switching circuit timing to control each switch. The timing diagram of the switching circuit generated by the bi-phase non-overlapping clock signal generator is shown in Fig. 8 . One end of the _second capacitor C2 is connected to the positive output end of the operational amplifier OPA1, the other end is connected to the inverting input end of the operational amplifier OPA1, and connected to the sampling capacitor through the switch S2. There are two switches S1, wherein the _first switch S1 is connected between the constant current source Iref _of the bright pixel 02 and the sampling capacitor, and the second switch S1 is connected between the constant current source Iref of the dark pixel ₀₁ and the positive electrode of the operational amplifier OPA1. between the input terminals. One end _of the switch S3 is connected between the _first switch S1 and the sampling capacitor, and the other end is connected between the second switch S1 and the positive input end _of the operational amplifier. One end of the switch _S4 is connected between the switch S2 and the sampling capacitor, and the other end is connected between the _second switch S1 and the positive input end _of the operational amplifier. The sampling capacitor is composed of a first capacitor _C1 and a _third capacitor C3 connected in parallel. For the convenience of description above, the constant current source Iref of the bright pixel 02 is used to represent the constant current source Iref connected to the bright pixel 02, and the constant current source Iref of the dark pixel 01 is used to represent the constant current source Iref connected to the dark pixel 01, the same below.

The working process and principle of the switched capacitor variable gain amplifier circuit described in this embodiment are as follows:

In the first stage, under the control of the two-phase non-overlapping clock signal, the output voltage of the bright pixel under the light condition and the output voltage of the dark pixel under the dark condition charge the sampling capacitor composed of the first capacitor and the third capacitor, and the light intensity The information is converted into a voltage signal across a sampling capacitor composed of the first capacitor and the third capacitor.

In the second stage, under the control of the two-phase non-overlapping clock signal, the switch circuit controls the sampling capacitor composed of the first capacitor and the third capacitor to discharge, and charges the amplifying capacitor composed of the second capacitor. Finally, the light intensity signal is transferred to the output terminal.

Since the size and circuit design of the bright and dark pixels are exactly the same as those of the dark pixels, through the differential comparison of the variable gain amplifier, by changing the capacitance value of the sampling capacitor composed of the first capacitor and the third capacitor and the amplifying capacitor composed of the second capacitor The change of the gain value can be realized by the ratio of the capacitance value, so as to eliminate the fixed pattern noise and read the current light intensity change.

The switch S ₁ , switch S ₂ , switch S ₃ , and switch S ₄ described in this embodiment are mainly composed of MOS complementary transistor switching circuits.

When the control signal of the control terminal of the MOS complementary tube switch circuit is at low level, the switch is in the off state, and the signal transmission cannot be completed; when the control signal of the control terminal of the MOS complementary tube switch circuit is at high level, the switch is in the conduction state, It can complete the transmission process of the signal from the input to the output. Bi-phase non-overlapping clocks provide the corresponding timing signals for switching circuit operation.

Example 2

Referring to FIG. 6 , this embodiment exemplarily describes the structure of a resistor network variable gain amplifier circuit.

The circuit for eliminating fixed pattern noise described in this embodiment includes a dark pixel 01 , a bright pixel 02 , a constant current source Iref, a variable gain differential amplifier circuit, and a switch circuit. The dark pixel 01 and the bright pixel 02 are respectively connected to a constant current source Iref to convert their output currents into output voltages, but for a pixel structure whose output is a voltage, this circuit does not need to set a constant current source Iref. The switch circuit is respectively connected between the dark pixel 01 and the variable gain differential amplifier circuit and between the bright pixel 02 and the variable gain differential amplifier circuit, and is used to control the connection or disconnection of the circuit. The structures and arrangements of the dark pixels 01 and the bright pixels 02 in this embodiment are as described in Embodiment 1.

In this embodiment, the variable gain differential amplifier circuit includes a first resistor R ₁ , a variable resistor, and an operational amplifier OPA2. The switching circuit includes a switch S ₀ and a dual-phase non-overlapping clock signal generator (not shown in FIG. 6 ) for generating switching circuit timing to control the switch S ₀ . There are two switches _S0 , wherein the first switch _S0 is connected in series with the _first resistor R1 between the constant current source Iref of the bright pixel 02 and the inverting input terminal of the operational amplifier OPA2, and the second switch _S0 is connected in series It is connected between the constant current source Iref of the dark pixel 01 and the positive input terminal of the operational amplifier OPA2. One end of the variable resistor is connected in series with the _first resistor R1 to the inverting input end of the operational amplifier OPA2, and the other end is connected to the positive output end of the operational amplifier OPA. The variable resistor consists of a _second resistor R2 connected in series with a _third resistor R3. For the convenience of description above, the constant current source Iref of the bright pixel 02 is used to represent the constant current source Iref connected to the bright pixel 02, and the constant current source Iref of the dark pixel 01 is used to represent the constant current source Iref connected to the dark pixel 01, the same below.

The operational amplifier OPA2 adopted in this embodiment has the same structure and function as the operational amplifier OPA1 described in Embodiment 1.

In the resistor network variable gain amplification mode described in this embodiment, the analog image signal voltage output by bright pixels under light conditions and the reference voltage output by dark pixels under dark conditions are differentially output. At this time, the size of the gain is the ratio of the sum of the resistance values of the second resistor and the third resistor to the resistance value of the first resistor. By changing the sum of the resistance values of the second resistor and the third resistor and the first The ratio of the resistance values of the resistors is used to change the gain value.

Example 3

Referring to FIG. 7 , a circuit for eliminating fixed pattern noise described in this embodiment includes a dark pixel 01 , a bright pixel 02 , a constant current source Iref, a variable gain differential amplifier circuit, and a switch circuit. The dark pixel 01 and the bright pixel 02 are respectively connected to a constant current source Iref to convert their output currents into output voltages, but for a pixel structure whose output is a voltage, this circuit does not need to set a constant current source Iref. The switch circuit is respectively connected between the dark pixel 01 and the variable gain differential amplifier circuit and between the bright pixel 02 and the variable gain differential amplifier circuit, and is used to control the connection or disconnection of the circuit. The circuit structure and arrangement of the dark pixel 01 and the bright pixel 02 in this embodiment are as described in Embodiment 1.

The variable gain differential amplifier circuit in this embodiment includes both a switched capacitor variable gain amplifier circuit and a resistor network variable gain amplifier circuit.

As shown in FIG. 7 , the switched capacitor variable gain amplifier circuit includes a sampling capacitor, a _second capacitor C2 and an operational amplifier OPA1. The switch circuit includes a switch S ₁ , a switch S ₂ , a switch S ₃ , a switch S ₄ and a two-phase non-overlapping clock signal generator used to generate the switching circuit timing to control each switch. The switching circuit timing diagram generated by it is shown in Fig. 8.

_Both ends of the _second capacitor C2 are respectively connected to the inverting input terminal and the positive output terminal of the operational amplifier OPA1, and connected to the sampling capacitor through the switch S2. There are two switches S1, wherein the _first switch S1 is connected between the constant current source Iref _of the bright pixel 02 and the sampling capacitor, and the second switch S1 is connected between the constant current source Iref of the dark pixel ₀₁ and the positive electrode of the operational amplifier OPA1. between the input terminals. One end _of the switch S3 is connected between the _first switch S1 and the sampling capacitor, and the other end is connected between the second switch S1 and the positive input end _of the operational amplifier OPA1. One end of the switch _S4 is connected between the sampling capacitor and the switch S2, and the other end is connected between the _second switch S1 and the positive input end _of the operational amplifier OPA1. The sampling capacitor is composed of a first capacitor _C1 and a _third capacitor C3 connected in parallel.

As shown in FIG. 5 , the resistor network variable gain amplifier circuit in this embodiment includes a first resistor R ₁ , a variable resistor, and an operational amplifier OPA2. The switching circuit includes a switch S ₀ and a dual-phase non-overlapping clock signal generator for generating the timing sequence of the switching circuit to control the switch S ₀ ; the timing diagram of the switching circuit generated by it is shown in FIG. 8 .

There are two switches _S0 , wherein the first switch _S0 is connected in series with the _first resistor R1 between the constant current source Iref of the bright pixel 02 and the inverting input terminal of the operational amplifier OPA2, and the second switch _S0 is connected in series It is connected between the constant current source Iref of the dark pixel 01 and the positive input terminal of the operational amplifier OPA2. One end of the variable resistor is connected in series with the _first resistor R1 to the inverting input end of the operational amplifier OPA2, and the other end thereof is connected to the positive output end of the operational amplifier OPA2. The variable resistor consists of a _second resistor R2 connected in series with a _third resistor R3.

In this embodiment, the structures and functions of the operational amplifier OPA1 and the operational amplifier OPA2 are completely the same.

The working principles of the switched capacitor variable gain amplification mode and the resistor network variable gain amplification mode are described below.

When the switch _S0 is turned off, the variable gain differential amplifier circuit works in the switched capacitor variable gain amplifier mode.

Specifically, under the timing control of the switching circuit generated by the two-phase non-overlapping clock signal generator shown in Figure 8, in the switched capacitor variable gain amplification working mode, in the first stage, the switches S ₁ ₄ is turned on, the switches S ₂ and S ₃ are turned off, the voltage across the first capacitor C ₁ and the third capacitor C ₃ is equal to the output voltage of the randomly read bright pixel 02 under light conditions and the random read dark under dark conditions. The output voltage of pixel 01. At this moment, the magnitude of charge at the input terminal of the operational amplifier OPA1 is

Q＝(V _CM -V _IN )(C ₁ +C ₃ )

In the second stage, the switches S ₁ and S ₄ are turned off, and the switches S ₂ and S ₃ are turned on. At this time, the charge at the input terminal is transferred to C ₂ . Due to the charge conservation

(V _CM -V _IN )(C ₁ +C ₃ )＝(V _OUT -V _CM )C ₂

Through the operational amplifier OPA1, the output voltage of the randomly read bright pixel 02 under the light condition and the output voltage of the randomly read dark pixel 01 under the dark condition are differentially output. At this time, the output voltage gain is the ratio of the sum of the capacitance values of the first capacitor C ₁ and the third capacitor C ₃ to the capacitance value of the second capacitor C ₂ (C ₁ +C ₃ )/C ₂ .

By adjusting the proportional coefficient of the sum of the capacitance values of the first capacitor and the third capacitor and the capacitance value of the second capacitor, the output voltage of the operational amplifier and the output voltage of the randomly read bright pixel under the light condition and the dark condition can be adjusted Randomly read the magnification of the output voltage difference of the dark pixel under, and realize that the voltage gain changes with the change of the proportional coefficient.

Optionally, when signal reduction is required, the sum of the capacitance values of the first capacitor and the third capacitor may also be set to be smaller than the capacitance value of the second capacitor. In a word, regardless of signal amplification or reduction, the variable gain amplifier circuit in the embodiment of the present application can be implemented independently without a dedicated amplification or reduction circuit.

When the switch _S0 is closed, the variable gain differential amplifier circuit works in the resistor network variable gain amplifier mode.

In the working mode of the resistor network variable gain amplifier, using the "virtual short" working principle of the operational amplifier, the voltage at the inverting input terminal of the operational amplifier OPA2 is V _X =V _CM . According to Kirchhoff's current theorem, we can get

Substituting V _X = V _CM into the above formula can be obtained,

Through the operational amplifier, the output voltage of the randomly read bright pixel 02 under the light condition and the output voltage of the randomly read dark pixel 01 under the dark condition are differentially output. At this time, the magnitude of the voltage gain is the ratio of the sum of the resistance values of the second resistor and the third resistor to the resistance value of the first resistor (R ₂ +R ₃ )/R ₁ .

By adjusting the proportional coefficient of the sum of the resistance values of the second resistor and the third resistor and the resistance value of the first resistor, the output voltage of the operational amplifier and the output voltage of the random read bright pixel 02 under illumination conditions can be adjusted And the magnification of the output voltage of the random read dark pixel 01 under the dark condition, the realization gain changes with the change of the proportional coefficient.

Optionally, when signal reduction is required, the sum of the resistance values of the second resistor and the third resistor may also be set to be smaller than the resistance value of the first resistor. In a word, regardless of signal amplification or reduction, the variable gain amplifier circuit in the embodiment of the present application can be implemented independently without a dedicated amplification or reduction circuit.

It should be noted that the present invention is not limited to the above-mentioned embodiments, if the various changes or deformations of the present invention do not depart from the spirit and scope of the present invention, provided that these changes and deformations belong to the claims of the present invention and within the equivalent technical scope , the present invention is also intended to include these changes and modifications.

Claims

A circuit for eliminating fixed pattern noise, characterized by comprising:

A bright pixel, which is any pixel in the image sensor pixel array, is used to sense incident light and output an analog image signal voltage;

The dark pixel has the same size, structure and pixel circuit as the bright pixel, and its output voltage is used as the reference voltage of the variable gain differential amplifier circuit;

A variable gain differential amplifier circuit, which is respectively connected to the bright pixel and the dark pixel, and compares the reference voltage output by the dark pixel and the signal voltage output by the bright pixel to realize the removal of noise in the pixel array of the image sensor and the bright pixel Reading of the sensed incident light intensity signal;

The switch circuit is respectively connected between the dark pixel and the variable gain differential amplifier circuit and between the bright pixel and the variable gain differential amplifier circuit, and is used to control the connection or disconnection of the circuit.
A circuit for eliminating fixed pattern noise according to claim 1, wherein the variable gain differential amplifier circuit includes a sampling capacitor, a second capacitor, and an operational amplifier, and the switch circuit includes a switch S 1 , Switch S 2 , switch S 3 , switch S 4 , and a dual-phase non-overlapping clock signal generator for generating switching circuit timing to control each switch; both ends of the second capacitor are respectively connected to the reverse input of the operational amplifier The terminal is connected to the positive output terminal, and connected to the sampling capacitor through the switch S2 ; the switch S1 is two , wherein the first switch S1 is connected between the bright pixel and the sampling capacitor, and the second switch S1 is connected to the dark pixel. Between the pixel and the positive input terminal of the operational amplifier ; one end of the switch S3 is connected between the first switch S1 and the sampling capacitor, and the other end is connected between the second switch S1 and the positive input terminal of the operational amplifier ; One end of the switch S4 is connected between the switch S2 and the sampling capacitor, and the other end is connected between the second switch S1 and the positive input end of the operational amplifier.
The circuit for eliminating fixed pattern noise according to claim 2, wherein the sampling capacitor is composed of a first capacitor and a third capacitor connected in parallel.
A circuit for eliminating fixed pattern noise according to claim 1, wherein the variable gain differential amplifier circuit includes a first resistor, a variable resistor, and an operational amplifier; the switch circuit includes a switch S 0 and a dual-phase non-overlapping clock signal generator for generating switching circuit timing to control the switch S 0 ; the switch S 0 is two, wherein the first switch S 0 is connected in series with the first resistor in series Between the pixel and the inverting input terminal of the operational amplifier, the second switch S0 is connected in series between the dark pixel and the positive input terminal of the operational amplifier; one end of the variable resistor is connected in series with the first resistor and then connected to the The inverting input end of the operational amplifier is connected, and the other end is connected with the positive output end of the operational amplifier.
A circuit for eliminating fixed pattern noise according to claim 4, wherein the variable resistor is composed of a second resistor connected in series with a third resistor.
A circuit for eliminating fixed pattern noise according to claim 1, wherein the variable gain differential amplifier circuit includes a switched capacitor variable gain amplifier circuit and a resistor network variable gain amplifier circuit;

The switched capacitor variable gain amplifying circuit includes a sampling capacitor, a second capacitor, and an operational amplifier, and the switching circuit includes a switch S 1 , a switch S 2 , a switch S 3 , a switch S 4 , and is used to generate switching circuit timing to control each The two-phase non-overlapping clock signal generator of the switch; The two ends of the second capacitor are respectively connected to the inverting input terminal and the positive output terminal of the operational amplifier, and are connected to the sampling capacitor through the switch S2 ; the switch S 1 is two, wherein the first switch S1 is connected between the bright pixel and the sampling capacitor, the second switch S1 is connected between the dark pixel and the positive input terminal of the operational amplifier ; one end of the switch S3 is connected to the first Between a switch S1 and the sampling capacitor, the other end is connected between the second switch S1 and the positive input end of the operational amplifier ; one end of the switch S4 is connected between the switch S2 and the sampling capacitor, and the other end is connected between the second switch S1 and the positive input terminal of the operational amplifier;

The resistor network variable gain amplifying circuit includes a first resistor, a variable resistor, and an operational amplifier; the switch circuit includes a switch S0 and a dual-phase non-overlapping clock for generating switching circuit timing to control the switch S0 Signal generator; there are two switches S 0 , wherein the first switch S 0 is connected in series with the first resistor between the bright pixel and the inverting input terminal of the operational amplifier, and the second switch S 0 is connected in series with the dark pixel. Between the pixel and the positive input of the operational amplifier; one end of the variable resistor is connected in series with the first resistor and connected to the negative input of the operational amplifier, and the other end is connected to the positive output of the operational amplifier end connection.
A circuit for eliminating fixed pattern noise according to claim 6, characterized in that: the sampling capacitor is composed of a first capacitor and a third capacitor connected in parallel; the variable resistor is composed of a second resistor and The third resistor is connected in series.
A circuit for eliminating fixed pattern noise according to any one of claims 2, 4 or 6, characterized in that: said bright pixels and dark pixels are mainly composed of passive pixels, active pixels or random read active pixels The composition of the pixel circuit.
A circuit for eliminating fixed pattern noise according to claim 8, characterized in that: said bright pixels and dark pixels are mainly composed of a random read active pixel circuit structure, including photodiodes, MOS amplifiers and switches MOS tube; the cathode of the photodiode is controlled by a reset signal, and its anode is connected to the substrate of the MOS amplifier tube; the source of the MOS amplifier tube is connected to the drain of the switch MOS tube, and its gate is controlled by a bias voltage; the switch The source of the MOS transistor is connected with a constant current source to convert the output current of the bright pixel or the dark pixel into an output voltage.
An image sensor, characterized in that the circuit according to claim 1 is arranged in the image sensor.