CN111095915B

CN111095915B - Dark current correlated double sampler, image sensor and dark current compensation method

Info

Publication number: CN111095915B
Application number: CN201980004076.2A
Authority: CN
Inventors: 王程左; 詹昶
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2019-08-29
Filing date: 2019-08-29
Publication date: 2022-03-15
Anticipated expiration: 2039-08-29
Also published as: CN111095915A; WO2021035605A1

Abstract

The embodiment of the application provides a dark current correlated double sampler, an image sensor and a dark current compensation method, comprising the following steps: the circuit comprises a switch circuit, n first capacitors, m second capacitors, an integrating capacitor and an operational amplifier, wherein the sum of the capacitance values of the n first capacitors is equal to the sum of the capacitance values of the m second capacitors; the n first capacitors are respectively connected with the output voltages of the n active pixels and the inverting input end of the operational amplifier through the switch circuit, the m second capacitors are respectively connected with the output voltages of the m dark pixels and the inverting input end of the operational amplifier through the switch circuit, and the integrating capacitor is connected between the inverting input end and the output end of the operational amplifier through the switch circuit. The subtraction of the output voltage of the active pixel from the output voltage of the dark pixel can be directly achieved by a dark current dependent double sampler to compensate for the dark current in the active pixel.

Description

Dark current correlated double sampler, image sensor and dark current compensation method

Technical Field

The embodiments of the present application relate to the field of CMOS image sensors, and more particularly, to a dark current correlated double sampler, an image sensor, and a dark current compensation method.

Background

A Complementary Metal Oxide Semiconductor (CMOS) dark current refers to a reverse current generated when a photodiode is in a dark environment under a reverse bias condition. Typically due to carrier diffusion motion, device surface, internal defects, and unwanted impurities. The magnitude of the dark current is therefore closely related to temperature and there may be inconsistencies and randomness in the distribution across the spatial plane. Dark current limits sensitivity, dynamic range, and SIGNAL-to-NOISE RATIO (SNR) and the like of the image sensor, and therefore dark current compensation is required.

Dark current compensation in the prior art eliminates dark current in a pixel array by means of complex hardware circuitry. For example, some dark pixels are disposed in an active pixel region, the active pixel and the dark pixel are respectively sampled by a dark current Correlated Double Sampler (CDS), output voltages of the active pixel and the dark pixel sampled by the CDS are respectively stored by two memories, and the dark current in the active pixel is removed by a compensation circuit after the output voltages are amplified by a programmable-gain amplifier (PGA). The prior art needs to expend a lot of hardware cost.

Disclosure of Invention

The embodiment of the application provides a dark current correlated double sampler, an image sensor and a dark current compensation method, and the subtraction of the output voltage of an active pixel and the output voltage of a dark pixel can be realized through the dark current correlated double sampler without a special memory and a special compensation circuit so as to compensate the dark current in the active pixel.

In a first aspect, a dark current correlated double sampler is provided, comprising: the circuit comprises a switching circuit, n first capacitors, m second capacitors, an integrating capacitor and an operational amplifier, wherein the sum of capacitance values of the n first capacitors is equal to the sum of capacitance values of the m second capacitors, and n and m are positive integers; the n first capacitors are respectively connected with the output voltages of the n active pixels and the inverting input end of the operational amplifier through the switch circuit, the m second capacitors are respectively connected with the output voltages of the m dark pixels and the inverting input end through the switch circuit, and the integrating capacitor is connected between the inverting input end and the output end through the switch circuit.

According to the embodiment of the application, the sum of the capacitance values of the n first capacitors connected with the output voltage of the active pixel is set to be equal to the sum of the capacitance values of the m second capacitors connected with the output voltage of the dark pixel, so that the subtraction between the output voltage of the active pixel and the output voltage of the dark pixel can be realized through the output end of the dark current related double sampler without a special memory and a compensation circuit, and the dark current in the active pixel is compensated.

The dark current correlated double sampler in the embodiment of the application is beneficial to reducing the hardware cost of the image sensor.

In a possible implementation manner, in the first stage, the switch circuit is configured to control the n first capacitors and the m second capacitors to be charged, and the switch circuit is further configured to control the integration capacitor to be discharged; in a second phase, the switch circuit is used for controlling the n first capacitors and the m second capacitors to stop charging and controlling the n first capacitors and the m second capacitors to discharge to the integration capacitor.

In one possible implementation, the ratio of the sum of the capacitance values of the n first capacitors and the sum of the capacitance values of the m second capacitors to the capacitance value of the integrating capacitor is k/p, where k is greater than or equal to p.

By adjusting the proportionality coefficient k/p of the capacitance values of the charge and discharge capacitor (the first capacitor or the second capacitor) and the integration capacitor, signal amplification can be realized.

When the dark current correlated double sampler is applied to an image sensor, signal amplification can be realized without a special PGA, so that the cost of the image sensor can be further reduced.

Alternatively, k may be set smaller than p when signal reduction is required. In summary, the dark current correlated double sampler in the embodiment of the present application can be implemented independently without a dedicated amplifying or reducing circuit, regardless of signal amplification or reduction.

In one possible implementation, the n active pixels and the m dark pixels constitute one pixel unit in a pixel array.

Because the dark current in each pixel unit is likely to have larger difference, the dark pixels with a certain ratio are inserted into each pixel unit, so that the dark current elimination of each pixel unit can be completed, and the dark current elimination result is more accurate and the precision is higher.

In one possible implementation, n is a positive integer greater than 1.

Alternatively, n may also be equal to 1.

When the dark current correlated double sampler in the embodiment of the application is applied to an image sensor, dark current compensation can be performed after averaging a plurality of active pixels, the circuit structure of the image sensor can be simplified, and therefore the cost of the image sensor can be reduced.

In one possible implementation, the switching circuit includes a first switch group and a second switch group, one end of the n first capacitors is connected with the output voltage of the n active pixels through the first switch group and is connected with the common mode voltage through the second switch group, the other end of the n first capacitors is connected with the common mode voltage through the first switch group and is connected with the inverting input end through the second switch group, one end of the m second capacitors is connected to the output voltages of the m dark pixels through the first switch group and to the inverting input terminal through the second switch group, the other ends of the m second capacitors are connected with the common-mode voltage, the integrating capacitor is connected with the switches in the first switch group in parallel, and the positive input end of the operational amplifier is connected with the common-mode voltage.

In one possible implementation, the switching circuit includes a first switch group and a second switch group,

one end of each of the n first capacitors is connected with the output voltage of the n active pixels through the first switch group and the inverting input end through the second switch group, the other end of each of the n first capacitors is connected with a common-mode voltage, one end of each of the m second capacitors is connected with the output voltage of the m dark pixels through the first switch group and the common-mode voltage through the second switch group, the other end of each of the m second capacitors is connected with the common-mode voltage through the first switch group and the inverting input end through the second switch group, the integrating capacitor is connected with the switches in the first switch group in parallel, and the forward input end of the operational amplifier is connected with the common-mode voltage.

Optionally, in a first phase, the first switch set is closed and the second switch set is open; in a second phase, the first switch set is open and the second switch set is closed.

In one possible implementation, any one of the n active pixels and the m dark pixels includes a photodiode, a transmission transistor, a reset switch tube, a source follower input tube, and a gate switch tube; the photoelectric conversion device comprises a photoelectric diode, a transmission tube, a source follow input tube, a gate switch tube, a reset switch tube and a source follow input tube, wherein light with different intensities generates different amounts of charges in the photoelectric diode, the generated charges are converted into voltages under the transmission of the transmission tube, the converted voltages are output to the first capacitor or the second capacitor through the source follow input tube and the gate switch tube, and the reset switch tube is used for resetting the photoelectric diode.

In one possible implementation, the any one pixel further includes a parasitic capacitor; the positive electrode of the photodiode is grounded, the negative electrode of the photodiode is connected with the source electrode of the transmission tube, the grid electrode of the transmission tube is controlled by a transmission signal, the drain electrode of the transmission tube is respectively connected with one end of the parasitic capacitor, the grid electrode of the source following input tube and the source electrode of the reset switch tube, the other end of the parasitic capacitor is grounded, the drain electrode of the reset switch tube is connected with a reset voltage, the grid electrode of the reset switch tube is controlled by the reset signal, the source electrode of the source following input tube is connected with the drain electrode of the gating switch tube, the drain electrode of the source following input tube is connected with a power voltage, the grid electrode of the gating switch tube is controlled by the gating signal, and the source electrode of the gating switch tube outputs the output voltage of the corresponding pixel.

In one possible implementation, in a third phase, the reset switch tubes and the transfer tubes of all the n active pixels and the m dark pixels are turned on, and the photodiodes of all the pixels are reset to the reset voltage; in the fourth stage, the reset switch tubes and the transmission tubes of all the pixels are closed, and all the pixels start to be exposed.

In a second aspect, there is provided an image sensor comprising a pixel array comprising the n active pixels and the m dark pixels, a dark current dependent double sampler as in the first aspect or any implementation thereof, and an analog-to-digital converter for converting an analog output of the dark current dependent double sampler to a digital output.

In one possible implementation, the n active pixels and the m dark pixels constitute one pixel unit in the pixel array, and the image sensor further includes a row scan controller and a column scan controller for selecting the one pixel unit.

Alternatively, the pixel array may include a plurality of pixel units, wherein each pixel unit may include n active pixels and m dark pixels.

In a third aspect, there is provided a dark current compensation method performed by a dark current-dependent double sampler comprising a switching circuit, n first capacitors, m second capacitors, an integrating capacitor, and an operational amplifier, a sum of capacitance values of the n first capacitors being equal to a sum of capacitance values of the m second capacitors, n and m being positive integers, the method comprising: in a first stage, under the control of the switch circuit, the n first capacitors respectively sample the output voltages of the n active pixels, and the m second capacitors respectively sample the output voltages of the m dark pixels; in the second stage, under the control of the switch circuit, the sampled charges on the n first capacitors and the sampled charges on the m second capacitors are respectively transferred to the integrating capacitor, and the output voltage of the operational amplifier is used for representing the difference value between the output voltage of the n active pixels and the output voltage of the m dark pixels.

In one possible implementation manner, the operational amplifier includes a positive phase input terminal, a negative phase input terminal, and an output terminal, the n first capacitors are respectively connected to the output voltages of the n active pixels and the negative phase input terminal of the operational amplifier through the switch circuit, the m second capacitors are respectively connected to the output voltages of the m dark pixels and the negative phase input terminal through the switch circuit, and the integrating capacitor is connected between the negative phase input terminal and the output terminal through the switch circuit.

The above third aspect, the dark current compensation method according to the embodiment of the present application may correspond to each unit/module in the dark current correlated double sampler according to the embodiment of the present application of the first aspect, and the corresponding process in the method may be implemented by each unit/module in the dark current correlated double sampler according to the first aspect, and is not described herein again for brevity.

Drawings

Fig. 1 shows a block circuit diagram of a typical image sensor.

Fig. 2 shows a schematic circuit block diagram of a dark current correlated double sampler of an embodiment of the application.

Fig. 3 shows a schematic circuit diagram of a pixel cell of an embodiment of the present application.

Fig. 4 shows a circuit schematic of a dark current correlated double sampler of an embodiment of the present application.

Fig. 5 shows another circuit schematic of a dark current correlated double sampler of an embodiment of the present application.

Fig. 6 shows an operation timing diagram of a dark current correlated double sampler according to an embodiment of the present application.

Fig. 7 shows a circuit block diagram of an image sensor of an embodiment of the present application.

Fig. 8 shows a schematic block diagram of a dark current compensation method of an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

Dark current compensation principle: if the output signal is sampled at the integration start time t1 and the integration end time t2 of the photoelectric signal (two sampling pulses are generated in one signal output period, and two voltages of the output signal are sampled respectively, that is, once the output voltage of the dark pixel is sampled, and the other time the output voltage of the active pixel is sampled), and the sampling time interval is held for two times, and if the two sampling values are processed by the subsequent compensation circuit, the dark current is basically eliminated, and the effective signal quantity of the active pixel for the light input quantity conversion within a certain exposure time is obtained.

Fig. 1 shows a schematic diagram of a typical image sensor 10. As shown in fig. 1, the image sensor 10 includes a pixel array 11, a CDS 13, a first memory 14, a second memory 15, and a compensation circuit 16, wherein the pixel array 11 includes a plurality of dark pixels 11a and a plurality of active pixels 11 b. The CDS 13 is used to sample the output voltages of the active pixel 11b and the dark pixel 11a, respectively, the first memory 14 is used to store the output voltage of the active pixel 11b, the second memory is used to store the output voltage of the dark pixel 11a, and the compensation circuit 16 performs dark current compensation by subtracting the output voltage of the dark pixel 11a in the second memory from the output voltage of the active pixel 11b in the first memory. Further, the image sensor 10 may further include a PGA (not shown in the drawings), and the output voltage of the compensation circuit is amplified by the PGA. The CDS in fig. 1 is only used to sample the output voltages of the dark pixel and the active pixel, and the processing of the sampled output voltages of the active pixel and the dark pixel is implemented on other hardware circuits. Therefore, the cost of the image sensor in fig. 1 is relatively high.

The embodiment of the application provides a novel dark current correlated double sampler, and when the dark current correlated double sampler is applied to an image sensor, the hardware cost of the image sensor can be reduced. As shown in fig. 2, the dark current correlated double sampler may include: the circuit comprises a switching circuit, n first capacitors, m second capacitors, an integrating capacitor and an operational amplifier, wherein the sum of capacitance values of the n first capacitors is equal to the sum of capacitance values of the m second capacitors, and n and m are positive integers; the n first capacitors are respectively connected with the output voltages of the n active pixels and the inverting input end of the operational amplifier through the switch circuit, the m second capacitors are respectively connected with the output voltages of the m dark pixels and the inverting input end through the switch circuit, and the integrating capacitor is connected between the inverting input end and the output end of the operational amplifier through the switch circuit.

Specifically, under the control of the switching circuit, the n first capacitors and the m second capacitors may be charged, and the integration capacitor may be discharged such that the amount of charge across the integration capacitor is zero. Then, under the control of the switching circuit, the charged n first capacitors and m second capacitors are discharged to the integrating capacitor and output through an output terminal of an operational amplifier.

Alternatively, it can be said that, under the control of the switching circuit, the n first capacitors sample the output voltages of the n active pixels, respectively, and the m second capacitors sample the output voltages of the m dark pixels, respectively. Then, under the control of the switch circuit, the sampled charges on the n first capacitors and the sampled charges on the m second capacitors are respectively transferred to the integration capacitor and output through an output terminal of an operational amplifier, wherein an output voltage of the operational amplifier is used for representing a difference value between the output voltage of the n active pixels and the output voltage of the m dark pixels.

According to the embodiment of the application, the sum of the capacitance values of the n first capacitors connected with the output voltage of the active pixel and the sum of the capacitance values of the m second capacitors connected with the output voltage of the dark pixel are set to be equal, so that the subtraction between the output voltage of the active pixel and the output voltage of the dark pixel can be realized through the output end of the dark current correlated double sampler without a special memory and a compensation circuit, and the dark current in the active pixel is compensated.

It should be understood that the first capacitor, the second capacitor and the operational amplifier in the operating state should be referenced to the same voltage, e.g., a common mode voltage.

Optionally, in an embodiment of the present application, a ratio of a sum of capacitance values of the n first capacitors and a sum of capacitance values of the m second capacitors to a capacitance value of the integration capacitor is k/p.

Since the sum of the capacitance values of the n first capacitors is equal to the sum of the capacitance values of the m second capacitors, the ratio of the sum of the capacitance values of the n first capacitors to the capacitance value of the integration capacitor or the ratio of the sum of the capacitance values of the m second capacitors to the capacitance value of the integration capacitor is k/p.

Signal amplification can be achieved by adjusting the proportionality coefficient k/p of the capacitance values of the charge and discharge capacitor (first capacitor or second capacitor) and the integration capacitor, for example, k is greater than or equal to p. When the dark current correlated double sampler is applied to an image sensor, signal amplification can be realized without a special PGA, so that the cost of the image sensor can be further reduced.

Optionally, in an embodiment of the present application, the n active pixels and the m dark pixels may constitute one pixel unit in a pixel array. That is, one pixel unit may be divided into a plurality of sub-pixels, and the plurality of sub-pixels may be respectively set as an active sub-pixel and a dark sub-pixel.

Optionally, in another embodiment of the present application, each of the n active pixels and the m dark pixels may also be a pixel unit in a pixel array.

It should be understood that the pixel array in the embodiment of the present application may include a plurality of pixel units, each of the pixel units may be divided into a plurality of sub-pixels including an active sub-pixel and a dark sub-pixel, and each of the pixel units may implement dark current cancellation by using one dark current correlated double sampler; it is also possible that each pixel unit in a part of pixel units is divided into a plurality of sub-pixels including active sub-pixels and dark sub-pixels, and the part of pixel units respectively adopt one dark current correlated double sampler to realize dark current elimination, while each pixel unit in another part of pixel units can be one active pixel or dark pixel, together constituting n active pixels and m dark pixels, and adopt one dark current correlated double sampler to realize dark current elimination.

In the prior art, dark pixels are usually arranged at the periphery of an active pixel area, the average value of the dark pixels is read to represent the dark current in a pixel array, and a dark current signal is estimated and eliminated through the processing of a late software algorithm. The dark current of each pixel unit may have a large difference due to uneven distribution of the dark current in the pixel array, uneven heating and the like, so that the prior art cannot achieve the expected effect. In the embodiment of the application, a certain ratio of dark pixels can be inserted into each pixel unit, and the compensation of the dark current of each pixel unit can be completed, so that the dark current elimination result is more accurate and the precision is higher.

Optionally, n is a positive integer greater than 1, that is, the n first capacitors are a plurality of first capacitors.

Alternatively, n may also be equal to 1, and likewise the subtraction of the output voltage of the active pixel from the output voltage of the dark pixel to compensate for the dark current in the active pixel can be implemented at the output of the dark current dependent double sampler.

Fig. 3 shows an embodiment of a pixel unit provided in the present application. In this example, a pixel unit consists of 4 identical sub-pixels 1-4, where 3 sub-pixels are active pixels and 1 sub-pixel is a dark pixel. The ratio of active pixels to dark pixels is 3: 1. It should be noted that the embodiment of the present application is not limited to the ratio between the active pixel and the dark pixel in fig. 3, and any reasonable ratio value may be set in specific implementation. Or in specific implementation, the ratio of the PD areas of the active pixel and the dark pixel in fig. 3 is equal to the ratio of the FD parasitic capacitor CFD.

Specifically, as shown in fig. 3, one pixel unit is composed of 4 sub-pixels, where sub-pixels 1 to 3 are active sub-pixels and sub-pixel 4 is a dark sub-pixel. One sub-pixel may include a Photodiode (PD), a transfer transistor M1, a reset switch M2, a source follower input transistor M3, and a gate switch M4; wherein, different intensities of light illuminate to generate different amounts of charges in the photodiode PD, the charges are transmitted to the FD point through the transmission tube M1, the FD point is converted into a voltage signal, the node voltage is output to the first capacitor or the second capacitor through the source follower input tube M3 and the gate switch tube M4, and the reset switch tube M2 is used for resetting the photodiode PD.

Optionally, as shown in fig. 3, one of the sub-pixels further includes a parasitic capacitor CFD, wherein the anode of the photodiode PD is grounded, the cathode of the photodiode PD is connected to the source of the pass transistor M1, the gate of the pass transistor M1 is controlled by a pass signal TX, and the drain of the pass transistor M1 and the parasitic capacitor C are respectively connected to the drain of the pass transistor M1_FDThe gate of the source follower input transistor M3 and the source of the reset switch transistor M2, the other end of the parasitic capacitor CFD is grounded, and the drain of the reset switch transistor is connected to a reset voltage V_rstThe grid electrode of the reset switch tube is controlled by a reset signal RST, the source electrode of the source following input tube M3 is connected with the drain electrode of the gating switch tube M4, the drain electrode of the source following input tube M3 is connected with a power supply voltage VCCP, the grid electrode of the gating switch tube M4 is controlled by a gating signal RSEL, and the source electrode of the gating switch tube M4 outputs the output voltage of the corresponding sub-pixel. For example, subpixel 1 outputs V_p1Sub-pixel 2 outputs V_p2Sub-pixel 3 outputting V_p3The sub-pixel 4 outputs V_p4。

It should be noted that the circuit structure of the sub-pixel in the embodiment of the present application includes, but is not limited to, the circuit structure shown in fig. 3. For example, the circuit structure of the sub-pixel may be a Capacitive feedback Trans-impedance Amplifier (CTIA) structure.

The dark current correlated double sampler of the embodiment of the present application will be described in detail below in conjunction with the embodiment of fig. 3.

FIG. 4 is a circuit schematic of a dark current correlated double sampler of one embodiment of the present application. Wherein, V_p1，V_p2，V_p3，V_p4Corresponding to the output voltage, V, of each sub-pixel in FIG. 3_p1，V_p2And V_p3Is the output voltage, V, of the active sub-pixel in a pixel unit_p4Is the output voltage of the dark sub-pixel in one pixel unit.

As shown in fig. 4, the dark current correlated double sampler includes: 1 capacitor 101 (i.e., the second capacitor in fig. 2), 3 capacitors 102 (i.e., the first capacitor in fig. 2), an operational amplifier 103 (i.e., the operational amplifier in fig. 2), a switch bank 1041 and a switch bank 1042 (i.e., the switch circuit in fig. 2, which may include the first switch bank and the second switch bank), and an integration capacitor 105 (i.e., the integration capacitor in fig. 2).

Wherein, one end of the capacitor 101 is connected to the output voltage V of the dark sub-pixel in one pixel unit in FIG. 3_p4The other end of capacitor 101 is connected to a common-mode voltage VCM, which may also be referred to as a reference voltage, by at least one switch of switch bank 1041 and by one switch of switch bank 1042 being connected to the inverting input of operational amplifier 103. One terminal of each capacitor 102 is connected to the output voltage of one active sub-pixel in one pixel unit in fig. 3 through one switch in the switch group 1041. I.e. one end of 3 capacitors 102 is connected to V_p1，V_p2And V_p3In addition, one end of each capacitor 102 may be connected to the common mode voltage through one switch in the switch group 1042, that is, one end of each of the 3 first capacitors 102 is connected to the common mode voltage. The other end of the 3 capacitors 102 can be connected to the inverting input of the operational amplifier 103 through the same switch in the switch group 1042 and through the switchGroup 1041 is connected to a common mode voltage. The integration capacitor 105 is connected in parallel with one switch in the switch group 1041, and is connected between the inverting input terminal and the output terminal of the operational amplifier 103. The positive input of the operational amplifier 103 may be connected to a common mode voltage.

Optionally, one end of the capacitor 101 may be connected to V through one or more switches in the switch group 1041_p4Connected, for example, to V by the same number of switches as the capacitors 102_p4The present embodiment is not limited to this. Specifically, in the embodiment of the present application, one end of the capacitor 101 may be connected to V through 3 switches in the switch group 1041_p4The connection makes it possible to avoid as much as possible the influence of the switch on the feed-through of the charge (or the influence of the charge injection) of the circuit.

The operation timing of the dark current correlated double sampler shown in fig. 4 will be described below in conjunction with the timing chart in fig. 6.

With respect to fig. 6, the operation timing of the dark current correlated double sampler in fig. 4 mainly includes four phases, wherein a first phase (the below-described T4 time period), a second phase (the below-described T5 time period), a third phase (the below-described T1 time period), and a fourth phase (the below-described T2 time period).

Specifically, during the time period T1, RST and TX of four sub-pixels in a selected row and column of pixel units are high, the reset switch M2 and the pass transistor M1 are turned on, and the FD and the photodiode PD are both reset to V_rstVoltage at which the theoretical value of the output voltage is V_{P1_0}、V_{P2_0}、V_{P3_0}And V_{P3_0}. Since they are reset simultaneously and the readout circuit error for each sub-pixel is considered to be the same, then V_{P1_0}＝V_{P2_0}＝V_{P3_0}＝V_{P4_0}＝V_{P_RST}Wherein V is_{P_RST}＝V_rst-V_gs，V_gsThe source follows the gate-source voltage of the input tube. During the time period T2, RST and TX are low, the reset switch M2 and pass transistor M1 are turned off, and the pixel cell begins to be exposed. In the stage, the active sub-pixel converts corresponding electrons according to different light incoming quantities, and correspondingly, electrons accumulated by dark current; dark sub-pixelOnly electrons generated by dark current are accumulated because they are not sensitive to light because they are in a dark environment. Alternatively, within a single pixel unit, we can consider the dark current densities of the four sub-pixels to be approximately equal, and the ratio of their PD areas to the CFD is equal, so at the end of the exposure, we can express the output voltage V of the active sub-pixel_p1～3＝V_{P_RST}–V_{P_LI}–V_{P_DK}＝V_{sig_a1～3}I.e. V_p1＝V_{sig_a1},V_p2＝V_{sig_a2},V_p3＝V_{sig_a3}Wherein V is_{P_LI}Voltage, V, representing the amount of light entering converted during a given exposure time_{P_DK}Indicating that dark current generates a voltage during a certain exposure time, assuming V_{sig_a1～3}＝V_{sig_a}(ii) a Similarly, at the exposure end time V_P4＝V_{P_RST}–V_{P_DK}＝V_{sig_d}. In the period T3, the operational amplifier enable signal OP _ EN of the dark current correlated double sampler is high, and the operational amplifier 103 is turned on in advance to prepare for operation.

Assume that switch block 1041 is controlled by switch signal SW1, switch block 1042 is controlled by switch signal SW2, the capacitance of capacitor 102 is represented by C2, the capacitance of capacitor 101 is represented by C1, and the capacitance of integrating capacitor 105 is represented by C_intThe operational amplifier is denoted by OP, where C1 is equal to the sum of 3C 2, i.e., if C2 is equal to C, then C1 is equal to 3C.

During the period of T4, SW1 pulls high to turn on switch bank 1041 and SW2 pulls low to turn on switch bank 1042. Capacitor 101 to V_P4Sampling, the amount of charge on the capacitor 101: q1 ═ 3C (V)_{sig_d}-VCM); capacitor 102 pair V_P1/V_P2/V_P3Sampling and averaging, the charge amount on an equivalent capacitor formed by 3 capacitors 102 in parallel: q2 ═ 3C (V)_{sig_a}-VCM); the integrating capacitor 105 is reset and VO is VCM using the virtual short principle of OP.

During the period of time T5, SW1 pulls down turn-off switch group 1041 and SW2 pulls up turn-on switch group 1042. The upper plate of the capacitor 101 is connected with the inverting input end of the OP, the lower plate of the capacitor 101 is connected with the VCM, the lower plate of the capacitor 102 is connected with the inverting input end of the OP, and the upper plate of the capacitor 102The plate is connected to VCM, and the charges of capacitor 101 and capacitor 102 are transferred to integrating capacitor 105, assuming that OP gain is large enough, by using the virtual short principle of OP,

from the fact that the sum of the charge on capacitor 101 and the charge on the equivalent capacitor formed by the parallel connection of 3 capacitors 102 is equal to the charge on integrating capacitor 105, the following equation can be derived:

-C_int(VO-VCM)+C1*(V_{sig_d}-VCM)-C2^’*(V_{sig_a}-VCM)＝0

where C2' represents the capacitance of an equivalent capacitor formed by 3 capacitors 102 connected in parallel, assuming that C is the capacitance of C_intSubstituting n × C, C1 ═ C2 ═ 3 × C into the above formula

VO＝VCM+(V_{sig_d}-V_{sig_a})*3/n＝VCM-V_{P_LI}*3/n

From the above, the dark current correlated double sampler in the embodiment of the present application can simultaneously sample the output voltage of the active pixel and the output voltage of the dark pixel through the n first capacitors and the m second capacitors, and simultaneously transfer the charges on the n first capacitors and the m second capacitors after sampling to the integrating capacitor, so as to achieve the purpose of eliminating the dark current in the active pixel. In the embodiment of the application, the output signal of the dark current correlated double sampler only remains the common mode voltage VCM and the illumination conversion voltage V_{P_LI}Therefore, useful illumination conversion semaphore can be obtained, and the effect of eliminating the influence of dark current is achieved. Meanwhile, the PGA can be omitted by adjusting the coefficient n to realize the signal amplification effect.

FIG. 5 is a circuit schematic of a dark current correlated double sampler according to another embodiment of the present application. Wherein, V_p1，V_p2，V_p3，V_p4Corresponding to the output voltage, V, of each sub-pixel in FIG. 3_p1，V_p2And V_p3Is the output voltage, V, of the active sub-pixel in a pixel unit_p4Is the output voltage of the dark sub-pixel in one pixel unit.

As shown in fig. 5, the dark current correlated double sampler includes: 1 capacitor 201 (i.e., the second capacitor in fig. 2), 3 capacitors 202 (i.e., the first capacitor in fig. 2), an operational amplifier 203 (i.e., the operational amplifier in fig. 2), a switch bank 2041 and a switch bank 2042 (i.e., the switch circuit in fig. 2, which may include a first switch bank and a second switch bank), and an integration capacitor 205 (i.e., the integration capacitor in fig. 2).

Wherein, one end of the capacitor 201 is connected to the output voltage V of the dark sub-pixel in one pixel unit in FIG. 3_p4Connected through at least one switch in switch bank 2041 and through at least one switch in switch bank 2042 to a common mode voltage VCM, which may also be referred to as a reference voltage. The other terminal of the capacitor 201 is connected to the inverting input of the operational amplifier 203 through a switch in the switch group 2042 and to VCM through a switch in the switch group 2041. One terminal of each capacitor 202 is connected to the output voltage of one active sub-pixel in one pixel unit in fig. 3 through one switch in the switch group 2041. I.e. one end of 3 capacitors 202 is connected to V_p1，V_p2And V_p3One end of each capacitor 202 may also be connected to the inverting input terminal of the operational amplifier 203 through one switch in the switch group 2042, that is, one end of each of the 3 capacitors 202 may be connected to the inverting input terminal of the operational amplifier 203 through the same switch in the switch group 2042. The other terminal of each capacitor 202 is connected to a common mode voltage. The integration capacitor 205 is connected in parallel with one switch of the switch group 2041 and is connected between the inverting input terminal and the output terminal of the operational amplifier 203. The positive input of the operational amplifier 203 is connected to a common mode voltage.

Optionally, one end of the capacitor 201 may be connected to V through one switch or multiple switches in the switch group 2041_p4Connected, for example, to V by the same number of switches as the capacitors 202_p4The present embodiment is not limited to this. Specifically, in the embodiment of the present application, one end of the capacitor 201 can be connected to V through 3 switches in the switch group 2041_p4Are connected, so that the switch pairs can be avoided as much as possibleThe effect of charge feed-through (or the effect of charge injection) by the circuit.

The operation timing of the dark current correlated double sampler shown in fig. 5 will be described below in conjunction with the timing chart in fig. 6.

Similarly, with respect to fig. 6, the operation timing of the dark current correlated double sampler in fig. 4 mainly includes four phases, wherein a first phase (the below-described T4 time period), a second phase (the below-described T5 time period), a third phase (the below-described T1 time period), and a fourth phase (the below-described T2 time period).

Specifically, during the time period T1, RST and TX of four sub-pixels in a selected row and column of pixel units are high, the reset switch M2 and the pass transistor M1 are turned on, and the FD and the photodiode PD are both reset to V_rstVoltage at which the theoretical value of the output voltage is V_{P1_0}、V_{P2_0}、V_{P3_0}And V_{P3_0}. Since they are reset simultaneously and the readout circuit error for each sub-pixel is considered to be the same, then V_{P1_0}＝V_{P2_0}＝V_{P3_0}＝V_{P4_0}＝V_{P_RST}Wherein V is_{P_RST}＝V_rst-V_gs，V_gsThe source follows the gate-source voltage of the input tube. During the time period T2, RST and TX are low, the reset switch M2 and pass transistor M1 are turned off, and the pixel cell begins to be exposed. In the stage, the active sub-pixel converts corresponding electrons according to different light incoming quantities, and correspondingly, electrons accumulated by dark current; the dark sub-pixel is not sensitive to light because it is in a dark environment and thus accumulates only electrons generated by dark current. Alternatively, within a single pixel unit, we can consider the dark current densities of the four sub-pixels to be approximately equal, and the sum of their PD area ratios C_FDThe ratio is equal, so at the time of the end of exposure T3, we can express the output voltage V of the active sub-pixel_p1～3＝V_{P_RST}–V_{P_LI}–V_{P_DK}＝V_{sig_a1～3}I.e. V_p1＝V_{sig_a1},V_p2＝V_{sig_a2},V_p3＝V_{sig_a3}Wherein V is_{P_LI}Voltage, V, representing the amount of light entering converted during a given exposure time_{P_DK}Show at a certain exposureDark current produces a voltage in the light time, assuming V_{sig_a1～3}＝V_{sig_a}(ii) a Similarly, at the exposure end time V_P4＝V_{P_RST}–V_{P_DK}＝V_{sig_d}. In the period T3, the operational amplifier enable signal OP _ EN of the dark current correlated double sampler is high, and the operational amplifier 103 is turned on in advance to prepare for operation.

It is assumed that the switch group 2041 is controlled by the switch signal SW1, the switch group 2042 is controlled by the switch signal SW2, the capacitance value of the capacitor 202 is represented by C1, the capacitance value of the capacitor 201 is represented by C2, and the capacitance value of the integrating capacitor 205 is represented by C_intThe operational amplifier is denoted by OP, where C2 is equal to the sum of 3C 1, i.e., if C1 is equal to C, then C2 is equal to 3C.

During the period T4, SW1 pulls high to turn on switch group 2041 and SW2 pulls low to turn on switch group 2042. Capacitor 201 to V_P4Sampling, amount of charge on capacitor 201: q1 ═ 3C (V)_{sig_d}-VCM); capacitor 202 pair V_P1/V_P2/V_P3Sampling and averaging, the charge amount on an equivalent capacitor formed by 3 capacitors 202 in parallel: q2 ═ 3C (V)_{sig_a}-VCM); the integrating capacitor 205 is reset and VO is VCM using the virtual short principle of OP.

In the period of T5, SW1 pulls down the closed switch group 2041, SW2 pulls up the closed switch group 2042, the lower plate of the capacitor 201 is connected to the inverting input terminal of OP, the upper plate of the capacitor 201 is connected to VCM, the upper plate of the capacitor 202 is connected to the inverting input terminal of OP, the lower plate of the capacitor 202 is connected to VCM, the charges of the capacitor 201 and the capacitor 202 are transferred to the integrating capacitor 205, and assuming that the OP gain is large enough, by using the virtual short principle of OP,

from the fact that the sum of the charge on capacitor 201 and the charge on the equivalent capacitor formed by the parallel connection of 3 capacitors 202 is equal to the charge on integrating capacitor 205, the following equation can be derived:

-C_int(VO-VCM)-C1’*(V_{sig_d}-VCM)+C2*(V_{sig_a}-VCM)＝0

wherein C1' representsThe capacitance of an equivalent capacitor formed by 3 capacitors 202 in parallel, let C be assumed_intSubstituting n × C, C1 ═ C2 ═ 3 × C into the above formula

VO＝VCM+(V_{sig_a}-V_{sig_d})*3/n＝VCM+V_{P_LI}*3/n

It should be noted that the dark current correlated double sampler of the embodiments of the present application includes, but is not limited to, applications in image sensors.

The circuit schematic diagram of the dark current correlated double sampler according to the embodiment of the present application is described in detail with reference to fig. 2 to 6, and an application example of the dark current correlated double sampler is described with reference to fig. 7. Here, fig. 7 illustrates an image sensor as an example.

As shown in fig. 7, the image sensor includes a pixel array 301, a dark current correlated double sampler 302 in the various embodiments described above, and an analog-to-digital converter 303. Wherein the pixel array 301 may include X rows and Y columns of pixel units, the number of the dark current correlated double samplers 302 may be at least one, each of the dark current correlated double samplers 302 is configured to collect n active pixels and m dark pixels in the pixel array 300 and compensate for dark currents in the n active pixels by subtracting output voltages of the m dark pixels from output voltages of the n active pixels, and the analog-to-digital converter 303 is configured to convert analog outputs of the dark current correlated double samplers 302 into digital outputs.

Optionally, the image sensor further includes a row scan controller 304 and a column scan controller 305, and the n active pixels and the m dark pixels constitute one pixel unit in the pixel array 301, that is, the pixel array may include a plurality of pixel units, and the row scan controller 304 and the column scan controller 305 are used to select one pixel unit in the pixel array 301.

The dark current is sampled twice by the dark current related double sampler and subtracted to eliminate, so that a special memory, a compensation circuit, PGA and other hardware circuits are not needed, and the hardware cost of the image sensor can be reduced.

Fig. 8 shows a schematic block diagram of a dark current compensation method 400 of an embodiment of the present application. The method 400 is performed by a dark current correlated double sampler comprising a switching circuit, n first capacitors, m second capacitors, an integrating capacitor, and an operational amplifier, wherein the sum of capacitance values of the n first capacitors is equal to the sum of capacitance values of the m second capacitors, n and m are positive integers, and the specific flow of the dark current compensation method 400 is as follows.

S401, in the first stage, under the control of the switch circuit, the n first capacitors respectively sample the output voltages of the n active pixels, and the m second capacitors respectively sample the output voltages of the m dark pixels;

s402, in the second stage, under the control of the switch circuit, the sampled charges on the n first capacitors and the sampled charges on the m second capacitors are respectively transferred to the integrating capacitor, and the output voltage of the operational amplifier is used to represent the difference between the output voltages of the n active pixels and the output voltages of the m dark pixels.

Optionally, the output voltage of the operational amplifier is used to represent a difference between an average value of the output voltages of the n active pixels and an average value of the output voltages of the m dark pixels.

The dark current compensation method according to the embodiment of the present application may correspond to each unit/module in the dark current correlated double sampler according to the embodiment of the present application, and the corresponding processes in the method may be implemented by each unit/module in the dark current correlated double sampler shown in fig. 2, fig. 4, and fig. 5, and are not described herein again for brevity.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

In addition, the terms "system" and "network" are often used interchangeably herein. It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A dark current correlated double sampler, comprising: the circuit comprises a switch circuit, n first capacitors, m second capacitors, an integrating capacitor and an operational amplifier, wherein the switch circuit comprises a first switch group and a second switch group, the first switch group comprises a first switch subgroup, a second switch subgroup, a third switch subgroup and a fourth switch subgroup, the second switch group comprises a fifth switch subgroup, a sixth switch subgroup and a seventh switch subgroup, the sum of capacitance values of the n first capacitors is equal to the sum of capacitance values of the m second capacitors, and n and m are positive integers;

the n first capacitors are connected with the output voltages of the n active pixels through the first switch subgroup of the first switch group, the n first capacitors are connected with the inverting input terminal of the operational amplifier through the sixth switch subgroup of the second switch group, the m second capacitors are connected with the output voltages of the m dark pixels through the third switch subgroup of the first switch group, the m second capacitors are connected with the inverting input terminal of the operational amplifier through the seventh switch subgroup of the second switch group, the integrating capacitor is connected in parallel with the fourth switch subgroup of the first switch group and is connected between the inverting input terminal and the output terminal of the operational amplifier, and the non-inverting input terminal of the operational amplifier is connected with the common-mode voltage.

2. The dark current correlated double sampler according to claim 1,

in a first phase, the switch circuit is used for controlling the n first capacitors and the m second capacitors to be charged, and the switch circuit is also used for controlling the integration capacitor to be discharged;

in a second phase, the switch circuit is used for controlling the n first capacitors and the m second capacitors to stop charging and controlling the n first capacitors and the m second capacitors to discharge to the integration capacitor.

3. The dark current correlated double sampler according to claim 1, wherein the ratio of the sum of the capacitance values of the n first capacitors and the sum of the capacitance values of the m second capacitors to the capacitance value of the integrating capacitor is k/p, respectively, where k is greater than or equal to p.

4. The dark current correlated double sampler of claim 1, wherein said n active pixels and said m dark pixels constitute one pixel cell in a pixel array.

5. The dark current correlated double sampler according to claim 1, wherein n is a positive integer greater than 1.

6. The dark current correlated double sampler according to claim 1, wherein one end of said n first capacitors is connected to output voltages of said n active pixels through said first switch subgroup of said first switch group and to said common mode voltage through said fifth switch subgroup of said second switch group, the other end of said n first capacitors is connected to said common mode voltage through said second switch subgroup of said first switch group and to an inverting input terminal of said operational amplifier through said sixth switch subgroup of said second switch group, one end of said m second capacitors is connected to output voltages of said m dark pixels through said third switch subgroup of said first switch group and to an inverting input terminal of said operational amplifier through said seventh switch subgroup of said second switch group, the other end of the m second capacitors is connected with the common mode voltage.

7. The dark current correlated double sampler according to claim 1, wherein one end of said n first capacitors is connected to output voltages of said n active pixels through said first switch subgroup of said first switch group and to an inverting input terminal of said operational amplifier through said sixth switch subgroup of said second switch group, the other end of the n first capacitors is connected with the common mode voltage, one end of the m second capacitors is connected with the output voltages of the m dark pixels through the third switch subgroup of the first switch group and is connected with the common mode voltage through the fifth switch subgroup of the second switch group, the other end of the m second capacitors is connected with the common mode voltage through the second switch subgroup of the first switch group and is connected with the inverting input end of the operational amplifier through the seventh switch subgroup of the second switch group.

8. The dark current correlated double sampler according to claim 6 or 7,

in a first phase, the first switch group is closed, and the second switch group is opened;

in a second phase, the first switch set is open and the second switch set is closed.

9. The dark current correlated double sampler according to claim 1, wherein any one of said n active pixels and said m dark pixels comprises a photodiode, a transfer transistor, a reset switch transistor, a source follower input transistor, and a gate switch transistor;

the photoelectric conversion device comprises a photoelectric diode, a transmission tube, a source follow input tube, a gate switch tube, a reset switch tube and a source follow input tube, wherein light with different intensities generates different amounts of charges in the photoelectric diode, the generated charges are converted into voltages under the transmission of the transmission tube, the converted voltages are output to the first capacitor or the second capacitor through the source follow input tube and the gate switch tube, and the reset switch tube is used for resetting the photoelectric diode.

10. The dark current correlated double sampler according to claim 9, wherein said any pixel further comprises a parasitic capacitor;

the positive electrode of the photodiode is grounded, the negative electrode of the photodiode is connected with the source electrode of the transmission tube, the grid electrode of the transmission tube is controlled by a transmission signal, the drain electrode of the transmission tube is respectively connected with one end of the parasitic capacitor, the grid electrode of the source following input tube and the source electrode of the reset switch tube, the other end of the parasitic capacitor is grounded, the drain electrode of the reset switch tube is connected with a reset voltage, the grid electrode of the reset switch tube is controlled by the reset signal, the source electrode of the source following input tube is connected with the drain electrode of the gating switch tube, the drain electrode of the source following input tube is connected with a power voltage, the grid electrode of the gating switch tube is controlled by the gating signal, and the source electrode of the gating switch tube outputs the output voltage of the corresponding pixel.

11. Dark current correlated double sampler according to claim 9 or 10,

in a third phase, the reset switch tubes and the transmission tubes of all the n active pixels and the m dark pixels are conducted, and the photodiodes of all the pixels are reset to a reset voltage;

in the fourth stage, the reset switch tubes and the transmission tubes of all the pixels are closed, and all the pixels start to be exposed.

12. An image sensor comprising a pixel array comprising the n active pixels and the m dark pixels, a dark current dependent double sampler as claimed in any one of claims 1 to 11, and an analog-to-digital converter for converting the analog output of the dark current dependent double sampler to a digital output.

13. The image sensor of claim 12, wherein the n active pixels and the m dark pixels form one pixel unit in the pixel array, the image sensor further comprising a row scan controller and a column scan controller for selecting the one pixel unit.

14. A dark current compensation method, performed by a dark current dependent double sampler comprising a switching circuit, n first capacitors, m second capacitors, an integrating capacitor and an operational amplifier, wherein the switching circuit comprises a first switch group and a second switch group, the first switch group comprises a first switch subgroup, a second switch subgroup, a third switch subgroup and a fourth switch subgroup, the second switch group comprises a fifth switch subgroup, a sixth switch subgroup and a seventh switch subgroup, a sum of capacitance values of the n first capacitors is equal to a sum of capacitance values of the m second capacitors, n and m are positive integers, the n first capacitors are connected to output voltages of n active pixels through the first switch subgroup of the first switch group, and the n first capacitors are connected to the operational amplifier through the sixth switch subgroup of the second switch group An inverting input of the amplifier, the m second capacitors being coupled to the output voltages of the m dark pixels through the third subset of switches of the first set of switches, the m second capacitors being coupled to the inverting input of the operational amplifier through a seventh subset of switches of the second set of switches, the integrating capacitor being coupled in parallel with the fourth subset of switches of the first set of switches and between the inverting input and the output of the operational amplifier, a non-inverting input of the operational amplifier being coupled to a common mode voltage, the method comprising:

in a first stage, under the control of the switch circuit, the n first capacitors respectively sample the output voltages of the n active pixels, and the m second capacitors respectively sample the output voltages of the m dark pixels;

in the second stage, under the control of the switch circuit, the sampled charges on the n first capacitors and the sampled charges on the m second capacitors are respectively transferred to the integrating capacitor, and the output voltage of the operational amplifier is used for representing the difference value between the output voltage of the n active pixels and the output voltage of the m dark pixels.

15. The dark current compensation method according to claim 14, wherein a ratio of a sum of the capacitance values of the n first capacitors and a sum of the capacitance values of the m second capacitors to the capacitance value of the integration capacitor is k/p, respectively, wherein k is greater than or equal to p.

16. The dark current compensation method according to claim 14 or 15, wherein the n active pixels and the m dark pixels constitute one pixel unit in a pixel array.