CN113533815A - Multi-channel sampling synchronization method based on time stamps - Google Patents

Abstract

The invention discloses a multi-channel sampling synchronization method based on timestamps, which comprises the steps of firstly carrying out multi-ADC data synchronization and then carrying out multi-channel sampling synchronization; when the data of the multiple ADCs are synchronous, the FPGA sends synchronous pulses to the clock manager in three times to respectively complete clock synchronization, data transmission link establishment and timestamp marking, then the FPGA receives serial channel data streams sent by the multiple ADCs and converts the serial channel data streams into parallel data by using the gigabit transceiver, then the parallel data of each channel is subjected to sequence modulation and dynamic delay increasing, and finally a final user data stream is formed; when multi-channel sampling is synchronous, the ADC time sequence is adjusted, and then the delay between channels is measured and corrected.

Description

Multi-channel sampling synchronization method based on time stamps

Technical Field

The invention belongs to the technical field of digital oscilloscopes, and particularly relates to a multi-channel sampling synchronization method based on a timestamp.

Background

With the continuous improvement of the scientific research level, the demand of people on the oscillograph with high sampling rate is continuously increased. In nuclear energy spectrum measurement, the sampling rate required for identifying gamma-ray pulses is at least greater than 15MSPS, when surge current on a power supply transmission line is observed, the duration of the surge is only hundreds of nanoseconds, the time precision of micro-pulse signals of a high-energy accelerator is hundreds of picoseconds, and the signals can be completely recorded only by a data acquisition system with high speed in a plurality of scientific research scenes. Therefore, high-performance oscilloscopes or data acquisition systems are gradually beginning to use new GSPSADCs (analog-to-digital converters), and the ADCs are characterized in that the original parallel LVDS interface is evolved into a serial JESD204B interface. The JESD204B interface has several benefits over a parallel LVDS interface: greater throughput, fewer transmission lines, smaller device packages, etc. However, when a high-speed data acquisition system is constructed by using multiple ADCs, data synchronization of the multiple ADCs also becomes a difficult problem.

The existing solution is to utilize the deterministic delay characteristics of the JESD204B protocol to achieve multi-slice synchronization. The JESD204B protocol divides two boundaries for a continuous stream of data: frame, multiframe, where the boundaries of the multiframe clock are determined by LMFC (local multiframe clock). At initialization, all lanes of the sender send ILAS (initial lane alignment sequence) and all lanes of the receiver receive ILAS, and each lane contains an elastic buffer, as long as all lanes of the receiver receive in the same multi-frame boundary

The ILAS simultaneously releases the elastic buffer to enable lane data alignment. However, in an actual system, ILAS of each channel often crosses a multi-frame clock boundary, and for this purpose, DTXLFMC (delay from SYSREF valid edge to receiving LMFC) and DRXLMFC (delay from SYSREF valid edge to sending LMFC) need to be adjusted so that ILAS of each channel arrives at the same LMFC.

The above method has three problems: 1. adjusting DTXLMFC and DRXLMFC requires maximum routing delay, minimum routing delay, transmit-end output delay, and receive-end input delay, which are difficult to obtain under normal conditions. 2. For applications such as radar systems, which require the use of thousands of transducers, the computational difficulty rises straight. 3. For applications requiring clock phase adjustments that disrupt the timing relationship between the SYSREF signal and the device clock, deterministic delays may present uncertainties. 4. The JESD204B data transfer link can only be aligned, and the analog channel cannot be aligned and desynchronized by the sample clock skew.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a multi-channel sampling synchronization method based on time stamps, which can align a plurality of JESD204B high-speed serial data links and reduce inter-channel delay caused by sampling clock skew, analog channel inconsistency and the like without additional hardware overhead.

In order to achieve the above object, the present invention provides a multi-channel sampling synchronization method based on time stamps, which is characterized by comprising the following steps:

(1) data synchronization of multiple ADCs;

(1.1) generating a low-frequency source clock signal by using a crystal oscillator and sending the low-frequency source clock signal to a clock manager of a double phase-locked loop;

(1.2) the FPGA carries out register initialization configuration on the clock manager through an SPI communication protocol; after the initialization configuration is completed, the clock manager performs two-stage locking and amplification on a low-frequency source clock signal, and then generates a multi-path sampling clock SCLK and a multi-path reference clock REFCLK through an internal clock distribution network, wherein the number of the SCLK and the REFCLK corresponds to the number of ADCs used by the system, the SCLK is sent to each ADC, and the REFCLK is sent to the FPGA;

(1.3) each ADC samples the input analog signal under the drive of SCLK, and converts the analog signal into sampling point data of M bits; then, adding W bits of redundant control bits for sampling point data of M bits by a serial channel mapping unit in the ADC to form serial channel data of M + W bits, wherein the value of the redundant control bits is 0 under the default condition;

(1.4) sending a synchronous pulse to a clock manager by the FPGA for three times, and respectively completing clock synchronization, data transmission link establishment and timestamp marking;

after the synchronous pulse sent by the FPFA for the first time is sent to the clock manager, the clock distribution network in the clock manager carries out reset operation, so that the phases of the multiple paths of sampling clocks SCLK are aligned, and the phases of the multiple paths of reference clocks REFCLK are aligned; then, the FPGA sends an SPI command to the clock manager, on one hand, the response of the clock distribution network to the synchronous pulse is shielded, and on the other hand, the response of the pulse distribution network to the synchronous pulse is opened; meanwhile, the FPGA also sends an SPI command to the ADC, the default register data of the ADC is rewritten, the default multi-frame clock alignment function in the ADC is forbidden, and the timestamp function is turned on;

after the synchronous pulse sent by the FPFA for the second time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation to generate a reference pulse SYSREF of the system, and the reference pulse SYSREF is respectively fed back to the FPGA and all the ADCs; after receiving the reference pulse SYSREF, the gigabit transceiver module in the FPGA raises SYNCB signals sent to each ADC by the FPGA, and after receiving the raised SYNCB signals, the ADC starts to transmit serial channel data streams to the FPGA;

after the synchronous pulse sent by the FPFA for the third time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation again, generates the reference pulse SYSREF of the system for the second time and feeds back the reference pulse SYSREF to the FPGA and all the ADCs respectively; after the ADC receives the reference pulse SYSREF, marking the first sampling point data after the rising edge moment of the reference pulse SYSREF, and keeping a certain position 1 and the rest positions 0 in the redundant control position of the serial channel data corresponding to the first sampling point data to finish time stamp marking;

(1.5) the FPGA receives serial channel data streams sent by a plurality of ADCs (analog to digital converters) by using a gigabit transceiver, deserializes the serial channel data streams of each channel, reduces the speed and increases the bit width by using a high-speed serial technology, converts the serial channel data streams into K paths of parallel data, and extracts a data clock DCLK (data clock) of the parallel data streams by using a clock recovery technology;

(1.6) carrying out sequence adjustment on the K paths of parallel data of each channel: detecting the position of a timestamp mark appearing in parallel data, and marking the position as L, wherein L is more than or equal to 1 and less than or equal to K; delaying the 1 st path to the L-1 st path of the original parallel data by two DCLK periods, and delaying the L path to the Kth path of the original parallel data by one DCLK period to form delayed parallel data; finally, rearranging the delayed parallel data in sequence from the L-th path to the K-th path and from the 1 st path to the L-1 st path to form the parallel data after sequence adjustment;

(1.7) respectively adding dynamic delay to the parallel data after each channel is sequenced by using a plurality of FIFOs, and starting the write enable of the FIFO of the corresponding channel when the parallel data after a certain channel is sequenced is detected to contain a timestamp marking bit '1'; when the parallel data after all the channels are sequenced are detected to contain a timestamp flag bit '1', starting the read enable of the FIFO of all the channels, keeping the write enable on, keeping the read and write balanced, and dynamically increasing the delay of the parallel data of each channel to form a final user data stream;

(2) multi-channel sampling synchronization;

(2.1) adjusting ADC time sequence;

reading back data of an internal register of the ADC through an SPI communication protocol, monitoring a SYSREF setup/hold time window register of the ADC, if a read-back value of the register is 1, indicating a time sequence violation, namely, an effective edge of the SYSREF appears in a window of an effective edge of an SCLK, the SYSREF does not meet a time sequence condition of the SCLK, and at the moment, gradually increasing a corresponding SYSREF delay value sent to the ADC until the time sequence violation is not displayed after reinitialization, namely, the read-back value is 0;

(2.2) measuring the delay between channels;

(2.2.1) selecting one channel as a reference channel, and taking the other channels as channels to be detected;

(2.2.2) outputting a sine signal with a known frequency by a signal source, and inputting the sine signal to a reference channel and a channel to be tested through a power divider and an isometric transmission line;

(2.2.3) collecting user data collected by the reference channel and the channel to be tested in the same time period by using an FPGA debugging tool ILA;

(2.2.4) calculating the phase difference of the collected user data, and recording the phase difference as theta;

(2.2.5) calculating the inter-channel delay delta t of the channel to be measured relative to the reference channel;

wherein f is the frequency of the input sinusoidal signal;

(2.3) correcting the interchannel delay;

increasing the SCLK delay and the SYSREF delay of the channel to be detected step by step to enable the increased delay amount to be as close to the inter-channel delay value delta t as possible until the absolute value of the difference between the increased delay amount and the measured inter-channel delay value is smaller than the adjustable minimum step of the clock chip delay;

and (2.4) repeating the steps (2.1) to (2.3) until the interchannel delay correction of all the channels is completed.

The invention aims to realize the following steps:

the invention relates to a multi-channel sampling synchronization method based on a timestamp, which comprises the steps of firstly carrying out multi-ADC data synchronization and then carrying out multi-channel sampling synchronization; when the data of the multiple ADCs are synchronous, the FPGA sends synchronous pulses to the clock manager in three times to respectively complete clock synchronization, data transmission link establishment and timestamp marking, then the FPGA receives serial channel data streams sent by the multiple ADCs and converts the serial channel data streams into parallel data by using the gigabit transceiver, then the parallel data of each channel is subjected to sequence modulation and dynamic delay increasing, and finally a final user data stream is formed; when multi-channel sampling is synchronous, the ADC time sequence is adjusted, and then the delay between channels is measured and corrected.

Meanwhile, the multi-channel sampling synchronization method based on the time stamp also has the following beneficial effects:

(1) alignment of multiple JESD204B high-speed serial data links can be achieved without additional hardware overhead by deploying a time stamp function under the JESD204B framework;

(2) compared with the traditional method for realizing multi-chip synchronization by using the deterministic delay characteristic of the JESD204B protocol, the multi-channel sampling synchronization method based on the time stamp breaks through the limitation that only the JESD204B data transmission link can be aligned, and the analog channel cannot be aligned and the asynchronization caused by the skew of the sampling clock can be eliminated;

(3) in the multi-ADC data synchronization, a parallel data sequence adjusting technology and a dynamic delay increasing technology are used, and the synchronization of the waveform data storage and transmission of the multi-submodule is efficiently realized.

(4) In the multichannel sampling synchronization, a time window register is established/maintained by monitoring SYSREF of the ADC, and a SYSREF signal delay value sent to the ADC is dynamically increased, so that a time sequence violation does not occur between a SYSREF signal and an ADC clock signal, and the problems that the time sequence relation between the SYSREF signal and a device clock is damaged and the deterministic delay may be uncertain in the conventional method when the clock phase is adjusted are solved.

Drawings

FIG. 1 is an architecture diagram of one embodiment of a timestamp based multi-channel sampling synchronization system of the present invention;

FIG. 2 is a block diagram of one embodiment of a clock manager;

FIG. 3 is a schematic diagram of the structure of serial channel data;

FIG. 4 is a schematic illustration of a sample point timestamping;

FIG. 5 is a schematic diagram of sample point sequence adjustment;

FIG. 6 is a schematic diagram of adding dynamic delay using a FIFO;

FIG. 7 is a flow chart of data within an FPGA;

FIG. 8 is a schematic diagram of monitoring SYSREF valid edge timing violations via registers;

Detailed Description

The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.

Examples

FIG. 1 is an architecture diagram of one embodiment of the present invention for a timestamp based multi-channel sampling synchronization system.

In this embodiment, the multi-channel sampling synchronization method based on the timestamp mainly includes two steps of multi-ADC data synchronization and multi-channel sampling synchronization, and each step is described in detail below, specifically as follows:

s1, synchronizing data of multiple ADCs;

in this embodiment, as shown in fig. 1, we sample 4 channels of analog signals and transmit the sampled data to the FPGA by using 4 pieces of ADCs with a sampling rate of 12bits (JESD204B interface) of 2.5GSPS, and then the specific process of data synchronization of the 4 pieces of ADCs is as follows:

s1.1, as shown in figure 2, generating a low-frequency source clock signal by using a crystal oscillator and sending the low-frequency source clock signal to a clock chip of a double phase-locked loop;

s1.2, the FPGA carries out register initialization configuration on a clock manager through an SPI communication protocol; after the initialization configuration is completed, the clock manager performs two-stage locking and amplification on a low-frequency source clock signal, and generates a 4-path sampling clock SCLK and a 4-path reference clock REFCLK through an internal clock distribution network, wherein the SCLK is sent to each ADC, and the REFCLK is sent to the FPGA;

s1.3, each ADC samples an input analog signal under the drive of SCLK, and the analog signal is converted into 12-bit sampling point data; then, adding 4-bit redundant control bits to 12-bit sampling point data through a serial channel mapping unit inside the ADC to form 16-bit serial channel data, as shown in fig. 3, where the value of the redundant control bits is 0 in a default condition;

s1.4, the FPGA sends a synchronization pulse to a clock manager for three times to respectively complete clock synchronization, data transmission link establishment and timestamp marking;

after the synchronous pulse sent by the FPFA for the first time is sent to the clock manager, the clock distribution network in the clock manager carries out reset operation, so that the phases of the 4 paths of sampling clocks SCLK are aligned, and the phases of the 4 paths of reference clocks REFCLK are aligned; then, the FPGA sends an SPI command to the clock manager, on one hand, the response of the clock distribution network to the synchronous pulse is shielded, and on the other hand, the response of the pulse distribution network to the synchronous pulse is opened; meanwhile, the FPGA also sends an SPI command to the ADC, the default register data of the ADC is rewritten, the default multi-frame clock alignment function in the ADC is forbidden, and the timestamp function is turned on;

after the synchronous pulse sent by the FPFA for the second time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation to generate a reference pulse SYSREF of the system, and the reference pulse SYSREF is respectively fed back to the FPGA and all the ADCs; after receiving the reference pulse SYSREF, the gigabit transceiver module in the FPGA raises SYNCB signals sent to each ADC by the FPGA, and after receiving the raised SYNCB signals, the ADC starts to transmit serial channel data streams to the FPGA;

after the synchronous pulse sent by the FPFA for the third time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation again, generates the reference pulse SYSREF of the system for the second time and feeds back the reference pulse SYSREF to the FPGA and all the ADCs respectively; after the ADC receives the reference pulse SYSREF, marking the first sampling point data after the rising edge moment of the reference pulse SYSREF, and keeping a certain position 1 and the rest positions 0 in the redundant control position of the serial channel data corresponding to the first sampling point data to finish time stamp marking; in this embodiment, the process of the ADC marking bits for adding the timestamp is as shown in fig. 4, when a transition of the SYSREF signal from a low level to a high level is detected, marking the first sampling point data after the rising edge time of the reference pulse SYSREF, and setting the highest position 1 in the 4 control bits, which is 0 at any other time;

s1.5, the FPGA receives serial channel data streams sent by 4 ADCs (analog to digital converters) by using a gigabit transceiver, deserializes the serial channel data streams of each channel, reduces the speed and increases the bit width by using a high-speed serial technology, converts the serial channel data streams into 8 paths of parallel data, and extracts a data clock DCLK (data clock) of the parallel data streams by using a clock recovery technology;

s1.6, sequencing 8 paths of parallel data of each channel: detecting the position of a timestamp mark appearing in parallel data, marking as L, wherein L is more than or equal to 1 and less than or equal to 8; delaying the 1 st path to the L-1 st path of the original parallel data by two DCLK periods, and delaying the L path to the 8 th path of the original parallel data by one DCLK period to form delayed parallel data; finally, rearranging the delayed parallel data in sequence from the L-th path to the 8-th path and from the 1-st path to the L-1 st path to form the parallel data after sequence adjustment;

because of the limitation of the clock rate of the FPGA, the sampling data of the ADC must be received and transmitted by reducing the clock rate and increasing the bit width, the data bit width of the single-chip ADC of the system is 12bits, the clock rate is up to 2.5GHz, the clock rate can be reduced to 312.5MHz after passing through the FPGA deserializer, the bit width can be correspondingly increased to 96bits, which means that in the FPGA, one data clock period is aligned to 8 sampling points, and the sampling point carrying the timestamp marker can be any one path in 8 paths of data, so the sequence of each path of data stream is firstly adjusted, and the sampling point carrying the timestamp marker is fixed on the first path in 8 paths of data.

As shown in fig. 5, the sampling point sequence adjustment is started after the Timestamp (Timestamp mark signal) is detected to be high, the sampling point (D4) carrying the Timestamp mark is moved to the position of the original first sampling point, the positions of the remaining 7 sampling points are filled with 3 sampling points (D5, D6, D7) after D4 and 4 sampling points (D8, D9, D10, D10) before the next clock cycle in the same clock cycle, and at this time, the data is effectively enabled to be pulled high.

S1.7, respectively adding dynamic delay to the parallel data after each channel is sequenced by using a plurality of FIFOs, and starting the write enable of the FIFO of the corresponding channel when the parallel data after one channel is sequenced is detected to contain a timestamp marking bit '1'; when the parallel data after all the channels are sequenced are detected to contain a timestamp flag bit '1', starting the read enable of the FIFO of all the channels, keeping the write enable on, keeping the read and write balanced, and dynamically increasing the delay of the parallel data of each channel to form a final user data stream;

in this embodiment, after the order of the data streams is adjusted, there is a phase difference of an integer multiple of clock cycles between the channel data, that is: Δ T ± N × 3.2ns, N ═ 1,2,3, …; to do this, we can send the sequentially adjusted data stream to a FIFO array, one FIFO for each piece of ADC data. The write bit width and the read bit width of the FIFO are kept consistent and are both 96 bits. The write enable of the FIFO is data valid enable; when it is detected that all the FIFOs have data written therein, the read enable is turned on together with all the FIFOs, the write enable is also turned off, and the FIFOs keep a read-write balanced state of reading while writing, so that corresponding delay is added to the fast path data and the slow path data are kept aligned, and a process of adding dynamic delay to the fast path data through the FIFOs is shown in fig. 6; the above-mentioned FPGA flowchart for adjusting the sequence and increasing the dynamic delay is shown in fig. 7, and the timestamp synchronization mechanism is configured up to this point.

S2, multi-channel sampling synchronization;

s2.1, adjusting the ADC time sequence;

reading back data of an internal register of the ADC through an SPI communication protocol, monitoring a SYSREF setup/hold time window register of the ADC, if a read-back value of the register is 1, indicating a time sequence violation, namely, an effective edge of the SYSREF appears in a window of an effective edge of an SCLK, the SYSREF does not meet a time sequence condition of the SCLK, and at the moment, gradually increasing a corresponding SYSREF delay value sent to the ADC until the time sequence violation is not displayed after reinitialization, namely, the read-back value is 0;

s2.2, measuring the delay between channels;

s2.2.1, selecting one channel as a reference channel and the other channels as channels to be detected;

s2.2.2, outputting a sine signal with a known frequency by a signal source, and inputting the sine signal to a reference channel and a channel to be measured by a power divider and an isometric transmission line;

s2.2.3, collecting user data acquired by the reference channel and the channel to be detected in the same time period by using an FPGA debugging tool ILA;

s2.2.4, calculating the phase difference of the collected user data, and recording as theta;

s2.2.5, calculating the inter-channel delay delta t of the channel to be measured relative to the reference channel;

wherein f is the frequency of the input sinusoidal signal;

s2.3, correcting the delay among the channels;

increasing the SCLK delay and the SYSREF delay of the channel to be detected step by step to enable the increased delay amount to be as close to the interchannel delay value delta t measured in the step S2.2 as possible until the difference between the increased delay amount and the absolute value of the measured interchannel delay value is smaller than the adjustable minimum step of the clock chip delay;

and S2.4, repeating the step S2.1 to the step S2.3 until the inter-channel delay correction of all the channels is completed.

In this embodiment, the inter-channel delay values of the multiple ADCs may be divided into a fixed portion and a random portion. The random delay is derived from a metastable state phenomenon caused by timing violation of a SYSREF signal and a device clock, and the metastable state elimination of the random delay can be avoided by adjusting the phase relationship of the SYSREF signal and the device clock; the fixed delay, which results from the data transmission path disparity, can be reduced to less than a programmable delay value by a previously deployed time stamping mechanism in conjunction with delay adjustment as will be described below.

As shown in fig. 7, the ADC used in the embodiment of the present invention includes a SYSREF setup time and hold time monitor register, and if the valid edge of SYSREF appears in the window of the CLK valid edge, the register read value will be 1, so as to warn the user that the SYSREF does not satisfy the timing condition of CLK, and the window width may be increased to leave more margin. After the clock manager provides a stable clock for the ADC, sending a SYSREF pulse signal, and reading back the register value, wherein if the value is 0, no adjustment is needed; if it is 1, the delay value of the corresponding SYSREF pulse is increased, and the above process is repeated until the read-back value becomes 0. For this embodiment, a sampling clock period is 400ps, and the programmable delay value of the clock manager output channel is 25ps, which can be adjusted to step from 0 to 23, so that a proper value can be always found so that the valid edge of SYSREF does not fall within the timing violation window of CLK. Finally, it is noted that all ADCs must do this.

And then determining a reference channel, wherein the other channels are to-be-detected channels, and inputting the same signal to measure the phase difference between the reference channel and the to-be-detected channel. The signal is obtained by dividing a signal source into two parts through a power divider and is connected to a system through equal-length transmission lines; the method of phase difference measurement may employ cross-correlation phase difference measurement, three-parameter sine fitting, or other signal phase difference measurement algorithms, which are not discussed in detail herein. The result of the calculation may be represented by the following sub-formula: Δ T ═ a × T + C × D + M;

where Δ T is the calculated interchannel delay, T is the sampling clock period, D is the clock manager programmable delay value, A and C are integers greater than or equal to 0, and m is the delay portion less than D. The meaning of this equation is to divide the interchannel delay value into a clock cycles, C adjustable minimum steps and the remaining unadjustable delay m parts. Taking the embodiment of the present invention as an example, if T is 400ps and D is 25ps, and if Δ T is measured to be 736ps, Δ T can be decomposed as: Δ t-736 ps-1-400 ps + 13-25 ps +11 ps; delaying the SYSREF signal for the late channel by a number of T delay values (using a digital delay channel different from D), the late signal data can be advanced by a clock cycles, because the sysrf signal moves by an integer number of clock cycles, no new timing violations are generated; the SYSREF signal and the CLK signal for the lagging channel are delayed by C delay values (not for the model delay channel of T) at the same time, and the lagging data can be advanced by C by D time values. Through the above decomposition, m is always smaller than D, i.e. 25ps for the present embodiment.

Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims (1)

1. A multi-channel sampling synchronization method based on time stamps is characterized by comprising the following steps:

(1) data synchronization of multiple ADCs;

(1.1) generating a low-frequency source clock signal by using a crystal oscillator and sending the low-frequency source clock signal to a clock manager of a double phase-locked loop;

(1.2) the FPGA carries out register initialization configuration on the clock manager through an SPI communication protocol; after the initialization configuration is completed, the clock manager performs two-stage locking and amplification on a low-frequency source clock signal, and then generates a multi-path sampling clock SCLK and a multi-path reference clock REFCLK through an internal clock distribution network, wherein the number of the SCLK and the REFCLK corresponds to the number of ADCs used by the system, the SCLK is sent to each ADC, and the REFCLK is sent to the FPGA;

(1.3) each ADC samples the input analog signal under the drive of SCLK, and converts the analog signal into sampling point data of M bits; then, adding W bits of redundant control bits for sampling point data of M bits by a serial channel mapping unit in the ADC to form serial channel data of M + W bits, wherein the value of the redundant control bits is 0 under the default condition;

(1.4) sending a synchronous pulse to a clock manager by the FPGA for three times, and respectively completing clock synchronization, data transmission link establishment and timestamp marking;

after the synchronous pulse sent by the FPFA for the first time is sent to the clock manager, the clock distribution network in the clock manager carries out reset operation, so that the phases of the multiple paths of sampling clocks SCLK are aligned, and the phases of the multiple paths of reference clocks REFCLK are aligned; then, the FPGA sends an SPI command to the clock manager, on one hand, the response of the clock distribution network to the synchronous pulse is shielded, and on the other hand, the response of the pulse distribution network to the synchronous pulse is opened; meanwhile, the FPGA also sends an SPI command to the ADC, the default register data of the ADC is rewritten, the default multi-frame clock alignment function in the ADC is disabled, and the timestamp opening function is turned on;

after the synchronous pulse sent by the FPFA for the second time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation to generate a reference pulse SYSREF of the system, and the reference pulse SYSREF is respectively fed back to the FPGA and all the ADCs; after receiving the reference pulse SYSREF, the gigabit transceiver module in the FPGA raises SYNCB signals sent to each ADC by the FPGA, and after receiving the raised SYNCB signals, the ADC starts to transmit serial channel data streams to the FPGA;

after the synchronous pulse sent by the FPFA for the third time is sent to the clock manager, the pulse distribution network in the clock manager carries out reset operation again, generates the reference pulse SYSREF of the system for the second time and feeds back the reference pulse SYSREF to the FPGA and all the ADCs respectively; after the ADC receives the reference pulse SYSREF, marking the first sampling point data after the rising edge moment of the reference pulse SYSREF, and keeping a certain position 1 and the rest positions 0 in the redundant control position of the serial channel data corresponding to the first sampling point data to finish time stamp marking;

(1.5) the FPGA receives serial channel data streams sent by a plurality of ADCs (analog to digital converters) by using a gigabit transceiver, deserializes the serial channel data streams of each channel, reduces the speed and increases the bit width by using a high-speed serial technology, converts the serial channel data streams into K paths of parallel data, and extracts a data clock DCLK (data clock) of the parallel data streams by using a clock recovery technology;

(1.6) carrying out sequence adjustment on the K paths of parallel data of each channel: detecting the position of a timestamp mark appearing in parallel data, and marking the position as L, wherein L is more than or equal to 1 and less than or equal to K; delaying the 1 st path to the L-1 st path of the original parallel data by two DCLK periods, and delaying the L path to the Kth path of the original parallel data by one DCLK period to form delayed parallel data; finally, rearranging the delayed parallel data in sequence from the L-th path to the K-th path and from the 1 st path to the L-1 st path to form the parallel data after sequence adjustment;

(1.7) respectively adding dynamic delay to the parallel data after each channel is sequenced by using a plurality of FIFOs, and starting the write enable of the FIFO of the corresponding channel when the parallel data after a certain channel is sequenced is detected to contain a timestamp marking bit '1'; when the parallel data after all the channels are sequenced are detected to contain a timestamp flag bit '1', starting the read enable of the FIFO of all the channels, keeping the write enable on, keeping the read and write balanced, and dynamically increasing the delay of the parallel data of each channel to form a final user data stream;

(2) multi-channel sampling synchronization;

(2.1) adjusting ADC time sequence;

reading back data of an internal register of the ADC through an SPI communication protocol, monitoring a SYSREF setup/hold time window register of the ADC, if a read-back value of the register is 1, indicating a time sequence violation, namely, an effective edge of the SYSREF appears in a window of an effective edge of an SCLK, the SYSREF does not meet a time sequence condition of the SCLK, and at the moment, gradually increasing a corresponding SYSREF delay value sent to the ADC until the time sequence violation is not displayed after reinitialization, namely, the read-back value is 0;

(2.2) measuring the delay between channels;

(2.2.1) selecting one channel as a reference channel, and taking the other channels as channels to be detected;

(2.2.2) outputting a sine signal with a known frequency by a signal source, and inputting the sine signal into a reference channel and a channel to be tested through a power divider and an isometric transmission line;

(2.2.3) collecting user data collected by the reference channel and the channel to be tested in the same time period by using an FPGA debugging tool ILA;

(2.2.4) calculating the phase difference of the collected user data, and recording the phase difference as theta;

(2.2.5) calculating the inter-channel delay delta t of the channel to be measured relative to the reference channel;

wherein f is the frequency of the input sinusoidal signal;

(2.3) correcting the interchannel delay;

increasing the SCLK delay and the SYSREF delay of the channel to be detected step by step to enable the increased delay amount to be as close to the interchannel delay value delta t as possible until the absolute value of the difference between the increased delay amount and the measured interchannel delay value is smaller than the adjustable minimum step of the clock manager delay;

and (2.4) repeating the steps (2.1) to (2.3) until the interchannel delay correction of all the channels is completed.

Images