CN116455394B - Multichannel ADC synchronization device and automatic synchronization method - Google Patents
Multichannel ADC synchronization device and automatic synchronization method Download PDFInfo
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Abstract
The invention discloses a multichannel ADC synchronization device and an automatic synchronization method, comprising a clock synchronization plate and at least two data acquisition plates connected with the clock synchronization plate, wherein the data acquisition plates comprise at least two ADC chips and an FPGA connected with the ADC chips; the clock synchronization board provides synchronous clocks and sampling clocks with consistent phases for the data acquisition board, the clock synchronization board provides RCLK and MCLK for the ADC chips, PCLK is provided for the FPGA, all the FPGA respectively use DCLK at the same position of the data acquisition board as clocks for sampling standard test sequences, each FPGA performs data acquisition on all LVDS links on the data acquisition board at the same time, and data of the data channels are automatically trained by using the standard test sequences generated by the synchronous clocks and the ADC chips, so that delay values from sampling points of the ADC chips to data output of the FPGA are the same, and after phase synchronization among the ADC chips connected by the FPGA is completed, the phase synchronization of the ADC chips among the boards is performed.
Description
Technical Field
The invention relates to the technical field of high-speed data acquisition, in particular to a multichannel ADC (analog to digital converter) synchronization device and an automatic synchronization method.
Background
The development of radar, satellite communication, 5G communication, MIMO radar technology requires that more and more wireless devices employ phased array systems. The phased array system consists of a plurality of receiving and transmitting components, and is used for acquiring the signal synchronization of the receiving channels required by the optimal performance, namely, the delay values of all data channels from the time when the required signals enter the ADC to the time when the FPGA outputs are kept consistent, namely, all ADC channels input the same signal, and the phases of all channels at the time when the FPGA outputs are the same value.
The existing multichannel ADC synchronization technical scheme mainly comprises the following three steps:
the first method (such as a multi-channel ADC synchronous sampling intermediate frequency receiver and a synchronous sampling method) is to not provide any synchronous signal to the ADC, input the same signal at all ADC input terminals, store the data of all ADC data channels at the same time by the FPGA and calculate the phase difference between the data channel signals, and then convert the phase difference of all data channels into a delay value to store in the nonvolatile memory.
The second method (such as a synchronization method and device of multiple high-speed ADC chips) is to send a synchronization pulse to all ADCs, and after receiving the pulse, the ADC realizes the output synchronization of the sampling points of the ADC itself; the same signal is input to all ADC input ends, the FPGA stores the data of all ADC data channels at the same time, calculates the phase difference between the data channel signals, and then converts the phase difference of all the data channels into a delay value to be stored in a nonvolatile memory.
Thirdly (such as a multichannel high-speed AD synchronous acquisition device and method) provides synchronous clocks for all ADCs, and the ADCs realize self sampling point output synchronization of the ADCs after receiving the synchronous clocks; the same signal is input to all ADC input ends, the FPGA stores the data of all ADC data channels at the same time, calculates the phase difference between the data channel signals, and then converts the phase difference of all the data channels into a delay value to be stored in a nonvolatile memory.
In the prior art, the first scheme needs to fill a low-frequency sine wave into the input end of an ADC, collect and store data of each ADC channel by using an FPGA, and calculate the phase difference between the channels; as the number of ADC channels increases, the number of ADC input channel cables that need to be manually replaced will increase, and the data stored in the ADC channels will also increase, resulting in a large amount of manual work.
The second scheme is more than the first scheme by one synchronous pulse, realizes the output synchronization of sampling points of the ADC, reduces the phase difference between channels of the ADC chip, still needs to fill a low-frequency sine wave into the input end of the ADC, uses an FPGA to collect and store the data of each ADC channel, and calculates the phase difference between the channels.
The third scheme is more than the first two schemes by one synchronous clock, can synchronize the sampling points of the ADC per synchronous clock period, can still recover the synchronization after being interfered by the outside, but still needs to fill a low-frequency sine wave into the input end of the ADC, collect and store the data of each ADC channel by using the FPGA, and calculate the phase difference between channels.
Disclosure of Invention
The invention aims to provide a multichannel ADC synchronization device and an automatic synchronization method, wherein the synchronization device utilizes a synchronization clock and a standard test sequence generated by an ADC chip to automatically train data of data channels, so that delay values from sampling points of the ADC chip to data output of an FPGA are the same; therefore, the automatic synchronization of the phase between channels can be realized without filling signals into the input ends of the ADC chips, and the method is suitable for the synchronization of a plurality of ADC chips in a board and the synchronization of a plurality of ADC chips between boards. According to the method, the synchronous clock and the standard test sequence generated by the ADC chips are utilized to automatically train the data of the data channels, so that the delay values from the sampling points of the ADC chips to the data output of the FPGA are the same, channel data synchronization of all the ADC chips connected with a single FPGA is finished, and after phase synchronization among the ADC chips connected with the FPGA is finished, phase synchronization of the ADC chips among boards is carried out.
The invention is realized by the following technical scheme: the multichannel ADC synchronization device comprises a clock synchronization plate and at least two data acquisition plates connected with the clock synchronization plate, wherein each data acquisition plate comprises at least two ADC chips and an FPGA connected with the ADC chips; the clock synchronizing plate provides a synchronous clock and a sampling clock with consistent phases for the data acquisition plate.
Further, in order to better realize the multichannel ADC synchronization device of the present invention, the following arrangement structure is adopted: the clock synchronization board outputs equal length to all ADC chip synchronization clocks RCLK, the clock synchronization board outputs equal length to all ADC chip sampling clocks MCLK, the TRIG_OUT of the clock synchronization board is equal length to all FPGA lines, and the line delay from the data processing clock PCLK of the clock synchronization board to all FPGA lines is not more than one data processing clock PCLK period.
Further, in order to better realize the multichannel ADC synchronization device of the present invention, the following arrangement structure is adopted: each ADC chip in each data acquisition board is connected with the FPGA through a channel clock DCLK line and an LVDS line, the channel clock DCLK line of each ADC chip is equal in length, and the LVDS line of each ADC chip is equal in length.
Further, in order to better realize the multichannel ADC synchronization device of the present invention, the following arrangement structure is adopted: the ADC chip sends a standard test sequence of fixed length at each synchronous clock cycle and sends a first value of the standard test sequence at each synchronous clock rising edge.
Further, in order to better realize the multichannel ADC synchronization device of the present invention, the following arrangement structure is adopted: each FPGA records LVDS link sampling sequence values of all data channels at the current moment at the same moment, and automatically completes the synchronization of the data of a plurality of ADC chips in the board; each FPGA uses one of the DCLK clocks connected to all ADC chips on the FPGA.
Further, in order to better realize the multichannel ADC synchronization device of the present invention, the following arrangement structure is adopted: the data acquisition board sets up M piece, and M is positive integer.
Further, in order to better realize the multichannel ADC synchronization device of the present invention, the following arrangement structure is adopted: n ADC chips are arranged on each data acquisition board, and N is a positive integer.
An automatic synchronization method of a multichannel ADC is realized based on a multichannel ADC synchronization device, and comprises the following steps:
1) The clock synchronization board provides a synchronous clock RCLK and a sampling clock MCLK for the ADC chip and a data processing clock PCLK for the FPGA; each ADC chip outputs an LVDS link and a channel associated clock DCLK to the FPGA; after the clock output of the clock synchronizing plate is stable, configuring all ADC chips to enable the ADC chips to send a standard test sequence on the rising edge of the synchronizing clock RCLK; each LVDS link circularly outputs a standard test sequence, and a first value of the standard test sequence is sent at the rising edge of a synchronous clock RCLK; preferably, when the length of the standard test sequence is l+1, the value of the standard test sequence is { bit0, bit1, bit2, … …, bitL }, where bit0 is the first value of the standard test sequence and L is a natural number;
2) The FPGA of all the data acquisition boards respectively uses the associated clock DCLK at the same position of the data acquisition boards as a clock for sampling the standard test sequence, each FPGA performs data acquisition on all LVDS links on the data acquisition boards at the same time, and no sampling time sequence exists between the FPGA; the FPGA samples the LVDS link to obtain a sequence with the length of a standard test sequence length (L+1), the sequence is recorded as an LVDS link sampling sequence, a first value of the LVDS link sampling sequence adopts any one value of standard test sequences { bit0, bit1, bit2, … … and bitL }, and L is a natural number;
3) Comparing the LVDS link sampling sequence acquired by each FPGA with a standard test sequence { bit0, bit1, bit2, … …, bitL }, namely obtaining an i value by identifying the distance from the first value (bit 0) of each acquired LVDS link sampling sequence to the first value (bit 0) of the standard test sequence;
4) Taking the minimum i value in all LVDS links, and marking the minimum i value as imin; the difference value obtained by subtracting imin from the i value of all LVDS links is the position relative value between sampling sequences of all LVDS links and is recorded as a k value; two adjacent LVDS links, when the position of the first value (bit 0) of the sampling sequence of the last LVDS link (marked as LVDS link 2) is below the bit (L+1)/2 position of the sampling sequence of the previous LVDS link (marked as LVDS link 1), the first value (bit 0) of the sampling sequence of the LVDS link 2 is the same as the distance between the left nearest first value (bit 0) and the right nearest first value (bit 0) of the sampling sequence of the LVDS link 1, so that the first value (bit 0) of the sampling sequence of the LVDS link 2 is not known to move left or right, namely bit displacement motion blur; to avoid bit-shifted motion blur, the delay difference between all LVDS links is required to be less than (l+1)/2 ADC sampling clock cycles.
5) According to the k value of each LVDS link, the FPGA delays the corresponding LVDS link sampling sequence by k bits, so that the delay from the transmission of a standard test sequence by the rising edge of a synchronous clock RCLK to the data output of the FPGA of all LVDS links of all ADC chips in each data acquisition board is a fixed value, namely deterministic delay, and the synchronization of all LVDS link data of all ADC chips in a single data acquisition board is completed;
6) After each acquisition board completes synchronization, taking one LVDS link at the same position of each data acquisition board as a reference LVDS link, and taking k values of the reference LVDS links of each data acquisition board as k0, k1, k2, … … and kM respectively; because the hardware design of the M data acquisition boards is consistent, the time delay of the reference LVDS link from the output end of the ADC chip to the receiving end of the FPGA is the same, and then the LVDS link sampling sequences of the corresponding data acquisition boards are respectively moved by L/2-k0, L/2-k1, L/2-k2 … … and L/2-kM, so that the inter-board synchronization of all the ADC chips is completed.
Compared with the prior art, the invention has the following advantages:
(1) The synchronous device automatically trains the data of the data channels by utilizing the synchronous clock and a standard test sequence generated by the ADC chip, so that the delay values from the sampling points of the ADC chip to the data output of the FPGA are the same; therefore, the automatic synchronization of the phase between channels can be realized without filling signals into the input ends of the ADC chips, and the method is suitable for the synchronization of a plurality of ADC chips in a board and the synchronization of a plurality of ADC chips between boards.
(2) The method utilizes a synchronous clock and a standard test sequence generated by the ADC chips to automatically train the data of the data channels, so that the delay values from the sampling points of the ADC chips to the data output of the FPGA are the same, the channel data synchronization of all the ADC chips connected with a single FPGA is finished, and after the phase synchronization of the ADC chips connected with the FPGA is finished, the phase synchronization of the ADC chips between boards is carried out.
According to the invention, each FPGA records LVDS link sampling sequence values of all data channels at the current moment at the same moment, and the synchronization of channel data of a plurality of ADC chips in a board is automatically completed; each FPGA only needs to use one DCLK clock of all ADC chips connected to the FPGA; no external signal is required to the ADC.
The invention synchronizes the clock rising edge to send the first value of the standard test sequence to the total delay of the FPGA data output to be a fixed value, namely the deterministic delay.
The data acquisition boards independently realize data synchronization, and the data acquisition boards are not mutually interfered.
The invention uses the links at the same position as the reference links synchronously between boards, and each board card moves the LVDS link sampling sequence according to the reference LVDS link.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Fig. 2 is a diagram of an automatic synchronization method according to the present invention.
Fig. 3 is a schematic diagram of an i value in the automatic synchronization method according to the present invention.
Fig. 4 is a schematic diagram of bit-shift motion blur in the automatic synchronization method according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples, but embodiments of the present invention are not limited thereto.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
Example 1:
the invention designs a multichannel ADC synchronous device, which utilizes a synchronous clock and a standard test sequence generated by an ADC chip to automatically train the data of data channels, so that the delay values from the sampling point output of the ADC chip to the data output of an FPGA are the same; therefore, the automatic synchronization of the phase between channels can be realized without filling signals into the input ends of the ADC chips, and the method is suitable for the synchronization of a plurality of ADC chips in a board and the synchronization of a plurality of ADC chips between boards, and comprises a clock synchronization board and at least two data acquisition boards connected with the clock synchronization board, wherein each data acquisition board comprises at least two ADC chips and an FPGA connected with the ADC chips; the clock synchronizing plate provides a synchronous clock and a sampling clock with consistent phases for the data acquisition plate.
Example 2:
the embodiment is further optimized based on the above embodiment, and the same features as the foregoing technical solutions are not described herein, so as to further better implement the multi-channel ADC synchronization device according to the present invention, and particularly, the following arrangement structure is adopted: the clock synchronization board outputs equal length to all ADC chip synchronization clocks RCLK, the clock synchronization board outputs equal length to all ADC chip sampling clocks MCLK, the TRIG_OUT of the clock synchronization board is equal length to all FPGA lines, and the line delay from the data processing clock PCLK of the clock synchronization board to all FPGA lines is not more than one data processing clock PCLK period.
Example 3:
the embodiment is further optimized based on the above embodiment, and the same features as the foregoing technical solutions are not described herein, so as to further better implement the multi-channel ADC synchronization device according to the present invention, and particularly, the following arrangement structure is adopted: each ADC chip in each data acquisition board is connected with the FPGA through a channel clock DCLK line and an LVDS line, the channel clock DCLK line of each ADC chip is equal in length, and the LVDS line of each ADC chip is equal in length.
Example 4:
the embodiment is further optimized based on the above embodiment, and the same features as the foregoing technical solutions are not described herein, so as to further better implement the multi-channel ADC synchronization device according to the present invention, and particularly, the following arrangement structure is adopted: the ADC chip sends a standard test sequence of fixed length at each synchronous clock cycle and sends a first value of the standard test sequence at each synchronous clock rising edge.
Example 5:
the embodiment is further optimized based on the above embodiment, and the same features as the foregoing technical solutions are not described herein, so as to further better implement the multi-channel ADC synchronization device according to the present invention, and particularly, the following arrangement structure is adopted: each FPGA records LVDS link sampling sequence values of all data channels at the current moment at the same moment, and automatically completes the synchronization of the data of a plurality of ADC chips in the board; each FPGA uses one of the DCLK clocks connected to all ADC chips on the FPGA.
Example 6:
the embodiment is further optimized based on the above embodiment, and the same features as the foregoing technical solutions are not described herein, so as to further better implement the multi-channel ADC synchronization device according to the present invention, and particularly, the following arrangement structure is adopted: the data acquisition board is provided with M blocks, and M is a positive integer; n ADC chips are arranged on each data acquisition board, and N is a positive integer.
Example 7:
an automatic synchronization method of a multichannel ADC comprises the following steps:
1) The clock synchronization board provides a synchronous clock RCLK and a sampling clock MCLK for the ADC chip and a data processing clock PCLK for the FPGA; each ADC chip outputs an LVDS link and a channel associated clock DCLK to the FPGA; after the clock output of the clock synchronizing plate is stable, configuring all ADC chips to enable the ADC chips to send a standard test sequence on the rising edge of the synchronizing clock RCLK; each LVDS link cyclically outputs a standard test sequence { bit0, bit1, bit2, … …, bit L } with the length of L+1, and a first value (bit 0) of the standard test sequence is sent on the rising edge of a synchronous clock RCLK;
2) The FPGA of all the data acquisition boards respectively uses the associated clock DCLK at the same position of the data acquisition boards as a clock for sampling the standard test sequence, each FPGA performs data acquisition on all LVDS links on the data acquisition boards at the same time, and no sampling time sequence exists between the FPGA; the FPGA samples the LVDS link to obtain an LVDS link sampling sequence with the length of a standard test sequence length (L+1), wherein a first value of the sequence adopts any one value of a standard test sequence { bit0, bit1, bit2, … … and bitL };
3) Comparing the LVDS link sampling sequence acquired by each FPGA with a standard test sequence { bit0, bit1, bit2, … …, bitL }, namely obtaining an i value by identifying the distance from the first value (bit 0) of each acquired LVDS link sampling sequence to the first value (bit 0) of the standard test sequence;
4) Taking the minimum i value in all LVDS links, and marking the minimum i value as imin; the difference value obtained by subtracting imin from the i value of all LVDS links is the position relative value between sampling sequences of all LVDS links and is recorded as a k value; two adjacent LVDS links, when the position of the first value (bit 0) of the sampling sequence of the last LVDS link (marked as LVDS link 2) is below the bit (L+1)/2 position of the sampling sequence of the previous LVDS link (marked as LVDS link 1), the first value (bit 0) of the sampling sequence of the LVDS link 2 is the same as the distance between the left nearest first value (bit 0) and the right nearest first value (bit 0) of the sampling sequence of the LVDS link 1, so that the first value (bit 0) of the sampling sequence of the LVDS link 2 is not known to move left or right, namely bit displacement motion blur; to avoid bit-shifted motion blur, the delay difference between all LVDS links is required to be less than (l+1)/2 ADC sampling clock cycles.
5) According to the k value of each LVDS link, the FPGA delays the sampling sequence of the LVDS links by k bits, so that the delay from the transmission of a standard test sequence by the rising edge of a synchronous clock RCLK to the data output of the FPGA of all LVDS links of all ADC chips in each data acquisition board is a fixed value, namely deterministic delay, and the synchronization of all LVDS link data of all ADC chips in a single data acquisition board is completed;
6) After each acquisition board completes synchronization, taking one LVDS link at the same position of each data acquisition board as a reference LVDS link, and taking k values of the reference LVDS links of each data acquisition board as k0, k1, k2, … … and kM respectively; because the hardware design of the M data acquisition boards is consistent, the time delay of the reference LVDS link from the output end of the ADC chip to the receiving end of the FPGA is the same, and then the LVDS link sampling sequences of the corresponding data acquisition boards are respectively moved by L/2-k0, L/2-k1, L/2-k2 … … and L/2-kM, so that the inter-board synchronization of all the ADC chips is completed.
Example 8:
the automatic multi-channel ADC synchronization method is realized based on a multi-channel ADC synchronization device, as shown in fig. 1, and the multi-channel ADC synchronization device comprises a clock synchronization plate and M data acquisition plates, wherein the clock synchronization plate is connected with the M data acquisition plates, each data acquisition plate comprises N ADC chips (AD 1-ADN) and 1 FPGA, and all the FPGAs are recorded as (FPGA 1-FPGAM). In order to realize the synchronization of the multi-channel ADC, the clock synchronization plate is required to output equal length to all the RCLK foot lines of the ADC chip synchronization clock, the clock synchronization plate is required to output equal length to all the MCLK foot lines of the ADC chip sampling clock, the TRIG_OUT is required to have equal length to all the FPGA lines, and the line delay from PCLK to all the FPGA is required to be not more than one PCLK period. The channel clock DCLK lines of each ADC chip are equal in length, and the LVDS lines of each ADC chip are equal in length.
Taking an example that the length of the standard test sequence of the ADC is L+1, the automatic synchronization method of the multi-channel ADC synchronization device is shown in the figure 2, and comprises the following steps:
s21 (all ADCs send standard test sequences at the rising edge of RCLK, the length of the standard test sequences is L+1, and the sequence of each LVDS link output standard test sequence is bit0, bit1, bit2, … …, bit L) specifically comprises: the clock synchronization board provides a synchronous clock RCLK and a sampling clock MCLK for the ADC chip and a data processing clock PCLK for the FPGA; each ADC chip outputs an LVDS link and a channel associated clock DCLK to the FPGA; after the clock output of the clock synchronizing plate is stable, configuring all ADC chips to enable the ADC chips to send a standard test sequence on the rising edge of the synchronizing clock RCLK; each LVDS link cyclically outputs a standard test sequence { bit0, bit1, bit2, … …, bit L } with the length of L+1, and a first value (bit 0) of the standard test sequence is sent on the rising edge of a synchronous clock RCLK;
s22 (each FPGA obtains a group of LVDS link sampling sequences from each LVDS link at the same time, compares the obtained LVDS link sampling sequences with standard test sequences (bit 0, bit1, bit2, … … and bitL in sequence to obtain the position relation between the LVDS link sampling sequences and the standard test sequences, and is marked as an i value): the FPGA of all the data acquisition boards respectively uses the associated clock DCLK at the same position of the data acquisition boards as a clock for sampling the standard test sequence, each FPGA performs data acquisition on all LVDS links on the data acquisition boards at the same time, and no sampling time sequence exists between the FPGA; the FPGA samples the LVDS link to obtain an LVDS link sampling sequence with the length of a standard test sequence length (L+1), wherein a first value of the sequence adopts any one value of a standard test sequence { bit0, bit1, bit2, … … and bitL };
as shown in fig. 3, the LVDS link sampling sequence collected by each FPGA is compared with the standard test sequence { bit0, bit1, bit2, … …, bit l }, and the i value is obtained by identifying the distance from the first value (bit 0) of the collected LVDS link sampling sequence to the first value (bit 0) of the standard test sequence;
s23 (the minimum i value in all LVDS links is taken and is marked as imin, the i value in all LVDS links is subtracted by imin to obtain the relative value of the position between sampling sequences of the LVDS links and is marked as k value.) is specifically as follows: taking the minimum i value in all LVDS links, and marking the minimum i value as imin; the difference value obtained by subtracting imin from the i value of all LVDS links is the position relative value between sampling sequences of all LVDS links and is recorded as a k value; as shown in fig. 4, when the position of the first value (bit 0) of the sampling sequence of the next LVDS link (denoted as LVDS link 2) is below the bit (l+1)/2 position of the sampling sequence of the previous LVDS link (denoted as LVDS link 1), the first value (bit 0) of the sampling sequence of the LVDS link 2 is the same as the distance between the nearest first value (bit 0) of the sampling sequence of the LVDS link 1, so that it is not known whether the first value (bit 0) of the sampling sequence of the LVDS link 2 moves to the left or to the right, i.e. bit shift motion blur; to avoid bit-shifted motion blur, the delay difference between all LVDS links is required to be less than (l+1)/2 ADC sampling clock cycles.
S24 (according to the k value of each LVDS link, the FPGA delays the sampling sequence of the LVDS link by k bits, and finally, the deterministic delay from the standard test sequence sent by the rising edge of RCLK to the data output of the FPGA of all LVDS links of the ADC in each acquisition board is realized) is specifically as follows: according to the k value of each LVDS link, the FPGA delays the sampling sequence of the LVDS links by k bits, so that the delay from the transmission of a standard test sequence by the rising edge of a synchronous clock RCLK to the data output of the FPGA of all LVDS links of all ADC chips in each data acquisition board is a fixed value, namely deterministic delay, and the synchronization of all LVDS link data of all ADC chips in a single data acquisition board is completed;
s25 (after each acquisition board completes synchronization, taking one LVDS link at the same position of the acquisition board as a reference to obtain k values of M reference LVDS links, namely k0, k1, k2, … … and kM, respectively, and moving the LVDS link sampling sequences of the corresponding boards by L/2-k0, L/2-k1, L/2-k2, … … and L/2-kM to complete the inter-board synchronization of the ADC) specifically comprises the following steps: after each acquisition board completes synchronization, taking one LVDS link at the same position of each data acquisition board as a reference LVDS link, and taking k values of the reference LVDS links of each data acquisition board as k0, k1, k2, … … and kM respectively; because the hardware design of the M data acquisition boards is consistent, the time delay of the reference LVDS link from the output end of the ADC chip to the receiving end of the FPGA is the same, and then the LVDS link sampling sequences of the corresponding data acquisition boards are respectively moved by L/2-k0, L/2-k1, L/2-k2 … … and L/2-kM, so that the inter-board synchronization of all the ADC chips is completed.
The invention firstly completes the channel data synchronization of all ADC chips connected with a single FPGA: the method comprises the steps that the characteristics that an ADC chip sends a standard test sequence with a fixed length in each synchronous clock period and sends a first value of the standard test sequence at the rising edge of each synchronous clock are utilized, and an FPGA is utilized to record LVDS link sampling sequence values of all links at the current moment at the same moment; and comparing the values of all LVDS link sampling sequences, calculating the relative position relation of all LVDS link sampling sequences, delaying all LVDS link sampling sequences to a buffer release point by using a buffer, and finally completing the alignment of the LVDS link sampling sequences of each channel, so that the total delay from the sending of the first value of the standard test sequence to the data output of the FPGA at the rising edge of the synchronous clock is a fixed value, namely deterministic delay. And finishing deterministic delay of data of all channels (ADC chips), namely finishing phase synchronization among channels of all ADC chips connected with a single FPGA.
After phase synchronization among ADC chip channels connected with an FPGA is completed, the phase synchronization of the ADC chip channels among boards is carried out: because the total delay from the ADC chip output to the FPGA input of the links at the same position of the same board card is the same, the links at the same position of the board card are selected as reference links, and the number of reference links to move can be obtained in the step 1 (synchronization among the ADC chips in the single board), so that the number of reference links to be moved again for obtaining the same delay value is obtained; and the other links of the board card and the reference link of the same board card are moved by the same amount, so that the synchronization of all ADC chip channel data among boards is completed.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modification, equivalent variation, etc. of the above embodiment according to the technical matter of the present invention fall within the scope of the present invention.
Claims (9)
1. A multi-channel ADC synchronization device, characterized in that: the clock synchronous plate and the data acquisition plate are connected with the clock synchronous plate, and the data acquisition plate comprises at least two ADC chips and an FPGA connected with the ADC chips; the clock synchronizing plate provides a synchronous clock and a sampling clock with consistent phases for the data acquisition plate; the multi-channel ADC synchronization device is used for realizing an automatic multi-channel ADC synchronization method and comprises the following steps:
1) The clock synchronization board provides a synchronous clock RCLK and a sampling clock MCLK for the ADC chip and a data processing clock PCLK for the FPGA; each ADC chip outputs an LVDS link and a channel associated clock DCLK to the FPGA; after the clock output of the clock synchronizing plate is stable, configuring all ADC chips to enable the ADC chips to send a standard test sequence on the rising edge of the synchronizing clock RCLK; each LVDS link circularly outputs a standard test sequence, and a first value of the standard test sequence is sent at the rising edge of a synchronous clock RCLK;
2) The FPGA of all the data acquisition boards respectively uses the associated clock DCLK at the same position of the data acquisition boards as a clock for sampling the standard test sequence, each FPGA performs data acquisition on all LVDS links on the data acquisition boards at the same time, and no sampling time sequence exists between the FPGA; the FPGA samples the LVDS link to obtain a sequence with the length equal to the length of a standard test sequence, and the sequence is recorded as an LVDS link sampling sequence, wherein a first value of the LVDS link sampling sequence adopts any value in the standard test sequence;
3) Comparing the LVDS link sampling sequences acquired by each FPGA with a standard test sequence, namely, obtaining an i value by identifying the distance from the first value of each acquired LVDS link sampling sequence to the first value of the standard test sequence;
4) Taking the minimum i value in all LVDS links, and marking the minimum i value as imin; the difference value obtained by subtracting imin from the i value of all LVDS links is the position relative value between sampling sequences of all LVDS links and is recorded as a k value;
5) According to the k value of each LVDS link, the FPGA delays the corresponding LVDS link sampling sequence by k bits, so that the delay from the transmission of a standard test sequence by the rising edge of a synchronous clock RCLK to the data output of the FPGA of all LVDS links of all ADC chips in each data acquisition board is a fixed value, namely deterministic delay, and the synchronization of all LVDS link data of all ADC chips in a single data acquisition board is completed;
6) After each acquisition board completes synchronization, taking one LVDS link at the same position of each data acquisition board as a reference LVDS link, and taking k values of the reference LVDS links of each data acquisition board as k0, k1, k2, … … and kM respectively; and then, respectively moving the LVDS link sampling sequences of the corresponding data acquisition boards by L/2-k0, L/2-k1, L/2-k2 … … and L/2-kM to complete the inter-board synchronization of all the ADC chips.
2. A multi-channel ADC synchronization device according to claim 1, wherein: the clock synchronization board outputs equal length to all ADC chip synchronization clocks RCLK, the clock synchronization board outputs equal length to all ADC chip sampling clocks MCLK, the TRIG_OUT of the clock synchronization board is equal length to all FPGA lines, and the line delay from the data processing clock PCLK of the clock synchronization board to all FPGA lines is not more than one data processing clock PCLK period.
3. A multi-channel ADC synchronization device according to claim 1, wherein: each ADC chip in each data acquisition board is connected with the FPGA through a channel clock DCLK line and an LVDS line, the channel clock DCLK line of each ADC chip is equal in length, and the LVDS line of each ADC chip is equal in length.
4. A multi-channel ADC synchronization device according to claim 1, wherein: the ADC chip sends a standard test sequence of fixed length at each synchronous clock cycle and sends a first value of the standard test sequence at each synchronous clock rising edge.
5. A multi-channel ADC synchronization device according to claim 1, wherein: each FPGA records LVDS link sampling sequence values of all data channels at the current moment at the same moment, and automatically completes the synchronization of the data of a plurality of ADC chips in the board; each FPGA uses one of the DCLK clocks connected to all ADC chips on the FPGA.
6. A multi-channel ADC synchronization device according to claim 1, wherein: the data acquisition board sets up M piece, and M is positive integer.
7. A multi-channel ADC synchronization device according to claim 1, wherein: n ADC chips are arranged on each data acquisition board, and N is a positive integer.
8. A multi-channel ADC synchronization device according to claim 1, wherein: when the length of the standard test sequence is L+1, the value of the standard test sequence is { bit0, bit1, bit2, … …, bit L }, wherein bit0 is the first value of the standard test sequence.
9. A multi-channel ADC synchronization device according to claim 1, wherein: the delay difference between all LVDS links is less than (l+1)/2 ADC chip sampling clock cycles.
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