CN103686990A - Device for achieving clock synchronization - Google Patents

Device for achieving clock synchronization Download PDF

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Publication number
CN103686990A
CN103686990A CN201310666443.XA CN201310666443A CN103686990A CN 103686990 A CN103686990 A CN 103686990A CN 201310666443 A CN201310666443 A CN 201310666443A CN 103686990 A CN103686990 A CN 103686990A
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signal
clock
network
gps
network port
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CN201310666443.XA
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Chinese (zh)
Inventor
邓凯
刘俊
何梁
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Beijing Northern Fiberhome Technologies Co Ltd
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Beijing Northern Fiberhome Technologies Co Ltd
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Priority to CN201310666443.XA priority Critical patent/CN103686990A/en
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Abstract

The embodiment of the invention discloses a device for achieving clock synchronization. The device for achieving clock synchronization is connected with a plurality of base stations through network cables, and comprises network ports and hardware components, wherein the hardware components are used for obtaining at least one path of clock synchronization signals through at least one clock synchronization mode, and the network ports are used for transmitting one path of clock signals of the paths of clock synchronization signals output by the hardware components to the base stations through the network cables. According to the device for achieving clock synchronization, the hardware cost can be reduced.

Description

Realize the device of clock synchronous
Technical field
The present invention relates to mobile communication technology field, particularly relate to the device of realizing clock synchronous.
Background technology
A related major issue of mobile communication network interfaceization is exactly clock synchronization issue.In order to guarantee communication quality, all there is higher requirement base station in mobile communication system to clock synchronous, for example, WCDMA(Wideband Code Division Multiple Access, Wideband Code Division Multiple Access (WCDMA)) and GSM(Global System for Mobile Communications, global system for mobile communications) air interface require the precision of clock synchronous be 0.05ppm(1,000,000/), the precision that CDMA2000 requires clock synchronous is at ± be no more than ± 10us of 3us(maximum).
For traditional TDM(Time-Division Multiplexing, time division multiplexing) transmission group net scheme, base station can be easy to recover synchronizing clock signals from the E1/T1 link of TDM, and can meet well the requirement of base station clock.And for IP data network, cannot support at present the clock of physical layer to transmit, website clock can not obtain from physical layer as traditional scheme, therefore, need to realize by other solution.As, base station is by external GPS/ Beidou antenna receiving satellite signal, and obtain clock sync signal (based on satellite-signal, the GPS/ Big Dipper method of synchronization), or base station receives the PTP(Precision Time Protocol that 1588 main equipments transmit by IP network, Precision Time Protocol) message, and obtain clock sync signal (that is, 1588 methods of synchronization) based on PTP message.
The present inventor finds under study for action, and operator need to arrange for realizing the related hardware parts of clock synchronous on each base station.As, if the GPS/ Big Dipper method of synchronization, the bimodulus module that at least needs to arrange GPS/ Beidou antenna and the GPS/ Big Dipper are used in base station; If 1588 methods of synchronization are used in base station, at least need to arrange 1588 protocol stack modules.This will inevitably increase hardware cost, when multiple synchronization mode is supported in base station simultaneously, more can aggravate the loss of hardware cost especially.
Summary of the invention
In order to solve the problems of the technologies described above, the embodiment of the present invention provides the device of realizing clock synchronous, to reduce hardware cost.
The embodiment of the invention discloses following technical scheme:
Realize a device for clock synchronous, described device is connected by netting twine with a plurality of base stations, and described device comprises the network port and by least one clock synchronization mode, obtains the hardware component of at least one road clock sync signal;
The described network port, for giving a plurality of base stations by described at least one road clock sync signal Zhong mono-tunnel clock signal of described hardware component output by network cable transmission.
Preferably, when adopting the GPS/ Big Dipper method of synchronization, described hardware component comprises: signal receiving antenna and GPS/ Big Dipper bimodulus clock source module;
Described signal receiving antenna, for receiving satellite signal;
Described GPS/ Big Dipper bimodulus clock source module, for described satellite-signal is processed, obtains pulse per second (PPS) 1PPS signal.
Preferably, described device also comprises that GPS/ Big Dipper bimodulus clock keeps module, for set up the conic section of 1PPS signal according to 1PPS signal, and when described GPS/ Big Dipper bimodulus clock source module losing lock, the conic section based on described 1PPS signal obtains 1PPS signal.
Preferably, when adopting 1588 method of synchronization, described hardware component is 1588 protocol stack modules;
Described 1588 protocol stack modules, the Precision Time Protocol PTP message transmitting by IP network for receiving 1588 main equipments, and described PTP message is processed, obtain 1PPS signal.
Preferably, described device is also connected with the base station of Time of Day TOD signal is provided, the described network port also for, by described TOD signal, by network cable transmission, give a plurality of base stations.
Preferably, the netting twine that described netting twine is return network, the described network port is return network port.
Preferably, described return network port specifically for, time end that described 1PPS signal is modulated to the network transformer that is positioned at described device side is upper, and described 1PPS signal receives in the source of network transformer that is positioned at base station side.
Preferably, described return network port specifically for, adopt asynchronous mode that described TOD signal is transferred to base station.
Preferably, described device also comprises FPGA module, for calculating the clock accuracy of at least one clock synchronization mode, from described at least one road clock sync signal of described hardware component output, select the clock sync signal obtaining by the highest clock synchronization mode of clock accuracy, and export to the described network port.
Preferably, the netting twine of described return network is Category-5 twisted pair.
As can be seen from the above-described embodiment, compared with prior art, the invention has the advantages that:
By being originally positioned at inside of base station, for realizing the related hardware parts of clock synchronous, transfer to a network node equipment,, on an apparatus for network node, arrange the related hardware parts of realizing clock synchronous, after network node equipment obtains at least one road clock sync signal by relevant hardware component, by the netting twine between itself and each base station wherein a road clock sync signal be transferred to base station, clock synchronous is carried out according to clock unlike signal in each base station.
Like this, not only can save hardware cost, meanwhile, because the signal receiving antenna in hardware component is only positioned on a network node equipment, more easily guarantee that signal receiving antenna can successfully receive satellite-signal, thereby also just improved the accuracy of clock synchronous.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structure chart of an execution mode of a kind of device of realizing clock synchronous of the present invention;
Fig. 2 is the structure chart of another execution mode of a kind of device of realizing clock synchronous of the present invention;
Fig. 3 realizes the schematic diagram communicating by Category-5 twisted pair between the device of clock synchronous and base station in the present invention;
Fig. 4 is the structure chart of another execution mode of a kind of device of realizing clock synchronous of the present invention.
Embodiment
The embodiment of the present invention provides the device of realizing clock synchronous.The core of technical solution of the present invention is, by being originally positioned at inside of base station, for realizing the related hardware parts of clock synchronous, transfers to a network node equipment, like this, only need on a network node equipment, arrange relevant hardware component.Meanwhile, at each inside of base station, only remain with synchronization module.After network node equipment obtains at least one road clock sync signal by relevant hardware component, by the netting twine between itself and each base station wherein a road clock sync signal be transferred to base station, clock synchronous is carried out according to clock unlike signal in each base station.
Like this, not only can save hardware cost, meanwhile, because the signal receiving antenna in hardware component is only positioned on a network node equipment, more easily guarantee that signal receiving antenna can successfully receive satellite-signal, thereby also just improved the accuracy of clock synchronous.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.
The device of realizing clock synchronous of take below supports that the GPS/ Big Dipper method of synchronization and 1588 methods of synchronization are example simultaneously, and technical scheme of the present invention is described.Now, the hardware component that is arranged in this device comprises signal receiving antenna (specifically comprising gps antenna and Beidou antenna) and GPS/ Big Dipper bimodulus clock source module, and 1588 protocol stack modules.
Specifically refer to Fig. 1, the structure chart of an execution mode of the device that it realizes clock synchronous for the present invention is a kind of, this device 10 is connected by netting twine with a plurality of base stations 20, and this device 10 comprises gps antenna 11, Beidou antenna 12, GPS/ Big Dipper bimodulus clock source module 13,1588 protocol stack modules 14 and the network port 15.Operation principle below in conjunction with this device is further introduced its internal structure and annexation.
Gps antenna 11, for receiving gps satellite signal;
Beidou antenna 12, for receiving Big Dipper satellite signal;
GPS/ Big Dipper bimodulus clock source module 13, for described gps satellite signal is processed, obtains 1PPS(1 Pluse Per Second, pulse per second (PPS)) signal, or, described bucket satellite-signal is processed, obtain 1PPS signal;
1588 protocol stack modules 14, for the PTP message that reception 1588 main equipments are transmitted by IP network, and process described PTP message, obtain 1PPS signal;
The network port 15, for giving a plurality of base stations 20 by the 1PPS signal of the 1PPS signal of GPS/ Big Dipper bimodulus clock source module 13 outputs or 1588 protocol stack module 14 outputs by network cable transmission.
In first preferred implementation of the present invention, consult shown in Fig. 2, this device 10 also comprises that GPS/ Big Dipper bimodulus clock keeps module 16, for set up the conic section of 1PPS signal according to 1PPS signal, and when described GPS/ Big Dipper bimodulus clock source module losing lock, the conic section based on described 1PPS signal obtains 1PPS signal.
Now, the network port 15, for keeping the GPS/ Big Dipper bimodulus clock 1PPS signal of module 16 outputs or the 1PPS signal of 1588 protocol stack module 14 outputs to give a plurality of base stations 20 by network cable transmission.
In second preferred implementation of the present invention, described device also with TOD(Time Of Day, Time of Day are provided) base station of signal connects, the described network port also for, by described TOD signal, by network cable transmission, give a plurality of base stations.
In the 3rd preferred implementation of the present invention, the netting twine that described netting twine is return network, the described network port is return network port.
In the 4th preferred implementation of the present invention, described return network port specifically for, time end that described 1PPS signal is modulated to the network transformer that is positioned at described device side is upper, and described 1PPS signal receives in the source of network transformer that is positioned at base station side.
In the 5th preferred implementation of the present invention, described return network port specifically for, adopt asynchronous mode that described TOD signal is transferred to base station.
In the 6th preferred implementation of the present invention, the netting twine of return network is Category-5 twisted pair.
Wherein, the Category-5 twisted pair of standard has four pairs of twisted-pair feeders, that is, and and 1-2,3-6,4-5 and 7-8.Can on a twisted-pair feeder in any a pair of twisted-pair feeder, transmit 1PPS signal.In order effectively to avoid the interference of 1PPS signal in transmitting procedure, as preferred execution mode, can the 1PPS signal of difference be transferred to base station by a pair of twisted-pair feeder.
In addition, in order to improve transmission range, in the 7th preferred implementation of the present embodiment, from the 1PPS signal of GPS/ Big Dipper bimodulus clock source module output, further by 422 chips, carry out level conversion processing, after processing, by Category-5 twisted pair, be transferred to base station again.
Refer to Fig. 3, it is for realizing the schematic diagram communicating by Category-5 twisted pair between the device of clock synchronous and base station in the present invention.
In the 7th preferred implementation of the present invention, consult shown in Fig. 4, this device 10 also comprises FPGA module 17, for calculating the clock accuracy of at least one clock synchronization mode, from described at least one road clock sync signal of described hardware component output, select the clock sync signal obtaining by the highest clock synchronization mode of clock accuracy, and export to the described network port.
For example, the precision synchronous due to GPS/ big dipper clock is relatively high, and FPGA module preferably adopts the 1PPS signal of GPS/ Big Dipper bimodulus clock source module output.Wherein, the quantity of the quantity of the satellite that FPGA block search arrives and the satellite of locking, which is higher to determine gps clock is synchronous and big dipper clock is synchronous precision, and selects.If source module losing lock during GPS/ Big Dipper bimodulus, FPGA module surveys whether there is the input of TOD signal, if there is the input of TOD signal, select TOD signal, if there is no the input of TOD signal, whether FPGA module continues to survey 1588 protocol stack modules the output of 1PPS signal, if there is the output of 1PPS signal, FPGA module is selected the 1PPS signal of 1588 protocol stack outputs, if there is no the output of 1PPS signal, FPGA module is surveyed GPS/ Big Dipper bimodulus clock and is kept module whether to have the output of 1PPS signal, if having, adopts GPS/ Big Dipper bimodulus clock to keep the 1PPS signal of module output.
If it is normal that any one or a few in the GPS/ Big Dipper method of synchronization, 1588 methods of synchronization and the TOD method of synchronization recovers, according to priority level as above, switch back corresponding clock signal, and exit the hold mode under GPS/ Big Dipper bimodulus clock maintenance module.
By FPGA module, the clock synchronization mode on apparatus for network node can manual configuration be selected by operator, also can by 485 interfaces, send the clock synchronization mode that network node equipment is selected in order by base station, and other relevant information of reception, as, the latitude and longitude information comprising in gps signal etc.
As can be seen from the above-described embodiment, compared with prior art, the invention has the advantages that:
By being originally positioned at inside of base station, for realizing the related hardware parts of clock synchronous, transfer to a network node equipment,, on an apparatus for network node, arrange the related hardware parts of realizing clock synchronous, after network node equipment obtains at least one road clock sync signal by relevant hardware component, by the netting twine between itself and each base station wherein a road clock sync signal be transferred to base station, clock synchronous is carried out according to clock unlike signal in each base station.
Like this, not only can save hardware cost, meanwhile, because the signal receiving antenna in hardware component is only positioned on a network node equipment, more easily guarantee that signal receiving antenna can successfully receive satellite-signal, thereby also just improved the accuracy of clock synchronous.
The technical staff in described field can be well understood to, and with succinct, the specific works process of the system of foregoing description, device and unit, can, with reference to the corresponding process in preceding method embodiment, not repeat them here for convenience of description.
In several embodiment provided by the present invention, should be understood that disclosed system, apparatus and method can realize by another way.For example, described above to device embodiment be only schematic, for example, the division of described unit, be only that a kind of logic function is divided, during actual realization, can have other dividing mode, for example a plurality of unit or assembly can be in conjunction with being maybe integrated into another system, or some features can ignore, or do not carry out.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, indirect coupling or the communication connection of device or unit can be electrical, mechanical or other form.
The described unit as separating component explanation can or can be also physically to separate, and the parts that show as unit can be or can not be also physical locations, can be positioned at a place, or also can be distributed in a plurality of network element.Can select according to the actual needs some or all of unit wherein to realize the object of the present embodiment scheme.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, can be also that the independent physics of unit exists, and also can be integrated in a unit two or more unit.Above-mentioned integrated unit both can adopt the form of hardware to realize, and can adopt the form of SFU software functional unit to realize.
It should be noted that, one of ordinary skill in the art will appreciate that all or part of flow process realizing in above-described embodiment method, to come the hardware that instruction is relevant to complete by computer program, described program can be stored in a computer read/write memory medium, this program, when carrying out, can comprise as the flow process of the embodiment of above-mentioned each side method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or random store-memory body (Random Access Memory, RAM) etc.
Above the device of realizing clock synchronous provided by the present invention is described in detail, applied specific embodiment herein principle of the present invention and execution mode are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.

Claims (10)

1. a device of realizing clock synchronous, is characterized in that, described device is connected by netting twine with a plurality of base stations, and described device comprises the network port and by least one clock synchronization mode, obtains the hardware component of at least one road clock sync signal;
The described network port, for giving a plurality of base stations by described at least one road clock sync signal Zhong mono-tunnel clock signal of described hardware component output by network cable transmission.
2. device according to claim 1, is characterized in that, when adopting the GPS/ Big Dipper method of synchronization, described hardware component comprises: signal receiving antenna and GPS/ Big Dipper bimodulus clock source module;
Described signal receiving antenna, for receiving satellite signal;
Described GPS/ Big Dipper bimodulus clock source module, for described satellite-signal is processed, obtains pulse per second (PPS) 1PPS signal.
3. device according to claim 2, it is characterized in that, described device also comprises that GPS/ Big Dipper bimodulus clock keeps module, for set up the conic section of 1PPS signal according to 1PPS signal, and when described GPS/ Big Dipper bimodulus clock source module losing lock, the conic section based on described 1PPS signal obtains 1PPS signal.
4. device according to claim 1, is characterized in that, when adopting 1588 method of synchronization, described hardware component is 1588 protocol stack modules;
Described 1588 protocol stack modules, the Precision Time Protocol PTP message transmitting by IP network for receiving 1588 main equipments, and described PTP message is processed, obtain 1PPS signal.
5. device according to claim 1, is characterized in that, described device is also connected with the base station of Time of Day TOD signal is provided, the described network port also for, by described TOD signal, by network cable transmission, give a plurality of base stations.
6. device according to claim 1, is characterized in that, the netting twine that described netting twine is return network, and the described network port is return network port.
7. device according to claim 6, it is characterized in that, described return network port specifically for, by described 1PPS signal be modulated at be positioned at described device side network transformer time end on, and described 1PPS signal receives in the source of network transformer that is positioned at base station side.
8. switch according to claim 6, is characterized in that, described return network port specifically for, adopt asynchronous mode that described TOD signal is transferred to base station.
9. device according to claim 1, it is characterized in that, described device also comprises FPGA module, for calculating the clock accuracy of at least one clock synchronization mode, from described at least one road clock sync signal of described hardware component output, select the clock sync signal obtaining by the highest clock synchronization mode of clock accuracy, and export to the described network port.
10. according to the switch described in any one in claim 1 to 9, it is characterized in that, the netting twine of described return network is Category-5 twisted pair.
CN201310666443.XA 2013-12-10 2013-12-10 Device for achieving clock synchronization Pending CN103686990A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015196696A1 (en) * 2014-06-26 2015-12-30 中兴通讯股份有限公司 Clock synchronization method, radio remote unit, building base band unit and base station
CN105388454A (en) * 2015-10-16 2016-03-09 四川中电昆辰科技有限公司 Quasi-synchronization structure, positioning device and positioning method thereof
CN106353728A (en) * 2016-08-23 2017-01-25 四川中电昆辰科技有限公司 Method of ranging and positioning based on optical synchronization signal and devices thereof
CN107247277A (en) * 2017-07-05 2017-10-13 京信通信系统(中国)有限公司 GPS/ Big Dipper dual mode datas shunt, branch control system and branch control method
CN109738759A (en) * 2019-01-24 2019-05-10 国网河北省电力有限公司沧州供电分公司 A kind of earth mesh conductive state nondestructive detection system and method
CN112333719A (en) * 2020-10-23 2021-02-05 深圳国人无线通信有限公司 Synchronization method and synchronization system of 5G small base station based on x86 server

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110002429A1 (en) * 2008-02-29 2011-01-06 Audinate Pty Ltd Network devices, methods and/or systems for use in a media network
WO2012119385A1 (en) * 2011-08-11 2012-09-13 华为技术有限公司 Method, device and system for performing time synchronization on pcie device
CN103188066A (en) * 2013-02-28 2013-07-03 中兴通讯股份有限公司 Reference clock signal processing method and device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110002429A1 (en) * 2008-02-29 2011-01-06 Audinate Pty Ltd Network devices, methods and/or systems for use in a media network
WO2012119385A1 (en) * 2011-08-11 2012-09-13 华为技术有限公司 Method, device and system for performing time synchronization on pcie device
CN103188066A (en) * 2013-02-28 2013-07-03 中兴通讯股份有限公司 Reference clock signal processing method and device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015196696A1 (en) * 2014-06-26 2015-12-30 中兴通讯股份有限公司 Clock synchronization method, radio remote unit, building base band unit and base station
CN105207765A (en) * 2014-06-26 2015-12-30 中兴通讯股份有限公司 Clock synchronization method, radio frequency remote unit, baseband processing unit and base station
CN105388454A (en) * 2015-10-16 2016-03-09 四川中电昆辰科技有限公司 Quasi-synchronization structure, positioning device and positioning method thereof
CN106353728A (en) * 2016-08-23 2017-01-25 四川中电昆辰科技有限公司 Method of ranging and positioning based on optical synchronization signal and devices thereof
CN107247277A (en) * 2017-07-05 2017-10-13 京信通信系统(中国)有限公司 GPS/ Big Dipper dual mode datas shunt, branch control system and branch control method
CN109738759A (en) * 2019-01-24 2019-05-10 国网河北省电力有限公司沧州供电分公司 A kind of earth mesh conductive state nondestructive detection system and method
CN112333719A (en) * 2020-10-23 2021-02-05 深圳国人无线通信有限公司 Synchronization method and synchronization system of 5G small base station based on x86 server

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