CN102868406A - Multichannel high-speed parallel alternate ADC (Analog to Digital Converter) sampling circuit - Google Patents
Multichannel high-speed parallel alternate ADC (Analog to Digital Converter) sampling circuit Download PDFInfo
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- CN102868406A CN102868406A CN201210339516XA CN201210339516A CN102868406A CN 102868406 A CN102868406 A CN 102868406A CN 201210339516X A CN201210339516X A CN 201210339516XA CN 201210339516 A CN201210339516 A CN 201210339516A CN 102868406 A CN102868406 A CN 102868406A
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Abstract
The invention provides a multichannel high-speed parallel alternate ADC (Analog to Digital Converter) sampling circuit, which comprises an analog differential signal input module, a clock generating and phase-splitting module, a parallel ADC module and a data transmission module, wherein each data output end of the analog differential signal input module is connected with each corresponding data input end in the parallel ADC module; each clock output end of the clock generating and phase-splitting module is connected with each corresponding clock input end in the parallel ADC module, and each data output end of the parallel ADC module is connected with the data transmission module; and a phase splitting unit consists of passive power divider, wherein each passive power divider is used for equally dividing an input clock phase and then outputting the input clock phase. The multichannel high-speed parallel alternate ADC sampling circuit finishes the phase splitting on a clock signal by using the passive power dividers, is little interfered because no power supply is needed for supplying power, and has high phase-splitting precision on the clock signal and small clock jitter.
Description
Technical field
The present invention relates to time-interleaved ADC(analog-digital converter) data acquisition technology.
Background technology
Any one signal chains system all needs transducer to survey the signals such as voltage from simulated world, electric current, temperature, pressure.The semaphore that these transducers detect is sent in the amplifier and amplifies, then by ADC analog signal is converted into digital signal, utilize processor, DSP(digital signal processor) or the FPGA(field programmable gate array) digital signal is processed, come noise or the distortion of information extraction or erasure signal.For the application that high speed signal is processed, the switching rate of ADC remains the bottleneck of a key, and this is because converter design at a high speed is subject to the restriction of hardware.Therefore, according to present IC(integrated circuit) design technology, realize sampling rate more at a high speed.At present, a kind of important way that realizes that ultrahigh speed is sampled is utilized the ADC of time-interleaved (Time-interleaved) structure exactly.The ADC of this structure utilizes the ADC chip parallel sampling of the relative low speed of multi-disc to realize superfast sample rate.
Multi-disc ADC parallel acquisition technique mainly is divided into two large classes: a class is the time-interleaved parallel acquisition technique (TIADC) of time domain, and another kind of is the parallel acquisition technique based on the dividing frequency band bank of filters of frequency domain.Based on the ADC parallel acquisition technique service band cutting techniques of bank of filters, to cut apart filter and usually adopt analog low-pass, band to lead to and high pass filter, its transition band has a great impact systematic function.Owing to realizing difficulty, also being at present the research experiment stage.And the TIADC parallel acquisition technique has become the main flow of ADC parallel acquisition technique because implementation is simple, is the main means that improve the ADC sample rate.
Time alternative ADC comprises M parallel sub-ADC, with reference to figure 1, and M=4, the sub-ADC of each passage Sub-ADC() there is sampling separately to keep front end, they are sampled to same input signal successively.After finally alternately closing the road, overall sampling rate f
sBe the M of sub-ADC doubly.In the ideal case, under the same input signal, the conversion accuracy of time alternative ADC should be consistent with the Sub-ADC performance.
Yet in side circuit, the shake of each Sub-ADC sampling clock, deviation all can cause the decline of the overall conversion accuracy of ADC after time-interleaved.
Time alternative ADC is mainly considered offset error, gain error, time error and bandwidth error etc. at present.The development of these error effect time alternative ADCs, the design of multi-channel high-speed parallel alternative ADC sampling circuit board is particularly important, how to reduce the mismatch error of time alternative ADC system, and is helpful to the performance raising of whole system.
Summary of the invention
Technical problem to be solved by this invention is to provide the generation of a kind of energy to wait the high-speed parallel alternative ADC sample circuit of minute phase place high-performance clock.
The present invention solves the problems of the technologies described above the technical scheme that adopts to be, a kind of multi-channel high-speed parallel alternative ADC sample circuit, comprise analog difference signal input module, clock generating and minute phase module, Parallel ADC module, data transmission module, each corresponding in each data output end of analog difference signal input module and Parallel ADC module data input pin links to each other, each corresponding in each output terminal of clock of clock generating and minute phase module and Parallel ADC module input end of clock links to each other, and each data output end of Parallel ADC module links to each other with data transmission module; Clock generating and a minute phase module comprise clock generating unit, minute facies unit, single-ended transfer difference unit, the output of clock generating unit links to each other with the input of minute facies unit, divide single-ended transfer difference unit of the corresponding connection of each output of facies unit, the output of each single-ended transfer difference unit is each output terminal of clock of clock generating and minute phase module;
It is characterized in that, facies unit was comprised of the Passive Power distributor in described minute, exported behind the clock phase five equilibrium of Passive Power distributor with input.
Concrete, when the ADC sample circuit was 2 passage, a minute facies unit was 3 Passive Power distributors, and the Passive Power distributor is exported after the clock signal of input being divided into the clock signal of 2 road phase differences, 180 degree.
Concrete, when the ADC sample circuit was 4 passage, a minute facies unit formed 2 grades of phase-splittings by 3 Passive Power distributors; Finish first order phase-splitting by 1 Passive Power distributor, export the 2nd grade of phase-splitting to after the clock signal of input being divided into the clock signal of 2 road phase differences 180 degree; Finish second level phase-splitting by 2 Passive Power distributors, 2 Passive Power distributors of second level phase-splitting are exported after respectively the clock signal of input being divided into the clock signal of 2 road phase differences 90 degree.
The invention has the beneficial effects as follows, use Passive Power distributor is finished the phase-splitting to clock signal, owing to not needing Power supply, it is disturbed less, and high to clock signal phase-splitting accuracy, clock jitter is little.
Description of drawings
Fig. 1 is the theory diagram of four-way timesharing alternative ADC;
Fig. 2 is embodiment 4 channel parallel alternative ADC schematic block circuit diagram.
Embodiment
The alternative ADC of four-way timesharing herein circuit is example, but is not limited to four-way.As shown in Figure 2, four-way timesharing alternative ADC sample circuit comprises 4 parts: analog difference signal input module, clock generating and minute phase module, Parallel ADC module, data transmission module.Each corresponding in each data output end of analog difference signal input module and Parallel ADC module data input pin links to each other, each corresponding in each output terminal of clock of clock generating and minute phase module and Parallel ADC module input end of clock links to each other, and each data output end of Parallel ADC module links to each other with data transmission module; Clock generating and a minute phase module comprise clock generating unit, minute facies unit, single-ended transfer difference unit, the output of clock generating unit links to each other with the input of minute facies unit, divide single-ended transfer difference unit of the corresponding connection of each output of facies unit, the output of each single-ended transfer difference unit is each output terminal of clock of clock generating and minute phase module.
1) analog difference signal input module:
Will be from the SMA(wireless aerial) mouthful the analog signal of original input be divided into treat parallel processing 4 tunnel analog signals along separate routes, transfer the single-ended signal of 4 road signals on along separate routes to differential signal and export the Parallel ADC module to.The shunt of analog signal and single-ended transfer difference all have multiple prior art to select, and do not give unnecessary details at this.
2) clock generating and minute phase module:
The power divider that to adopt 1 model be AMT-2 is as first order phase-splitting, the sampling clock (0 degree and 180 degree) that will be divided into from the clock of SMA mouth 2 road phase differences, 180 degree, adopting model is that 2 power dividers of SCPQ-150 are as second level phase-splitting, produce the sampling clock (0 degree, 90 is spent, 180 degree, 270 are spent) of 4 tunnel phase phasic differences, 90 degree, 4 the tunnel to divide the single-ended transfer difference unit that connects on the output of facies unit to adopt model be the transformer of ADT1-1WT, with clock signal single-ended signal slip sub-signal.
For the situation of two passages, only need the Passive Power distributor AMT-2 of two phase-splittings to get final product.
3) Parallel ADC module:
Comprise 4 ADC, the high-speed ADC device that it is AD9233 that the present embodiment adopts 4 models of AD company comes parallel sampling, guarantees that the peripheral circuit step line of every a slice ADC is isometric, and impedance matching is identical, reduces because placement-and-routing causes does not interchannelly mate.Adopt model to provide unified external reference voltage for the ADR441 power supply chip for 4 ADC, the data output process model of ADC is that the buffer of 74VCX16244 carries out data buffering, strengthens the signal driver ability by raising level signal.The input signal of each ADC is identical.
4) data transmission module:
Process in this enforcement and comprise data buffer storage unit, data transmission unit, data test unit.Data buffer storage unit is used for the asynchronous clock data that buffer memory comes from the Parallel ADC module.Data transmission unit is used for the road is closed in the output of each sub-ADC, the output of generation system.The data test unit is in order to make things convenient in the development process logic analyzer to the test of data.
Data transmission module comprises that a model is the FPGA of EP2C35672, the download chip that model is EPC8QI100, a download interface, a HSMC interface, a surface mounting plug interface, FPGA receives output data and the clock of Parallel ADC module, with deposit data in the FIFO(of inside first in first out) in the cache blocks, and coexistence 64KBytes is equivalent to the data of each road 16KBytes, then reading out data is delivered to HSMC interface and surface mounting plug interface, fifo module is realized the function of asynchronous clock data buffer storage, and can guarantee to align on the data time sequence on each road, avoid occurring loss of data.The HSMC interface can conveniently be realized transfer of data with the external FPGA development board that is mainly used in digital calibration.The surface mounting plug interface both can make things convenient for the logic analyzer test, can realize transfer of data again.
When designing based on ADC sampling circuit board of the present invention, in order further to guarantee the high accuracy low jitter of clock signal, clock generating and the device that minute phase module relates to are put in the PCB(printed circuit) the plate top layer, the device that the analog difference signal input module is related to is put in the PCB(printed circuit) the plate bottom, can avoid like this phase mutual interference and impact between clock and the signal.
Based on the actual testing authentication of ADC sampling circuit board process of ADC sample circuit design of the present invention, the tester of employing mainly contains stabilized voltage power supply instrument, signal generator, high-performance clock generator, oscilloscope, logic analyzer, FPGA development board, data acquisition board, PC.According to testing result, can satisfy the requirement of TIADC raising systematic sampling rate based on the ADC sampling circuit board of ADC sample circuit design of the present invention.
Claims (6)
1. multi-channel high-speed parallel alternative ADC sample circuit, comprise analog difference signal input module, clock generating and minute phase module, Parallel ADC module, data transmission module, each corresponding in each data output end of analog difference signal input module and Parallel ADC module data input pin links to each other, each corresponding in each output terminal of clock of clock generating and minute phase module and Parallel ADC module input end of clock links to each other, and each data output end of Parallel ADC module links to each other with data transmission module; Clock generating and a minute phase module comprise clock generating unit, minute facies unit, single-ended transfer difference unit, the output of clock generating unit links to each other with the input of minute facies unit, divide single-ended transfer difference unit of the corresponding connection of each output of facies unit, the output of each single-ended transfer difference unit is each output terminal of clock of clock generating and minute phase module;
It is characterized in that, facies unit was comprised of the Passive Power distributor in described minute, exported behind the clock phase five equilibrium of Passive Power distributor with input.
2. a kind of multi-channel high-speed parallel alternative ADC sample circuit as claimed in claim 1, it is characterized in that, when the ADC sample circuit was 2 passage, a minute facies unit was 3 Passive Power distributors, and the Passive Power distributor is exported after the clock signal of input being divided into the clock signal of 2 road phase differences, 180 degree.
3. a kind of multi-channel high-speed parallel alternative ADC sample circuit as claimed in claim 1 is characterized in that, when the ADC sample circuit was 4 passage, a minute facies unit formed 2 grades of phase-splittings by 3 Passive Power distributors; Finish first order phase-splitting by 1 Passive Power distributor, export the 2nd grade of phase-splitting to after the clock signal of input being divided into the clock signal of 2 road phase differences 180 degree; Finish second level phase-splitting by 2 Passive Power distributors, 2 Passive Power distributors of second level phase-splitting are exported after respectively the clock signal of input being divided into the clock signal of 2 road phase differences 90 degree.
4. a kind of multi-channel high-speed parallel alternative ADC sample circuit as claimed in claim 1, it is characterized in that, described Parallel ADC module comprises 1 power supply chip, an integral multiple ADC of 2 and the buffer of equal number, the output of ADC links to each other with the output of corresponding buffer, each ADC power supply of power supply chip provides unified external reference voltage.
5. a kind of multi-channel high-speed parallel alternative ADC sample circuit as claimed in claim 1 is characterized in that, data transmission module comprises data buffer storage unit, data transmission unit; Data buffer storage unit is used for the asynchronous clock data that buffer memory comes from the Parallel ADC module; Data transmission unit is used for the road is closed in the output of each sub-ADC, the output of generation system.
6. a kind of multi-channel high-speed parallel alternative ADC sample circuit as claimed in claim 1 is characterized in that, data transmission module comprises the data test unit, is used for the development process logic analyzer to the test of data.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734710A (en) * | 2015-03-11 | 2015-06-24 | 上海华岭集成电路技术股份有限公司 | Test system for ADC chip characteristic parameter test precision |
| CN104883653A (en) * | 2014-02-27 | 2015-09-02 | 广州思林杰网络科技有限公司 | Audio frequency tester, method of measuring and uploading data through the tester |
| CN106054118A (en) * | 2016-05-24 | 2016-10-26 | 中国民用航空总局第二研究所 | High-speed sampling method and high-speed sampling system for navigation equipment online measurement |
| CN106154907A (en) * | 2016-06-15 | 2016-11-23 | 北京航空航天大学 | A kind of high speed high-accuracy data collection system based on time interleaving sampling |
| CN107124185A (en) * | 2017-04-10 | 2017-09-01 | 中山大学 | A kind of data buffer storage and playback system of time-interleaved A/D conversion system |
| CN107727930A (en) * | 2017-12-02 | 2018-02-23 | 陈景尧 | Intelligent high-precision analog signal sampling system and the method for sampling |
| CN108390673A (en) * | 2018-02-05 | 2018-08-10 | 佛山市顺德区中山大学研究院 | A kind of high-speed ADC interleave samples system |
| CN108616279A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of low jitter multichannel intermediate-freuqncy signal acquisition clock circuit |
| CN111342841A (en) * | 2020-03-10 | 2020-06-26 | 西南科技大学 | Reconfigurable multi-channel signal acquisition and transmission system |
| CN112698094A (en) * | 2020-12-04 | 2021-04-23 | 中山大学 | Multi-channel multi-acquisition-mode high-speed acquisition system and method |
| RU206989U1 (en) * | 2021-06-30 | 2021-10-05 | Российская Федерация, От Имени Которой Выступает Министерство Промышленности И Торговли Российской Федерации | Mezzanine analog-to-digital converter (ADC) module |
| CN113890539A (en) * | 2021-12-07 | 2022-01-04 | 深圳市爱普特微电子有限公司 | Multi-channel analog input circuit for ADC module |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883653A (en) * | 2014-02-27 | 2015-09-02 | 广州思林杰网络科技有限公司 | Audio frequency tester, method of measuring and uploading data through the tester |
| CN104883653B (en) * | 2014-02-27 | 2019-01-18 | 广州思林杰网络科技有限公司 | A kind of audio-frequency test instrument and use method tester measurement, upload data |
| CN104734710A (en) * | 2015-03-11 | 2015-06-24 | 上海华岭集成电路技术股份有限公司 | Test system for ADC chip characteristic parameter test precision |
| CN106054118A (en) * | 2016-05-24 | 2016-10-26 | 中国民用航空总局第二研究所 | High-speed sampling method and high-speed sampling system for navigation equipment online measurement |
| CN106054118B (en) * | 2016-05-24 | 2018-08-03 | 中国民用航空总局第二研究所 | The high-speed sampling method and system of navigation equipment on-line measurement |
| CN106154907B (en) * | 2016-06-15 | 2018-08-14 | 北京航空航天大学 | A kind of high speed high-accuracy data collection system based on time interleaving sampling |
| CN106154907A (en) * | 2016-06-15 | 2016-11-23 | 北京航空航天大学 | A kind of high speed high-accuracy data collection system based on time interleaving sampling |
| CN108616279A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of low jitter multichannel intermediate-freuqncy signal acquisition clock circuit |
| CN107124185A (en) * | 2017-04-10 | 2017-09-01 | 中山大学 | A kind of data buffer storage and playback system of time-interleaved A/D conversion system |
| CN107727930A (en) * | 2017-12-02 | 2018-02-23 | 陈景尧 | Intelligent high-precision analog signal sampling system and the method for sampling |
| CN108390673A (en) * | 2018-02-05 | 2018-08-10 | 佛山市顺德区中山大学研究院 | A kind of high-speed ADC interleave samples system |
| CN111342841A (en) * | 2020-03-10 | 2020-06-26 | 西南科技大学 | Reconfigurable multi-channel signal acquisition and transmission system |
| CN112698094A (en) * | 2020-12-04 | 2021-04-23 | 中山大学 | Multi-channel multi-acquisition-mode high-speed acquisition system and method |
| RU206989U1 (en) * | 2021-06-30 | 2021-10-05 | Российская Федерация, От Имени Которой Выступает Министерство Промышленности И Торговли Российской Федерации | Mezzanine analog-to-digital converter (ADC) module |
| CN113890539A (en) * | 2021-12-07 | 2022-01-04 | 深圳市爱普特微电子有限公司 | Multi-channel analog input circuit for ADC module |
| CN113890539B (en) * | 2021-12-07 | 2022-03-15 | 深圳市爱普特微电子有限公司 | Multi-channel analog input circuit for ADC module |
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Application publication date: 20130109 |